JP5727355B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which prevents direct current afterimages and flickers to improve display quality and a driving method thereof.

  The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal cell according to a video signal. As shown in FIG. 1, an active matrix type liquid crystal display device switches a data voltage supplied to a liquid crystal cell using a thin film transistor (TFT) formed for each liquid crystal cell (Clc). Since the data is actively controlled, the display quality of the moving image can be improved. In FIG. 1, “Cst” is a storage capacitor (Storage Capacitor, Cst) for maintaining a data voltage charged in a liquid crystal cell (Clc), “DL1” is a data line to which a data voltage is supplied, and “ GL1 ′ means a gate line to which a scan voltage is supplied.

  Such a liquid crystal display device adopts an inversion method in which the polarity is inverted between adjacent liquid crystal cells and the polarity is inverted in units of frame periods in order to reduce the DC offset component and reduce the deterioration of the liquid crystal. It is driven. By the way, if any one of the two polarities of the data voltage is supplied dominantly for a long time, an afterimage is generated. Such an afterimage is called “DC image sticking” because a voltage of the same polarity is repeatedly charged in the liquid crystal cell. One of such examples is a case where an interlaced data voltage is supplied to the liquid crystal display device. Interlaced data (hereinafter referred to as “interlaced data”) includes only odd line data voltages displayed in odd horizontal line liquid crystal cells in odd frame periods and is displayed in even horizontal line liquid crystal cells in even frame periods. Includes only data voltages that

  FIG. 2 is a waveform diagram showing one example of interlaced data supplied to the liquid crystal cell (Clc). The liquid crystal cell (Clc) to which the data voltage as shown in FIG. 2 is supplied is assumed to be any one of the liquid crystal cells arranged on the odd horizontal lines.

  Referring to FIG. 2, the liquid crystal cell (Clc) is supplied with a positive voltage during an odd frame period and supplied with a negative voltage during an even frame period. In the interlace method, a high positive polarity data voltage is supplied to the liquid crystal cells (Clc) arranged on the odd horizontal lines only during the odd frame period, so that the positive polarity is like the waveform in the box during the four frame periods. The negative data voltage becomes dominant compared to the negative data voltage, and a DC afterimage appears. FIG. 3 is an image showing experimental results of a DC afterimage that appears by interlaced data. If an original image such as the left image in FIG. 3 is supplied to the liquid crystal display panel for a certain period of time in an interlaced manner, the data voltage whose polarity changes in units of frame periods changes in amplitude between odd frames and even frames, and as a result After the original image such as the left image, if the data voltage of the intermediate gradation, that is, 127 gradation is supplied to all the liquid crystal cells (Clc) of the liquid crystal display panel, the direct current pattern appears faint as the right image. An afterimage appears.

  As another example of the direct current afterimage, if the same image is moved or scrolled at a constant speed, it is the same as the liquid crystal cell (Clc) depending on the correlation between the scrolled picture size and the scrolling speed (moving speed). Polarity voltage can be repeatedly accumulated and a DC afterimage can appear. Such an example is shown in FIG. FIG. 4 is an image showing the experimental result of the DC afterimage that appears when the oblique line pattern and the character pattern are moved at a constant speed.

  In the liquid crystal display device, not only the moving image display quality deteriorates due to the direct current afterimage, but also the display quality deteriorates due to a flicker phenomenon in which a luminance difference is periodically sensed by the naked eye. Therefore, in order to improve the display quality of the liquid crystal display device, it is necessary to solve the DC afterimage and prevent the flicker phenomenon.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof for preventing a DC afterimage and flicker and improving display quality as an invention devised to solve the problems of the prior art. It is in.

  In order to achieve the above object, a liquid crystal display device of the present invention includes a liquid crystal display panel having a plurality of liquid crystal cells in which a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied are formed. And a first polarity control signal and a second polarity control signal that is different from the first polarity control signal, and a third polarity control signal that is opposite in phase to the first polarity control signal, and the second polarity control. A logic circuit that generates a fourth polarity control signal that is a reverse phase of the signal, and that generates a horizontal output inversion signal that is inverted in units of one frame period; and in response to the polarity control signal, The polarity of the supplied data voltage is shifted in the column direction of the liquid crystal cell in units of one frame period, and the polarity of the data voltage is changed in one frame period in response to the horizontal output inversion signal. Comprising a data driving circuit for shifting along the horizontal direction of the liquid crystal display panel in units, a gate drive circuit for supplying the scan pulse to the gate lines.

  The logic of the polarity control signal is inverted every two horizontal periods.

  During the Nth frame period, the liquid crystal cells arranged in the 4j (i is an integer of 0 or more) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 2 vertical lines have positive polarity. A data voltage is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the 4i + 3 and 4i + 4 vertical lines, and in the 4i + 1 and 4i + 2 vertical lines. The negative polarity data voltage is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines, and the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 3 and 4i + 4 vertical lines. Is supplied with a positive data voltage, and the 4j + 4th and 4i + 3 vertical lines are connected to the 4jth jth line during the (N + 1) th frame period. The liquid crystal cells arranged on the first and fourth j + 4 horizontal lines are supplied with the positive data voltage, and the liquid crystal cells arranged on the fourth j + 1 and fourth j + 4 horizontal lines on the fourth i + 1 and fourth i + 4 vertical lines. Is supplied with the negative data voltage, and the negative data voltage is supplied to the liquid crystal cells disposed in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 2 and fourth i + 3 vertical lines. The liquid crystal cells disposed in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 1 and fourth i + 4 vertical lines are supplied with the positive data voltage, and the fourth i + 3 and fourth i + 4 during the N + 2 frame period. The liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in a vertical line include the positive polarity data. The liquid crystal cells disposed on the 4j + 1 and 4j + 2 horizontal lines in the 4i + 1 and 4i + 2 vertical lines are supplied with the negative data voltage, and the 4i + 3 and 4i + 4 vertical lines. The liquid crystal cells arranged on the 4j + 3 and 4j + 4 horizontal lines are supplied with the negative data voltage and arranged on the 4j + 3 and 4j + 4 horizontal lines on the 4i + 1 and 4i + 2 vertical lines. The liquid crystal cell is supplied with the positive data voltage, and the liquid crystal cell disposed in the 4j + 1 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 4 vertical lines is supplied to the liquid crystal cell during the N + 3 frame period. A positive data voltage is supplied, and the 4j + 1 and 4i + 3 and 4i + 3 vertical lines are connected to the 4j + 1 and 4i + 3 vertical lines. The negative polarity data voltage is supplied to the liquid crystal cells arranged in the 4j + 4 horizontal line, and the liquid crystal cells arranged in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 1 and 4i + 4 vertical lines. The negative data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 2 and fourth i + 3 vertical lines.

The liquid crystal cell is supplied with a first liquid crystal cell group to which a voltage having the same polarity is continuously supplied during two frame periods, and a voltage having the first polarity and a second polarity is continuously supplied during the two frame periods. A second liquid crystal cell group,
In each frame period, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged along the horizontal direction and the vertical direction, and the first liquid crystal cell group in units of one frame period. And the position of the second liquid crystal cell group change from each other.

  During the Nth frame period, the liquid crystal cells arranged in the 4j (j is an integer of 0 or more) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 4 vertical lines have positive polarity. Is supplied to the liquid crystal cells disposed in the 4j + 1 and 4j + 2 horizontal lines of the 4i + 2 and 4i + 3 vertical lines, and the 4i + 1 and 4i + 4 vertical lines are supplied with a negative data voltage. The negative data voltage is supplied to the liquid crystal cells arranged on the 4j + 3 and 4j + 4 horizontal lines, and the 4j + 3 and 4j + 4 horizontal lines are arranged on the 4j + 3 and 4j + 4 horizontal lines. The positive polarity data voltage is supplied to the liquid crystal cell, and the previous 4i + 3 and 4i + 4 vertical lines are used during the (N + 1) th frame period. The liquid crystal cells arranged on the 4j + 1 and 4j + 4 horizontal lines are supplied with the positive data voltage, and arranged on the 4j + 1 and 4j + 4 horizontal lines on the 4i + 1 and 4i + 2 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 3 and fourth i + 4 vertical lines. The liquid crystal cells disposed in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 1 and 4i + 2 vertical lines are supplied with the positive data voltage, and the 4i + 2 and 4i + 2 and 4i + 2 The liquid crystal cell disposed on the 4j + 1 and 4j + 4 horizontal lines in the 4i + 3 vertical line includes the positive electrode. The negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 4 vertical lines, and the 4i + 2 and 4i + 2 and 4i + 4th data lines are supplied. The negative data voltage is supplied to the liquid crystal cells disposed on the 4j + 2 and 4j + 3 horizontal lines on the 4i + 3 vertical line, and on the 4j + 2 and 4j + 3 horizontal lines on the 4i + 1 and 4i + 4 vertical lines. The liquid crystal cell is supplied with the positive data voltage, and is disposed on the 4j + 1 and 4j + 2 horizontal lines in the 4i + 1 and 4i + 2 vertical lines during the (N + 3) th frame period. Is supplied with the positive data voltage, and the 4i + 3 and 4i + 4 vertical lines are connected to the positive data voltage. The liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines are supplied with the negative data voltage, and the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 2 vertical lines. Is supplied with the negative data voltage, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 3 and fourth i + 4 vertical lines.

  The liquid crystal cell includes a first liquid crystal cell group to which a voltage having the same polarity is continuously supplied during two frame periods, and a first polarity voltage and a second polarity voltage being continuously supplied between the two frame periods. A second liquid crystal cell group to be supplied, and the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 3 columns between the Nth frame period and the N + 2th frame period; The liquid crystal cell group includes liquid crystal cells arranged in the 4i + 2 and 4i + 4 columns, and the liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group between the N + 1 frame period and the N + 3 frame period. The cells are alternately arranged in the horizontal direction and the vertical direction.

  In addition, the liquid crystal display device of the present invention includes a liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines to which a data voltage is supplied and a plurality of gate lines to which a scan pulse is supplied. A polarity control signal for inverting the data voltage, a control circuit for generating a horizontal output inversion signal for shifting the polarity of the data voltage in the horizontal direction of the liquid crystal display panel in units of one frame period, and the polarity control signal In response, a data driving circuit that inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods, shifts in the horizontal direction in response to the horizontal output inversion signal, and supplies the data line to the data line And a gate driving circuit for supplying the scan pulse to the gate line.

  During the Nth frame period, a positive data voltage is supplied to the liquid crystal cells arranged in the odd horizontal lines of the 4i (i is a positive integer) +1 vertical line and the 4i + 4 vertical line, and the 4i + 2 vertical line is supplied. A negative data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines in the 4i + 3 vertical line and the liquid crystal cells arranged on the even horizontal lines in the 4i + 1 vertical line and the 4i + 4 vertical line. The negative data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines of the 4i + 2 vertical line and the 4i + 3 vertical line, so that the N + 1th frame. The liquid crystal cells disposed on the odd horizontal lines of the 4i + 1 vertical line and the 4i + 2 vertical line have a positive polarity during the period. The data voltage is supplied, and the negative data voltage is supplied to the liquid crystal cells disposed on the odd horizontal lines of the 4i + 3 vertical line and the 4i + 4 vertical line, and the 4i + 1 vertical line and the 4th vertical line are supplied. The negative polarity data voltage is supplied to the liquid crystal cells arranged on the even horizontal lines with 4i + 2 vertical lines, and the liquid crystal cells arranged on the even horizontal lines with the 4i + 3 vertical lines and the 4i + 4 vertical lines are supplied to the liquid crystal cells. Is supplied with the positive data voltage, and the negative data voltage is applied to the liquid crystal cells arranged on the odd horizontal lines in the 4i + 1 vertical line and the 4i + 4 vertical line during the (N + 2) th frame period. And the liquid crystal cells arranged on the odd-numbered horizontal lines of the 4i + 2 vertical line and the 4i + 3 vertical line. The positive data voltage is supplied to the cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines of the 4i + 1 vertical line and the 4i + 4 vertical line. The negative polarity data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines of the 4i + 2 vertical line and the 4i + 3 vertical line, and the 4i + 1 vertical line and the 4i + 2 are supplied during the N + 3 frame period. The negative data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines in the vertical lines, and the liquid crystal cells arranged on the odd horizontal lines in the 4i + 3 vertical lines and the 4i + 4 vertical lines are supplied to the liquid crystal cells arranged on the odd horizontal lines. The positive data voltage is supplied, and the even horizontal line is applied to the 4i + 1 vertical line and the 4i + 2 vertical line. The positive polarity data voltage is supplied to the liquid crystal cell arranged in the vertical line, and the negative polarity data voltage is supplied to the liquid crystal cell arranged on the even horizontal line in the fourth i + 3 vertical line and the fourth i + 4 vertical line. Supplied.

  During the Nth frame period, positive polarity data is supplied to the liquid crystal cells arranged in the 4j (j is a positive integer) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 4 vertical lines. A voltage is supplied to the liquid crystal cells disposed in the 4j + 1 and 4j + 2 horizontal lines at the 4i + 2 and 4i + 3 vertical lines, and a negative data voltage is supplied to the liquid crystal cells arranged at the 4i + 1 and 4i + 4 vertical lines. The negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines, and the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 2 and 4i + 3 vertical lines. The positive data voltage is supplied, and the fourth j + 1 and fourth i + 2 vertical lines are used for the fourth j + 1 and fourth i + 2 vertical lines during the (N + 1) th frame period. The liquid crystal cells arranged in the 4j + 2 horizontal line are supplied with the positive data voltage, and the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines are the negative polarity in the 4i + 3 and 4i + 4 vertical lines. Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 2 vertical lines, and the 4i + 3 and 4i + 4 are supplied with the negative data voltage. The liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the vertical line are supplied with the positive data voltage, and the 4j + 1 and 4i + 1 and 4i + 4 vertical lines in the 4j + 1 and 4i + 4 vertical lines are supplied with the positive data voltage. The liquid crystal cells arranged on the 4j + 2 horizontal line are supplied with the negative data voltage, and The liquid crystal cells disposed on the 4j + 1 and 4j + 2 horizontal lines at the +2 and 4i + 3 vertical lines are supplied with the positive data voltage, and the 4j + 3 and 4j + 4 horizontal lines at the 4i + 1 and 4i + 4 vertical lines. The positive polarity data voltage is supplied to the liquid crystal cells arranged in the line, and the negative polarity data is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 2 and fourth i + 3 vertical lines. During the (N + 3) th frame period, the negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the 4i + 1 and 4i + 2 vertical lines. Liquid crystal cells disposed on the 4j + 1 and 4j + 2 horizontal lines in the 4i + 3 and 4i + 4 vertical lines. Is supplied with the positive data voltage, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 1 and fourth i + 2 vertical lines. The negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 3 and 4i + 4 vertical lines.

  The liquid crystal display device driving method according to the present invention includes a liquid crystal display panel having a plurality of liquid crystal cells in which a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied are formed. In the driving method of the display device, a first polarity control signal and a second polarity control signal different from the first polarity control signal are generated, and a third polarity control signal which is an opposite phase of the first polarity control signal, and Generating a fourth polarity control signal having a phase opposite to that of the second polarity control signal and generating a horizontal output inversion signal whose logic is inverted in units of one frame period; and in response to the polarity control signal, the data The polarity of the data voltage supplied to the line is shifted in the vertical direction in units of one frame period, and the polarity of the data voltage is changed in one frame period in response to the horizontal output inversion signal. A step of shifting along the horizontal direction in the unit, including supplying the scan pulse to the gate lines.

  The liquid crystal display device driving method according to the present invention includes a liquid crystal display panel having a plurality of liquid crystal cells in which a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied are formed. In a driving method of a display device, a step of generating a polarity control signal whose logic is periodically inverted and a horizontal output inversion signal for shifting the polarity of the data voltage along the horizontal direction in units of one frame period And inverting the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal and shifting in the horizontal direction in response to the horizontal output inversion signal. And supplying the scan pulse to the gate line.

  In addition, the driving method of the liquid crystal display device of the present invention includes a liquid crystal display panel having a plurality of liquid crystal cells in which a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied are formed. In a driving method of a liquid crystal display device, a step of analyzing digital video data of an input video, a step of generating a polarity control signal whose logic is periodically inverted, and interlace data input as a result of video judgment of the input video Generating a horizontal output inversion signal for shifting the polarity of the data voltage along the horizontal direction of the liquid crystal display panel in units of one frame period, and the data voltage in response to the polarity control signal. Is inverted in units of one horizontal period and shifted in the horizontal direction in response to the horizontal output inversion signal to the data line. A step of feeding includes the step of supplying the scan pulse to the gate lines.

  The liquid crystal display device of the present invention includes a liquid crystal display panel having a plurality of data lines to which a data voltage is supplied and a plurality of gate lines to which a scan pulse is supplied to have a plurality of liquid crystal cells, and a response to a polarity control signal. A data driving circuit that supplies the data voltage to the data line; a gate driving circuit that supplies the scan pulse to the gate line; and a controller that generates the polarity control signal differently in units of frame periods. The display panel includes first and second liquid crystal cell groups having different data voltage frequencies within two frame periods, and the first liquid crystal cell group and the second liquid crystal cell group are alternately arranged in one frame period in the vertical and horizontal directions. The positions of the first and second liquid crystal cell groups each have a size within 2 × 2 liquid crystal cells. The data voltage frequency is lower than the data voltage frequency of the second liquid crystal cell group, and the controller reverses the logic in units of one frame period and outputs some data among the data voltages output from the data driving circuit. An H2 / H1 inversion signal is generated that inverts the polarity of the voltage and shifts the polarity of the data voltage supplied to the data line along the horizontal direction of the liquid crystal display panel. A plurality of first decoders for converting with a negative gamma compensation voltage; a plurality of second decoders for converting digital video data with a negative gamma compensation voltage; and the first decoder and the second decoder in response to the polarity control signal. A plurality of multi-flexors that alternately select the output of the multi-flexor and a control terminal of a part of the multi-flexers The control signal supplied to the control terminal in response to the H2 / H1 inversion signal is inverted in units of one frame period, and the polarity of the data voltage supplied to the data line is set to the horizontal of the liquid crystal display panel. A horizontal output inverting circuit is provided for shifting along the direction.

  The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in 2 horizontal period periods, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in 1 horizontal period period. A second polarity control signal, a third polarity control signal generated in the fourth i + 3 frame period and in an opposite phase to the first polarity control signal, and a second polarity control signal generated in the fourth i + 4 frame period. Includes a fourth polarity control signal generated in an opposite phase.

  During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 2 vertical lines in the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and 4i + 4. The liquid crystal cells (Clc) are disposed in the 4i + 3 and 4i + 4 vertical lines in the horizontal line, and the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween. During the frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and 4th on the 4i + 1 and 4i + 4 horizontal lines. 4i + 2 including a liquid crystal cell arranged in a vertical line, and the second liquid crystal cell group is arranged with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 2 vertical lines at the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and 4i + 4 horizontal lines. The liquid crystal cells are disposed in the 4i + 3 and 4i + 4 vertical lines, and the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween, during the 4i + 4 frame period. The first liquid crystal cell group includes the liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines with the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and 4i + 2 vertical lines with the 4i + 1 and 4i + 4 horizontal lines. The second liquid crystal cell group is disposed vertically and horizontally with the first liquid crystal cell group in between. It is.

  The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in 2 horizontal period periods, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in 1 horizontal period period. A second polarity control signal, a third polarity control signal generated in the fourth i + 3 frame period and in an opposite phase to the first polarity control signal, and a second polarity control signal generated in the fourth i + 4 frame period. Includes a fourth polarity control signal generated in an opposite phase.

  During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and 4i + 4. A liquid crystal cell disposed in the 4i + 1 and 4i + 2 vertical lines in a horizontal line, and the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween, and the liquid crystal cells are disposed in a 4i + 2 frame period. Meanwhile, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 2 vertical lines at the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 3 and 4i + 4 verticals at the 4i + 1 and 4i + 4 horizontal lines. A liquid crystal cell arranged in a line, wherein the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween. , During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 3 horizontal lines, and the liquid crystal cells in the 4i + 1 and 4i + 4 horizontal lines. A liquid crystal cell disposed in the 4i + 1 and 4i + 2 vertical lines, the second liquid crystal cell group being disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween, and during the 4i + 4 frame period, The first liquid crystal cell group is disposed on the fourth i + 1 and fourth i + 2 vertical lines at the fourth i + 2 and fourth i + 3 horizontal lines, and on the fourth i + 3 and fourth i + 4 vertical lines at the fourth i + 1 and fourth i + 4 horizontal lines. The second liquid crystal cell group is disposed vertically and horizontally with the first liquid crystal cell group interposed therebetween.

  The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in 2 horizontal period periods, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in the 2 horizontal period periods. A second polarity control signal having a phase difference of one horizontal period with respect to the first polarity control signal, and a third polarity generated in the fourth i + 3 frame period and in an opposite phase with respect to the first polarity control signal. A control signal and a fourth polarity control signal generated in the 4i + 4 frame period and generated in the opposite phase to the second polarity control signal.

  During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 2 vertical lines in the 4i + 1 and 4i + 3 horizontal lines, and the 4i + 2 and 4i + 4. The liquid crystal cells (Clc) are disposed in the 4i + 3 and 4i + 4 vertical lines in the horizontal line, and the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween. During the frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines on the 4i + 1 and 4i + 3 horizontal lines, and the 4i + 1 and 4th on the 4i + 2 and 4i + 4 horizontal lines. 4i + 2 including a liquid crystal cell arranged in a vertical line, and the second liquid crystal cell group is arranged with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 2 vertical lines at the 4i + 1 and 4i + 3 horizontal lines, and the 4i + 2 and 4i + 4 horizontal lines. The liquid crystal cells are disposed in the 4i + 3 and 4i + 4 vertical lines, and the second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween, during the 4i + 4 frame period. The first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 3 and 4i + 4 vertical lines in the 4i + 1 and 4i + 3 horizontal lines, and the 4i + 1 and 4i + 2 vertical lines in the 4i + 2 and 4i + 4 horizontal lines. The second liquid crystal cell group is disposed vertically and horizontally with the first liquid crystal cell group in between. It is.

  The polarity control signal is generated between the 4i + 1 frame period and the 4i + 2 frame period and the logic is inverted in 2 horizontal period periods, and between the 4i + 3 frame period and the 4i + 4 frame period. The second polarity control signal is generated and inverted in logic in the two horizontal period cycles, and is generated in an opposite phase to the first polarity control signal.

  During a 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on 4i + 3 and 4i + 4 vertical lines, and the second liquid crystal cell group includes 4i + 1 and 4i + 2 A liquid crystal cell disposed on a vertical line, and during a 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells disposed on the 4i + 1 and 4i + 2 vertical lines, and the second liquid crystal cell group includes the liquid crystal cell. The first liquid crystal cell group includes liquid crystal cells disposed on the 4i + 3 and 4i + 4 vertical lines, and the first liquid crystal cell group includes liquid crystal cells disposed on the 4i + 3 and 4i + 4 vertical lines during the 4i + 3 frame period. The cell group includes liquid crystal cells disposed on the 4i + 1 and 4i + 2 vertical lines, and the first liquid crystal cell group includes the 4i + i during the 4i + 4 frame period. Include liquid crystal cells arranged in one and the (4i + 2) th vertical line, the second liquid crystal cell group includes liquid crystal cells arranged in the (4i + 3) th and the (4i + 4) th vertical line.

  The controller counts a gate start pulse and generates frame count information that indicates the number of frames, and generates a line count information that counts a source output enable signal and indicates the number of horizontal lines of the liquid crystal display panel. A line counter, a polarity control signal generating circuit for generating different polarity control signals for each frame period based on the frame count information and the line count information, and the polarity control signal in response to the frame count information A multi-flexor for selecting

  The first polarity control signal generated from the polarity control signal generation circuit is inverted during the 4i + 1 frame period connected between the polarity control signal generation circuit and the multiflexor, and during the 4i + 3 frame period, A first inverter that generates a third polarity control signal; and a second polarity control that is connected between the polarity control signal generation circuit and the multiflexor and is generated from the polarity control signal generation circuit during a 4i + 2 frame period. A second inverter for inverting the signal and generating a fourth polarity control signal for the 4i + 4 frame period is further provided.

  A first polarity control signal connected between the polarity control signal generation circuit and the multiflexor and generated from the polarity control signal generation circuit during the 4i + 1 frame period and the 4i + 2 frame period is inverted to obtain a 4i + 3 An inverter for generating a second polarity control signal between the frame period and the 4i + 4th frame period is further included.

  It further includes a video analysis circuit that analyzes the digital video data of the input video and controls the polarity control signal and the H2 / H1 inversion signal generated from the controller according to the analysis result.

  The liquid crystal display device driving method of the present invention includes a plurality of data lines to which a data voltage from a data driving circuit is supplied and a plurality of gate lines to which a scan pulse from a gate driving circuit is supplied. In a driving method of a liquid crystal display device having a liquid crystal display panel having a liquid crystal cell, supplying the data voltage to the data line in response to a polarity control signal and supplying the scan pulse to the gate line And generating the polarity control signal differently for each frame period, and inverting the logic for each frame period and inverting the polarity of a part of the data voltage output from the data driving circuit. H2 / H1 inversion for shifting the polarity of the data voltage supplied to the data line along the horizontal direction of the liquid crystal display panel The liquid crystal display panel includes first and second liquid crystal cell groups having different data voltage frequencies within two frame periods, and the first liquid crystal cell group and the second liquid crystal cell group are vertical. The positions of the first and second liquid crystal cell groups are alternately changed in units of one frame period alternately in the horizontal direction, and each of the first and second liquid crystal cell groups has a size within 2 × 2 liquid crystal cells. The voltage frequency is lower than the data voltage frequency of the second liquid crystal cell group.

The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in the period of 2 horizontal periods, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in the period of 1 horizontal period. A second polarity control signal, and a third polarity control signal that is generated in a 4i + 3 frame period and is generated in an opposite phase to the first polarity control signal;
A fourth polarity control signal generated in a 4i + 4 frame period and generated in an opposite phase to the second polarity control signal.

  The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in one horizontal period period, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in two horizontal period periods. A second polarity control signal generated in the fourth i + 3 frame period and in a phase opposite to the first polarity control signal, and a fourth polarity control signal generated in the fourth i + 4 frame period. A fourth polarity control signal generated in an opposite phase to the two polarity control signal is included.

  The polarity control signal is generated in the 4i + 1 frame period and the logic is inverted in a period of 2 horizontal periods, and the polarity control signal is generated in the 4i + 2 frame period and the logic is inverted in a period of 2 horizontal periods. A second polarity control signal having a phase difference of one horizontal period with respect to the first polarity control signal, and a second polarity control signal generated in a 4i + 3 frame period and having an opposite phase with respect to the first polarity control signal. A three-polarity control signal and a fourth polarity control signal generated in the fourth i + 4 frame period and generated in the opposite phase to the second polarity control signal.

  The polarity control signal is generated between the 4i + 1 frame period and the 4i + 2 frame period, and the logic is inverted in two horizontal period periods, and between the 4i + 3 frame period and the 4i + 4 frame period. And a second polarity control signal generated by inverting the logic in the period of the two horizontal periods and generating an opposite phase to the first polarity control signal.

  The method further includes analyzing digital video data of an input image and controlling the polarity control signal and the H2 / H1 inversion signal according to the analysis result.

  According to the liquid crystal display device and the driving method of the present invention, the driving frequency of the data voltage supplied to the first liquid crystal cell group of the liquid crystal display panel is controlled to be low within two frame periods to prevent a DC afterimage and the second liquid crystal cell. The display voltage is controlled not only to increase the display quality by controlling the drive frequency of the data voltage supplied to the group to prevent flicker but also to reduce the size of each of the first liquid crystal cell group and the second liquid crystal cell group. To improve.

FIG. 3 is an equivalent circuit diagram illustrating a liquid crystal cell of a liquid crystal display device. The wave form diagram which shows one embodiment of interlace data. Experiment result screen showing DC afterimage by interlaced data. Experimental result screen showing DC afterimages from scroll data. FIG. 3 is a diagram for explaining a driving method of the liquid crystal display device according to the first embodiment of the present invention. FIG. 6 is a waveform diagram showing a DC afterimage effect by the first liquid crystal cell group shown in FIG. 5. The figure which shows the polarity pattern of the data voltage which concerns on 1st Embodiment of this invention. The figure which shows the polarity pattern of the data voltage which concerns on 1st Embodiment of this invention. FIG. 9 is a waveform diagram showing an AC value and a DC offset value of a data voltage measured by a liquid crystal display panel supplied with the data voltage as shown in FIGS. 1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention. FIG. 11 is a block diagram showing in detail the data driving circuit shown in FIG. 10. FIG. 12 is a circuit diagram showing in detail the digital / analog converter shown in FIG. 11. FIG. 11 is a block diagram showing in detail the logic circuit shown in FIG. 10. FIG. 14 is a block diagram showing in detail the POL generation circuit shown in FIG. 13. 9 is a flowchart for explaining a driving method of a liquid crystal display device according to a second embodiment of the present invention. The block diagram which shows the liquid crystal display device which concerns on 2nd Embodiment of this invention. 9 is a flowchart for explaining a driving method of a liquid crystal display device according to a third embodiment of the present invention. The figure which shows the polarity pattern of the data voltage with which the 1st and 2nd liquid crystal cell group is charged with the drive method of the liquid crystal display device which concerns on 3rd Embodiment of this invention. FIG. 10 is a diagram illustrating a polarity pattern of data voltages supplied to the first and second liquid crystal cell groups during a 20 frame period in the driving method of the liquid crystal display device according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a polarity pattern of data voltages supplied to the first and second liquid crystal cell groups during a 20 frame period in the driving method of the liquid crystal display device according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a polarity pattern of data voltages supplied to the first and second liquid crystal cell groups during a 20 frame period in the driving method of the liquid crystal display device according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a polarity pattern of data voltages supplied to the first and second liquid crystal cell groups during a 20 frame period in the driving method of the liquid crystal display device according to the third embodiment of the present invention. FIG. 10 is a diagram illustrating a polarity pattern of data voltages supplied to the first and second liquid crystal cell groups during a 20 frame period in the driving method of the liquid crystal display device according to the third embodiment of the present invention. The block diagram which shows the liquid crystal display device which concerns on 3rd Embodiment of this invention. FIG. 21 is a block diagram illustrating the logic circuit shown in FIG. 20 in detail. FIG. 22 is a block diagram showing in detail the POL generation circuit shown in FIG. 21. 9 is a flowchart for explaining a driving method of a liquid crystal display device according to a fourth embodiment of the present invention. The block diagram which shows the liquid crystal display device which concerns on 4th Embodiment of this invention. The figure which shows the polarity pattern of the data voltage supplied to the liquid crystal display device which concerns on 5th Embodiment of this invention. The block diagram which shows the liquid crystal display device which concerns on 5th Embodiment of this invention. FIG. 27 is a block diagram showing the logic circuit shown in FIG. 26 in detail. FIG. 28 is a block diagram showing in detail the POL generation circuit shown in FIG. 27. FIG. 27 is a block diagram showing in detail the data driving circuit shown in FIG. 26. FIG. 30 is a circuit diagram showing in detail the digital / analog converter shown in FIG. 29; The figure which shows the other polarity pattern of the data voltage supplied to the liquid crystal display device which concerns on embodiment of this invention. The wave form diagram which shows a reference | standard polarity control signal, the 1st thru | or 4th polarity control signal, and a horizontal output inversion signal. 10 is a flowchart for explaining a driving method of a liquid crystal display device according to a sixth embodiment of the present invention. The block diagram which shows the liquid crystal display device which concerns on 6th Embodiment of this invention. The figure which shows the polarity pattern of the data voltage supplied to the liquid crystal display device which concerns on 7th Embodiment of this invention. The block diagram which shows the liquid crystal display device which concerns on 7th Embodiment of this invention. FIG. 37 is a block diagram showing in detail the data driving circuit shown in FIG. 36. FIG. 38 is a circuit diagram showing in detail the digital / analog converter shown in FIG. 37. FIG. 39 is a waveform diagram showing a polarity control signal and a horizontal output inversion signal for controlling the digital / analog converter shown in FIG. The flowchart for demonstrating the drive method of the liquid crystal display device which concerns on 8th Embodiment of this invention. The block diagram which shows the liquid crystal display device which concerns on 8th Embodiment of this invention. The figure which shows the other polarity pattern of the data voltage supplied to the liquid crystal display device which concerns on 7th and 8th embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The figure which shows the polarity pattern of the various data voltage applicable to the liquid crystal display device which concerns on 9th Embodiment of this invention. The wave form diagram which shows the optical waveform measured with the liquid crystal display panel to which a data voltage like FIG. 43A thru | or FIG. 45B is supplied. The block diagram which shows the liquid crystal display device which concerns on 9th Embodiment of this invention. The block diagram which shows the liquid crystal display device which concerns on 10th Embodiment of this invention. FIG. 49 is a block diagram showing in detail the POL logic circuit shown in FIG. 48. FIG. 49 is a block diagram showing in detail the data driving circuit shown in FIGS. 47 and 48; FIG. 51 is a circuit diagram showing in detail the digital / analog converter shown in FIG. 50. FIG. 51 is a circuit diagram showing in detail another embodiment of the digital / analog converter shown in FIG. 50. FIG. 44 is a waveform diagram showing a polarity control signal and an H2 / H1 inversion signal for obtaining the polarity pattern of the data voltage shown in FIGS. 43A and 43B. 44A and 44B are waveform diagrams showing a polarity control signal and an H2 / H1 inverted signal for obtaining the polarity pattern of the data voltage shown in FIGS. 44A and 44B. FIG. 46 is a waveform diagram showing a polarity control signal and an H2 / H1 inversion signal for obtaining the polarity pattern of the data voltage shown in FIGS. 45A and 45B. The flowchart for demonstrating the drive method of the liquid crystal display device which concerns on 11th Embodiment of this invention. The block diagram which shows the liquid crystal display device which concerns on 11th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS.

  In the driving method of the liquid crystal display device according to the embodiment of the present invention, the data driving frequencies of the first liquid crystal cell group and the second liquid crystal cell group that coexist in the liquid crystal display panel are different within two frame periods.

  The first liquid crystal cell group is driven at a low data driving frequency in order to prevent a DC afterimage. In comparison, the second liquid crystal cell group is driven at a relatively high driving frequency in order to prevent flicker that may appear by the first liquid crystal cell group.

  The polarity pattern change of the data voltage charged in the first liquid crystal cell group corresponds to the driving frequency of the first liquid crystal cell group, and the polarity pattern change of the data voltage charged in the second liquid crystal cell group is the second liquid crystal cell group. Corresponds to the drive frequency.

  The polarity pattern of the data voltage charged in the first liquid crystal cell group and the second liquid crystal cell group changes every frame, and the same polarity pattern is repeated in N (N is an integer of 4 or more) frame period. The following embodiment will be described assuming that “N” is “4”.

Referring to FIG. 5, in the driving method of the liquid crystal display device according to the first embodiment of the present invention, the first liquid crystal cell group is set to a data voltage frequency ½ lower than the second liquid crystal cell group within two frame periods. To drive. For example, the first liquid crystal cell group is driven to a data voltage frequency of 30 Hz and the second liquid crystal cell group is driven to a data voltage frequency of 60 Hz within two frame periods. In addition, the first liquid crystal cell group can be driven to a data voltage frequency of 60 Hz and the second liquid crystal cell group can be driven to a data voltage frequency of 120 Hz within two frame periods.

A driving method of a liquid crystal display device according to the first embodiment of the present invention prevents a DC afterimage by supplying a data voltage whose polarity is inverted in a period of two frame periods to a first liquid crystal cell group, thereby preventing a second liquid crystal cell. A data voltage whose polarity is inverted in one frame period is supplied to the group to prevent the flicker phenomenon. The prevention effect of the DC afterimage by the first liquid crystal cell group will be described with reference to FIG.

  Referring to FIG. 6, a high data voltage is supplied to an arbitrary liquid crystal cell (Clc) included in the first liquid crystal cell group during an odd frame period, and a relatively low data voltage is supplied during an even frame period. Assume that the polarity of the data voltage changes in a period of 2 frame periods. Then, the positive data voltage supplied to the liquid crystal cell (Clc) of the first liquid crystal cell group during the first and second frame periods and the liquid crystal cell (Clc) of the first liquid crystal cell group during the third and fourth frame periods. ) Is neutralized and the polarized voltage deflected in the liquid crystal cell (Clc) is not accumulated.

  Accordingly, the liquid crystal display device of the present invention is a data voltage, for example, an interlaced image, to which a voltage having a dominant polarity is applied in any one of an odd frame and an even frame as shown in FIG. No DC afterimage appears even at the data voltage of.

  The first liquid crystal cell group can prevent a DC afterimage, but flicker can occur because the data voltage having the same polarity is supplied to the liquid crystal cell (Clc) in two frame period periods. The liquid crystal cell (Clc) of the second liquid crystal cell group is applied with a data voltage whose polarity is inverted in a period of one frame period in which the flicker is hardly felt with the naked eye, thereby minimizing the flicker phenomenon caused by the first liquid crystal cell group. . This is because the human naked eye is sensitive to changes, and if the liquid crystal display device in which the first liquid crystal cell group and the second liquid crystal cell group having different driving frequencies coexist is seen, the driving frequency of the second liquid crystal cell group having a high driving frequency. This is because the drive frequency of the first liquid crystal cell group is recognized.

  7 and 8 are diagrams illustrating polarity patterns of data voltages according to the first embodiment of the present invention.

  Referring to FIG. 7, the driving method of the liquid crystal display device according to the first embodiment of the present invention repeats the data voltage polarity pattern at a period of 4 frame periods, and positions the first and second liquid crystal cell groups for each frame. Move.

In the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes even horizontal line (Ec) horizontal liquid crystal cells (Clc) and the second liquid crystal cell group includes odd horizontal line liquid crystal cells (Clc). Clc). During the 4i + 1 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other.
Similarly, during the 4i + 1 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group interposed therebetween. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other.

  During the 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) having odd horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) having even horizontal lines. During the 4i + 2 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts.

  The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 2 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group interposed therebetween. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other.

  During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) of even horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) of odd horizontal lines. During the 4i + 3 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 3 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group in between. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other. As can be seen from the comparison of the data voltage polarity pattern in the 4i + 3 frame period and the data voltage polarity pattern in the 4i + 1 frame period, the positions of the first and second liquid crystal cell groups are the same in the 4i + 1 frame period and the 4i + 3 frame period. Therefore, the polarity of the data voltage is contradictory.

  During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) with odd horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) with even horizontal lines. During the 4i + 4 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 4 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group in between. Contradict each other.

  The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other. As can be seen by comparing the data voltage polarity pattern of the 4i + 4 frame period and the data voltage polarity pattern of the 4i + 2 frame period, the positions of the first and second liquid crystal cell groups are the same in the 4i + 2 frame period and the 4i + 4 frame period. In comparison, the polarity of the data voltage is contradictory.

  The first polarity control signal (POLa) generated during the 4i + 1 frame period and the third polarity control signal (POLc) generated during the 4i + 3 frame period are generated in opposite phases. The second polarity control signal (POLb) generated during the 4i + 2 frame period and the fourth polarity control signal (POLd) generated during the 4i + 4 frame period are generated in waveforms with opposite phases. The first polarity control signal (POLa) and the second polarity control signal (POLb) have a phase difference of about one horizontal period, and the third polarity control signal (POLc) and the fourth polarity control signal (POLd) also have one horizontal period. Phase difference.

  In the polarity control signals (POLa to POLd) for controlling the data voltage polarity pattern of FIG. 8, the second and fourth polarity control signals (POLb, POLd) are the second and fourth polarity control signals (POLb) of FIG. , POLd) are generated in the opposite phase.

  Referring to FIG. 8, in the 4i + 1 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) having odd horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) having even horizontal lines.

  During the 4i + 1 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 1 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group interposed therebetween. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other.

  During the 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) with even horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) with odd horizontal lines. During the 4i + 2 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts.

  The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 2 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group interposed therebetween. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other.

  During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) of odd horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) of even horizontal lines. During the 4i + 3 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts.

  The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 3 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group in between. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Compared with the positions of the first and second liquid crystal cell groups in the 4i + 1 frame period and the 4i + 3 frame period, the polarity of the data voltage is opposite.

  During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells (Clc) with even horizontal lines, and the second liquid crystal cell group includes liquid crystal cells (Clc) with odd horizontal lines. During the 4i + 4 frame period, the polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the second liquid crystal cell group in between are mutually Conflicts.

  The polarities of the data voltages charged in the liquid crystal cells (Clc) of the first liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Similarly, during the 4i + 4 frame period, the polarity of the data voltage charged in the liquid crystal cell (Clc) of the second liquid crystal cell group adjacent in the vertical direction with the liquid crystal cell (Clc) of the first liquid crystal cell group in between. Contradict each other. The polarities of the data voltages charged in the liquid crystal cells (Clc) of the second liquid crystal cell group adjacent in the horizontal direction are opposite to each other. Compared with the positions of the first and second liquid crystal cell groups in the 4i + 2 frame period and the 4i + 4 frame period, the polarity of the data voltage is opposite.

  Since the liquid crystal cells (Clc) of the first liquid crystal cell group have a relatively long polarity change period, flicker can be seen if they are spatially concentrated. Therefore, the driving method of the liquid crystal display device according to the embodiment of the present invention is such that the liquid crystal cells (Clc) of the first liquid crystal cell group are not continued more than two horizontal lines in each frame period as shown in FIGS. Control the polarity of the voltage.

  Since the liquid crystal cell (Clc) of the first liquid crystal cell group has a relatively long polarity change period, if its position is the same for three frame periods or more, it induces a luminance difference from other horizontal lines and causes wave noise. Can bring. Accordingly, in the driving method of the liquid crystal display device according to the first embodiment of the present invention, as shown in FIGS. 7 and 8, the first liquid crystal cell group is alternately turned into the second liquid crystal cell group and the second liquid crystal cell unit in units of one frame. The cell group is controlled to the first liquid crystal cell group.

  FIG. 9 shows a result of an experiment in which a 127-gradation data voltage is supplied to the liquid crystal display panel with the polarity pattern as shown in FIGS. 7 and 8, and the voltage waveform of the liquid crystal display panel is measured. In this experiment, the second liquid crystal cell group of the liquid crystal display panel is supplied with a data voltage whose polarity is changed at a frequency of 60 Hz within two frame periods, and the polarity of the first liquid crystal cell group is changed at a frequency of 30 Hz. Although the data voltage is supplied, the frequency of the data voltage measured by the liquid crystal display panel is 60 Hz because the 60 Hz frequency, which is fast, is dominant. The AC voltage value (AC) of the data voltage, that is, the amplitude was 30.35 mV, and the DC offset value (DC) between the center of the AC voltage and the ground voltage (GND) was 1.389 V. In addition, as a result of measuring the optical waveform by installing an optical sensor on the test liquid crystal display panel in this experiment, the optical waveform of the test liquid crystal display panel is also measured at 60 Hz by the dominant frequency of the second liquid crystal cell group. It was done. This is because the light waveform measured by the test liquid crystal display panel is determined by the light conversion period of the second liquid crystal cell group having a higher frequency than the first liquid crystal cell having the slower frequency.

  10 to 14 show a liquid crystal display device according to the first embodiment of the present invention.

  Referring to FIG. 10, the liquid crystal display device according to the first embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a logic circuit 102, a data driving circuit 103, and a gate driving circuit 104.

  In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The liquid crystal display panel 100 includes m × n liquid crystal cells (Clc) in which m data lines (D1 to Dm) and n gate lines (G1 to Gn) are arranged in a matrix by an intersecting structure. As described above, the liquid crystal cell (Clc) includes a first liquid crystal cell group and a second liquid crystal cell group that are driven to different data voltage frequencies within two frame periods.

  The lower glass substrate of the liquid crystal display panel 100 has data lines (D1 to Dm), gate lines (G1 to Gn), TFTs, a pixel electrode 1 of a liquid crystal cell (Clc) connected to the TFTs, a storage capacitor (Cst), and the like. Is formed.

  A black matrix, a color filter, and a common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. On the other hand, the common electrode 2 is formed on the upper glass substrate by a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, or an IPS (In Plane Switching) mode and an FFS (Fringe Field Switching). ) Is formed on the lower glass substrate like the pixel electrode 1 by a horizontal electric field driving method like the mode. A polarizing plate having optical axes orthogonal to each other is attached on the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, and an alignment film for setting the free tilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

  The timing controller 101 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable (Data Enable), and a clock signal (CLK), and receives a data driving circuit 104, a gate driving circuit 104, and a logic circuit 102. A control signal for controlling the operation timing is generated. Such control signals include a gate start pulse (Gate Start Pulse: GSP), a gate shift clock signal (Gate Shift Clock: GSC), a gate output enable signal (Gate Output Enable: GOE), and a source start pulse (Source Start Pulse: SSP). ), A source sampling clock (SSC), a source output enable signal (Source Output Enable: SOE), and a reference polarity control signal (Polarity: POL). A gate start pulse (GSP) indicates a starting horizontal line where scanning starts within one vertical period in which one screen is displayed. The gate shift clock signal (GSC) is input to a shift register in the gate driving circuit, and as a timing control signal for sequentially shifting the gate start pulse (GSP), a pulse width corresponding to the on period of the TFT is set. Generated. The gate output signal (GOE) instructs the output of the gate drive circuit 104. The source start pulse (SSP) and the data control signal (DDC) indicate a start pixel in one horizontal line on which data is displayed. The source sampling clock (SSC) instructs a data latch operation in the data driving circuit 103 with reference to a rising or falling edge. A source output enable signal (SOE) instructs the output of the data driving circuit 103. The reference polarity control signal (POL) indicates the polarity of the data voltage supplied to the liquid crystal cell (Clc) of the liquid crystal display panel 100. The reference polarity control signal (POL) is either a 1-dot inversion polarity control signal whose logic is inverted in one horizontal period or a 2-dot inversion polarity control signal whose logic is inverted in 2 horizontal periods. Is generated in one form.

  The logic circuit 102 receives a gate start pulse (GSP), a source output enable signal (SOE), and a reference polarity control signal (POL) and sequentially receives polarity control signals (POLa to POLd) for preventing afterimage and flicker. Or a reference polarity control signal (POL) is selectively output.

  The data driving circuit 103 latches digital video data (RGB) under the control of the timing controller 101, and in response to the polarity control signal (POL / POLa to POLd) from the timing controller 101, the digital video data is analog. Conversion is performed using a positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and supply the data voltage to the data lines (D1 to Dm).

  The gate driving circuit 104 is a shift register, a level shift for converting the output signal of the shift register with a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shift and the gate lines (G1 to Gn). Scan pulses each having a pulse width of approximately one horizontal period are sequentially output.

  The logic circuit 102 can be incorporated in the timing controller 101.

  The liquid crystal display device according to the first embodiment of the present invention further includes a system 105 that supplies digital video data (RGB) and timing signals (Vsync, Hsync, DE, CLK) to the timing controller 101.

  The system 105 includes a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and the like. The video data is extracted from the video signal input from the broadcast signal or the external device, and the video data is converted to digital timing. Supply to the controller 101. The interlace broadcast signal received by the system 105 is stored in a line memory and then output. The video data of the interlaced broadcast signal exists only on the odd line in the odd frame period and exists only on the even line in the even frame period. Therefore, when the interlace broadcast signal is received, the system 105 generates the even line data of the odd frame period and the odd line data of the even frame with the average value or the black data value of the effective data stored in the line memory 106.

  Such a system 105 supplies timing signals (Vsync, Hsync, DE, CLK) and power to the timing controller 101 together with digital video data.

  11 and 12 are circuit diagrams showing the data driving circuit 103 in detail.

  Referring to FIGS. 11 and 12, each of the data driving circuits 103 includes a plurality of integrated circuits (Integrated Circuits, ICs) that drive k (k is an integer smaller than m) data lines (D to Dk). Each of the integrated circuits includes a shift register 111, a data register 112, a first latch 113, a second latch 114, a digital / analog converter (hereinafter referred to as “DAC”) 115, a charge share circuit (Charge Share Circuit) 116, and an output circuit. 117 is included.

  The shift register 111 shifts the source start pulse (SSP) from the timing controller 101 by the source sampling clock (SSC) to generate a sampling signal. Further, the shift register 111 shifts the source start pulse (SSP) and transmits the carry signal (CAR) to the shift register 111 of the next stage integrated circuit. The data register 112 temporarily stores odd digital video data (RGBodd) and even digital video data (RGBeven) separated by the timing controller 101, and supplies the stored data (RGBodd, RGBeven) to the first latch 113.

  The first latch 113 samples the digital video data (RGBeven, RGBodd) from the data register 112 in response to a sampling signal sequentially input from the shift register 111, and the data (RGBeven, RGBodd) is one horizontal line. After latching every minute, data for one horizontal line is output simultaneously. The second latch 114 latches data for one horizontal line input from the first latch 113 and then latches simultaneously with the second latch 114 of another integrated circuit during the low logic period of the source output enable signal (SOE). Output digital video data.

  As shown in FIG. 12, the DAC 115 includes a P-decoder (PDEC) 121 to which a positive gamma reference voltage (GH) is supplied, an N-decoder (NDEC) 122 to which a negative gamma reference voltage (GL) is supplied, and a polarity control signal. In response to (POL / POLa to POLd), a multiflexor 123 that selects the output of the P-decoder 121 and the output of the N-decoder 122 is included.

  The P-decoder 121 decodes the digital video data input from the second latch 114 and outputs a positive gamma compensation voltage corresponding to the gradation value of the data. The N-decoder 122 is input from the second latch 114. The digital video data is decoded and a negative gamma compensation voltage corresponding to the gradation value of the data is output. In response to the polarity control signal (POL / POL1 / POL2), the multiflexor 123 selects the positive polarity / negative polarity gamma compensation voltage by alternately selecting the positive polarity gamma compensation voltage and the negative polarity gamma compensation voltage. Is output to the analog data voltage. The charge share circuit 116 shorts adjacent data output channels during a source output enable signal (SOE) high logic period to output an average value of adjacent data voltages, or source output enable signal (SOE) high. A common voltage (Vcom) is supplied to the data output channel during the logic period to reduce a rapid change in the positive data voltage and the negative data voltage. The output circuit 117 includes a buffer to minimize the signal attenuation of the analog data voltage supplied to the data lines (D to Dk).

  13 and 14 are circuit diagrams showing the logic circuit 102 in detail.

  Referring to FIGS. 13 and 14, the logic circuit 102 includes a frame counter 131, a line counter 132, a POL generation circuit 133, and a multiflexor 134.

  The frame counter 131 is generated once during one frame period, and indicates the number of frames of an image displayed on the liquid crystal display panel 100 in response to a gate start pulse (GSP) generated simultaneously with the start of the one frame period. Frame count information (Fcnt) to be output. The frame count information (Fcnt) is generated in 2-beat information so that each of the four frame periods can be identified, assuming that the polarity pattern of the data voltage as shown in FIGS. 7 and 8 is generated. .

  The line counter 132 outputs line count information (Lcnt) indicating a horizontal line displayed on the liquid crystal display panel 100 in response to a source output enable signal (SOE) that indicates a time point at which a data voltage is supplied for each horizontal line. To do.

  The line count information (Fcnt) is 2 because the polarity of the data voltage displayed on the liquid crystal display panel 100 is inverted in 1 or 2 horizontal lines as shown in the polarity pattern of the data voltage as shown in FIGS. Generated in beat information.

  As a timing signal supplied to the frame counter 131 and the line counter 132, a clock generated from the internal oscillator of the timing controller 101 can be used. Since this clock has a high frequency, the EMI is transmitted between the timing controller 101 and the logic circuit 102. (Electromagnetic interference) can be increased. The present invention uses a gate start pulse (GSP) and a source output enable signal (SOE), which have a smaller frequency than the clock generated by the internal oscillator of the timing controller 101, as the operation timing signals for the frame counter 131 and the line counter 132. Thus, an increase in EMI between the timing controller 101 and the logic circuit 102 can be reduced.

  The POL generation circuit 133 includes a first POL generation circuit 141, a second POL generation circuit 142, first and second inverters (143, 144), and a multiflexor 145. The first POL generation circuit 141 generates a first polarity control signal (POLa) whose polarity is inverted every two horizontal periods based on the line counter information (Lcnt). The first inverter 143 inverts the first polarity control signal (POLa) to generate a third polarity control signal (POLc). Based on the line counter information (Lcnt), the second POL generation circuit 142 has a second polarity having a phase difference of about one horizontal period with respect to the first polarity control signal (POLa) by inverting the polarity in units of two horizontal periods. A control signal (POLb) is generated. The second inverter 144 inverts the second polarity control signal (POLb) to generate a fourth polarity control signal (POLd). In response to the frame counter information (Fcnt), the first and second POL generation circuits (141, 142) invert the polarity of the polarity control signals (POLb, POLc) during the frame period. In response to the 2-beat frame count information (Fcnt), the multiflexor 145 outputs the first polarity control signal (POLa) during the 4i + 1 frame period, and then performs the second polarity control during the 4i + 2 frame period. After outputting the signal (POLb), the third polarity control signal (POLc) is output during the 4i + 3 frame period. The multiflexor 145 outputs a fourth polarity control signal (POLd) during the 4i + 4 frame period.

  The multiflexor 134 selects the polarity control signals (POLa to POL1d) from the POL generation circuit 133 corresponding to each frame period as shown in FIGS. 7 and 8 according to the logical value of the control terminal connected to the option pin. The option pin is connected to the control terminal of the multiflexor 134 and can be selectively connected to the base voltage (GND) or the power supply voltage (Vcc) by the operator of the set manufacturer.

  For example, if the option pin is connected to the base voltage (GND) and the control terminal of the multiflexor 134, the multiflexor 134 is supplied with a selection control signal (SEL) of “0” to its control terminal, and the reference polarity When the control signal (POL) is output and the option pin is connected to the power supply voltage (Vcc) and the control terminal of the multiflexor 134, the multiflexor 134 has a selection control signal ('1') on its control terminal ( SEL) is supplied to output the polarity control signals (POL1a to POL1d) from the POL generation circuit 133. The selection control signal (SEL) of the multiflexor 134 can be replaced with a user selection signal input through a user interface or a selection control signal automatically generated from the system 105 or the timing controller 101 according to the data analysis result.

  FIG. 15 is a flowchart for explaining a driving method of the liquid crystal display device according to the second embodiment of the present invention.

  Referring to FIG. 15, the driving method of the liquid crystal display device according to the second embodiment of the present invention analyzes input data, and the input data may appear as a DC afterimage such as interlace data or scroll data. Determine whether the data. (S1, S2)

  If it is determined in step S2 that the currently input data is data that allows a DC afterimage to appear, the second embodiment of the present invention performs the first to fourth polarity control signals (POLa to POLA) in units of frame periods. POLd) is sequentially generated, and the data voltage driving frequency of the first liquid crystal cell group is controlled to be lower than the data voltage driving frequency of the second liquid crystal cell group within two frame periods.

  If it is determined in step S2 that the currently input data is data in which no DC afterimage appears, the second embodiment of the present invention generates a reference polarity control signal (POL) in every frame period, The data voltage driving frequencies of the first and second liquid crystal cell groups are controlled to be the same. (S4)

  FIG. 16 shows a liquid crystal display device according to a second embodiment of the present invention.

  Referring to FIG. 16, the liquid crystal display device according to the second embodiment of the present invention includes a system 105, a liquid crystal display panel 100, a video analysis circuit 161, a timing controller 101, a logic circuit 162, a data driving circuit 103, and a gate driving circuit. 104. In this embodiment, the system 105, the liquid crystal display panel 100, the timing controller 101, the data driving circuit 103, and the gate driving circuit 104 are substantially the same as those in the first embodiment. The explanation is omitted.

  The video analysis circuit 161 determines whether it is data that can generate a DC afterimage with respect to the digital video data of the currently input video. The video analysis circuit 161 compares data between adjacent lines in one frame video, and determines that currently input data is interlaced data if the data between the lines is larger than a predetermined threshold value. The video analysis circuit 161 compares the data of each pixel in units of frames, detects the moving image and the moving speed of the image in the display image, and if the moving image moves at a preset speed, the moving image is included. The frame data is determined from the scroll data. As a result of such video analysis, the video analysis circuit 161 generates a selection signal (SEL2) instructing interlace data and scroll data, and controls the logic circuit 162 using the selection signal (SEL2).

  In response to the first logic value of the selection signal (SEL2) from the video analysis circuit 161, the logic circuit 162 performs the first to fourth polarity control signals (POLa) during the 4i + 1 to 4i + 4 frame periods as shown in FIG. To POLd) are generated sequentially. The logic circuit 162 transmits the reference polarity control signal (POL) as it is to the data driving circuit 103 when data other than the interlace data and scroll data is input in response to the second logic value of the selection signal (SEL2). To do.

  The timing controller 101, the video analysis circuit 161, and the logic circuit 162 can be integrated on a single chip.

  Referring to FIGS. 17 and 18, the driving method of the liquid crystal display device according to the third embodiment of the present invention is performed in two frame periods during N (N is a positive integer of 2 or more) frame periods. The data driving frequency of one liquid crystal cell group is controlled to be lower than the driving frequency of the second liquid crystal cell group. (S1) Each of the first and second liquid crystal cell groups includes a plurality of liquid crystal cells (Clc).

  In the driving method of the liquid crystal display device according to the third embodiment of the present invention, a data voltage having a polarity pattern different from the polarity pattern that determines the polarity of the data voltage is applied during the N + 1th frame period. To supply the first and second liquid crystal cell groups. (S2) Hereinafter, the polarity pattern for controlling the polarity of the data voltage during the (N + 1) th frame period is referred to as “non-regular polarity pattern”. The non-regular polarity pattern is a polarity pattern different from the polarity pattern of the data voltage supplied to the liquid crystal cells (Clc) of the first and second liquid crystal cell groups during the N frame periods before the (N + 1) th frame period. Utilizing it, the polarity pattern of the liquid crystal cell (Clc) is made irregular.

  The driving method of the liquid crystal display device according to the first embodiment of the present invention uses the first liquid crystal cell group to prevent a direct current afterimage as shown in FIG. 6, and uses the second liquid crystal cell group as shown in FIG. To prevent the flicker phenomenon.

  19A to 19E show one embodiment of the polarity pattern of the data voltage in which the irregular polarity pattern is periodically inserted.

  Referring to FIG. 19A to FIG. 19E, the driving method of the liquid crystal display device according to the third embodiment of the present invention repeats the polarity pattern of the data voltage in a cycle of 20 frame periods.

  The logic of the liquid crystal cells (Clc) of the first and second liquid crystal cell groups is inverted in units of two horizontal periods in each of the 4i + 1 to 4i + 4th frame periods except for the 5i (i is a positive integer) frame period. 1 polarity control signal (Polarity signal, POL1a to POL1d) is charged with a data voltage having a polarity pattern in which the polarity is inverted in two horizontal period periods in the vertical direction and the polarities of adjacent data voltages in the horizontal direction are opposite to each other. To do. The first polarity control signal (POL1a) generated in the 4i + 1 to 4i + 4 frame periods is basically generated in a vertical 2-dot inversion form in which the logic is inverted in two horizontal period periods.

  In the fifth i (i is a positive integer greater than or equal to 0) frame period, the liquid crystal cells (Clc) of the first and second liquid crystal cell groups are charged with data voltages whose polarity changes in a non-regular polarity pattern in a 1-dot inversion form. To do. That is, during the fifth i frame period, the liquid crystal cells (Clc) of the first and second liquid crystal cell groups are cycled by one horizontal period in the vertical direction by the second polarity control signal (POL2) whose logic is inverted in units of one horizontal period. A data voltage having a polarity pattern in which the polarity is inverted and the polarity of adjacent data voltages in the horizontal direction is inverted is charged. The first polarity control signals (POL1a to POL1d) are replaced with the second polarity control signal (POL2) in the fifth i frame period.

  1st and 2nd frame period, 4th and 5th frame period, 9th and 10th frame period, 11th and 12th frame period, 14th and 15th frame period, 16th and 17th frame period, 19th frame period And in each of the 20th frame period, some of the liquid crystal cells (Clc) of the first and second liquid crystal cell groups maintain their positions in the next frame period, and some of the others are in the next frame period. Move to a horizontal line. In comparison, the second to fourth frame periods, the seventh to ninth frame periods, the tenth and eleventh frame periods, the twelfth to fourteenth frame periods, the fifteenth and sixteenth frame periods, and the seventeenth to nineteenth frames. In each frame period, the positions of the liquid crystal cells (Clc) of the first and second liquid crystal cell groups are not overlapped between the previous frame and the next frame period.

  The 1a polarity control signal (POL1a) generated during the 4i + 1 frame period and the 1c polarity control signal (POL1c) generated during the 4i + 3 frame period are generated in opposite phases. The 1b polarity control signal (POL1b) generated during the 4i + 2 frame period and the 1d polarity control signal (POL1d) generated during the 4i + 4 frame period are generated in waveforms with opposite phases. The first a polarity control signal (POL1a) and the first b polarity control signal (POL1b) have a phase difference of about one horizontal period, and the first c polarity control signal (POL1c) and the first d polarity control signal (POL1d) also have one horizontal period. Phase difference.

  As shown in FIG. 19A to FIG. 19E, the driving method of the liquid crystal display device according to the third embodiment of the present invention is a frame period in which the positions of the horizontal lines where the liquid crystal cells (Clc) of the first liquid crystal cell group exist are continuous. Control the number up to 2 or less. Since the liquid crystal cell (Clc) of the first liquid crystal cell group has a relatively long polarity change period, if its position is the same for three frame periods or more, it induces a luminance difference from other horizontal lines and causes wave noise. Can do.

  20 to 21 show a liquid crystal display device according to a third embodiment of the present invention.

  Referring to FIG. 20, the liquid crystal display according to the third embodiment of the present invention includes a liquid crystal display panel 200, a timing controller 201, a logic circuit 202, a data driving circuit 203, a gate driving circuit 204, and a system 205. System 205 includes a line memory 206 for storing interlaced data. Since the liquid crystal display panel 100, the timing controller 201, the data driving circuit 203, the gate driving circuit 204, and the system 205 are substantially the same as those in the above-described embodiment, detailed description thereof is omitted.

  The logic circuit 202 receives the gate start pulse (GSP), the source output enable signal (SOE), and the reference polarity control signal (POL) and receives the 4i + 1 to 4i + 4 frame periods except for the 5i frame period. A first polarity control signal (POL1) is generated, and a second polarity control signal (FGDPOL) is generated during the fifth i frame period. The first polarity control signal (POL1) includes a 1a polarity control signal (POL1a) generated in the 4i + 1 frame period, a 1b polarity control signal (POL1b) generated in the 4i + 2 frame period, and a 4i + 3 frame period. 1c polarity control signal (POL1c) generated between the first and fourth frames, and a first d polarity control signal (POL1d) generated during the 4i + 4 frame period. Further, the logic circuit 202 can selectively transmit the reference polarity control signal (POL) to the data driving circuit 203 as it is during all the frame periods.

  21 and 22 are circuit diagrams showing in detail the logic circuit 202 shown in FIG.

  Referring to FIGS. 21 and 22, the logic circuit 202 includes a frame counter 211, a line counter 212, a POL generation circuit 213, and a multiflexor 214.

  The frame counter 211 indicates the number of frames of an image displayed on the liquid crystal display panel 200 in response to a gate start pulse (GSP) generated once during one frame period and simultaneously with the start of one frame period. Frame count information (Fcnt) to be output. The frame count information (Fcnt) is generated in 5-beat information so that each of the 20 frame periods can be identified, assuming that the polarity pattern of the data voltage as shown in FIGS. 8A to 8E is generated. .

  The line counter 212 outputs line count information (Lcnt) indicating a horizontal line displayed on the liquid crystal display panel 200 in response to a source output enable signal (SOE) that indicates a point in time for supplying a data voltage for each horizontal line. To do. The line count information (Fcnt) is 2 because the polarity of the data voltage displayed on the liquid crystal display panel 200 is inverted to 1 or 2 horizontal line periods as can be seen from the polarity pattern of the data voltage as shown in FIGS. 8A to 8E. Generated in beat information.

  As a timing signal supplied to the frame counter 211 and the line counter 212, a clock generated from an internal oscillator of the timing controller 201 can be used. However, since this clock has a high frequency, the clock between the timing controller 201 and the logic circuit 202 can be used. EMI (electromagnetic interference) can be increased. The present invention uses a gate start pulse (GSP) and a source output enable signal (SOE), which have a smaller frequency than the clock generated by the internal oscillator of the timing controller 201, as the operation timing signals of the frame counter 211 and the line counter 212. The increase in EMI between the timing controller 201 and the logic circuit 202 can be reduced.

  The POL generation circuit 213 includes a first POL generation circuit 221, a second POL generation circuit 222, a third POL generation circuit 223, and first and second inverters (224, 145). The first POL generation circuit 221 generates a 1a polarity control signal (POL1a) whose polarity is inverted every two horizontal periods based on the line counter information (Lcnt). The first inverter 224 inverts the 1a polarity control signal (POL1a) to generate the 1c polarity control signal (POL1c). Based on the line counter information (Lcnt), the second POL generation circuit 222 is inverted in polarity in units of two horizontal periods and has a first b polarity having a phase difference of about one horizontal period with respect to the first a polarity control signal (POL1a). A control signal (POL1b) is generated. The second inverter 225 generates a first d polarity control signal (POL1d) by inverting the first b polarity control signal (POL1b). The third POL generation circuit 223 generates a second polarity control signal (POL1b) whose polarity is inverted in units of one horizontal period based on the line counter information (Lcnt). Each of the first to third POL generation circuits (221, 142, 143) inverts the polarity of the polarity control signal (POL1a to POL1d, POL2) during the frame period in response to the frame counter information (Fcnt).

  In response to the frame counter information (Fcnt), the multiflexor 214 selects the polarity control signals (POL1, POL2) from the POL generation circuit 213 corresponding to each frame period as shown in FIGS. 8A to 8E. The multiflexer 214 can output a reference polarity control signal (POL) in every frame period by a separate option pin selected by the set manufacturer. The option pin is connected to the option control terminal of the multiflexor 214 and selectively connected to the base voltage or the power supply voltage (Vcc) by the operator of the set maker, and the output of the multiflexer 214 is connected to the reference polarity control signal (POL). ).

  FIG. 23 is a flowchart for explaining a driving method of the liquid crystal display device according to the fourth embodiment of the present invention.

  Referring to FIG. 23, the driving method of the liquid crystal display device according to the fourth embodiment of the present invention analyzes input data, and a DC afterimage can appear as the input data is interlaced data or scroll data. Determine whether the data. (S231, S232)

  If it is determined in step S232 that the currently input data is data in which a DC afterimage can appear, the fourth embodiment of the present invention is the first that exists in the liquid crystal display panel during N frame periods. A data voltage whose polarity is inverted every two frame periods is supplied to the liquid crystal cell group, and the data driving frequency of the second liquid crystal cell group is controlled to be lower than the data driving frequency of the first liquid crystal cell group within the two frame periods. (S233)

  In succession, the fourth embodiment of the present invention controls the polarity of the data voltage with a “non-regular polarity pattern” during the 5i frame period. (S234)

  Accordingly, in the second embodiment of the present invention, if it is determined that the input data is data that can generate a DC afterimage such as interlaced data or scroll data, the first liquid crystal cell group within two frame periods. Is controlled to be lower than the data voltage driving frequency of the second liquid crystal cell group.

  If it is determined in step S232 that the currently input data is data in which no DC afterimage appears, the fourth embodiment of the present invention generates a reference polarity control signal (POL) in every frame period and The data voltage drive frequencies of the first and second liquid crystal cell groups are controlled to be the same. (S5)

  FIG. 24 shows a liquid crystal display device according to a fourth embodiment of the present invention.

  Referring to FIG. 24, the liquid crystal display device according to the fourth exemplary embodiment of the present invention includes a system 205, a liquid crystal display panel 200, a video analysis circuit 241, a timing controller 201, a logic circuit 242, a data driving circuit 203, and a gate driving circuit. 204. In this embodiment, the system 205, the liquid crystal display panel 200, the timing controller 201, the data driving circuit 203, and the gate driving circuit 204 are substantially the same as those of the above-described embodiment. Abbreviated.

  The video analysis circuit 241 determines whether the digital video data of the currently input video can generate a DC afterimage. The video analysis circuit 241 compares data between adjacent lines in one frame video, and determines that currently input data is interlaced data if the data between the lines is larger than a predetermined threshold value. Also, the video analysis circuit 241 compares the data of each pixel in units of frames, detects the moving image and the moving speed of the image in the displayed video, and moves the moving image when the moving image becomes constant at a preset speed. Frame data including an image is determined by scroll data. As a result of such video analysis, the video analysis circuit 241 generates a selection signal (SEL2) indicating interlace data or scroll data, and controls the logic circuit 242 using the selection signal (SEL2).

  In response to the first logic value of the selection signal (SEL2) from the video analysis circuit 161, the logic circuit 242 sends the first polarity control signals (POL1a to POL1d) in the 4i + 1 to 4i + 4 frame periods as shown in FIG. The second polarity control signal (FGDPOL) is sequentially generated during the fifth i frame period. When data different from data that can generate a DC afterimage such as interlace data and scroll data is input, the logic circuit 242 responds to the second logic value of the selection signal (SEL2) and performs reference in all frame periods. The polarity control signal (POL) is transmitted to the data driving circuit 203 as it is.

  The timing controller 201, the video analysis circuit 241 and the logic circuit 242 can be integrated on one chip.

  FIG. 25 shows a polarity pattern of data voltages supplied to the liquid crystal display device according to the fifth embodiment of the present invention.

  Referring to FIG. 25, in the driving method of the liquid crystal display device according to the fifth embodiment of the present invention, the polarity of the data voltage charged in the liquid crystal cell is inverted every two frame periods, and at the same time, adjacent in the horizontal direction. The polarity inversion period of the data voltage supplied to the liquid crystal cell is controlled to be different from each other.

  For example, the 4j + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) and the 4jj (j is a positive integer) +1 and 4j + 2 horizontal lines (R1, R2, R5, R6) during the Nth frame period. The liquid crystal cells arranged in the positive line are supplied with a positive (+) data voltage, and the 4j + 1 and 4j + 2 horizontal lines (R1, R2,..., 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) A liquid crystal cell arranged in R5, R6) is supplied with a negative (−) data voltage. During the Nth frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). (+) Data voltage is supplied.

  During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) have positive polarity (+ ) Is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8). The data voltage (−) is supplied. During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) have a negative polarity. A liquid crystal cell arranged on the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) with the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) supplied with the data voltage (−). Is supplied with a positive (+) data voltage.

  During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) have positive polarity. The (+) data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). A negative (−) data voltage is supplied. During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). (+) Data voltage is supplied.

  During the (N + 3) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have positive polarity (+ ) To the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). The data voltage (−) is supplied. During the (N + 3) th frame period, the liquid crystal cells arranged on the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have a negative polarity. A liquid crystal cell arranged on the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) on the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) is supplied with the data voltage of (−). Is supplied with a positive (+) data voltage.

  In the (N + 4) th frame period, the data voltage is supplied to the liquid crystal cell with the same polarity pattern as the Nth frame period, and in the (N + 5) th frame period, the data voltage is supplied to the liquid crystal cell in the same polarity pattern as the (N + 1) th frame period. The In the (N + 6) th frame period, the data voltage is supplied to the liquid crystal cell with the same polarity pattern as in the (N + 2) th frame period, and in the (N + 7) th frame period, the data voltage is supplied to the liquid crystal cell in the same polarity pattern as the (N + 3) th frame period. Is done.

  The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the horizontal direction and the vertical direction in each frame period, and the positions thereof are changed in units of one frame period.

  As can be seen in FIG. 25, the liquid crystal display device according to the fifth embodiment of the present invention has a data voltage whose polarity is inverted in two liquid crystal cell units (2-dot inversion) adjacent in the horizontal direction and the vertical direction. The liquid crystal cells are supplied to the liquid crystal cells, and the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged (one dot inversion) in each of the horizontal direction and the vertical direction. The first liquid crystal cell group can prevent a DC afterimage, and the second liquid crystal cell group can prevent flicker by increasing the spatial frequency at which the polarity of the data voltage changes on the screen of the liquid crystal display panel.

  26 to 30 show a liquid crystal display device according to a fifth embodiment of the present invention.

  Referring to FIG. 26, the liquid crystal display according to the fifth embodiment of the present invention includes a liquid crystal display panel 260, a timing controller 261, a logic circuit 262, a data driving circuit 263, a gate driving circuit 264, and a system 265. System 265 includes a line memory 266 for storing interlaced data. Since the liquid crystal display panel 260, the timing controller 261, the gate driving circuit 264, and the system 265 are substantially the same as those of the above-described embodiment, a detailed description thereof will be omitted.

  The logic circuit 262 receives a gate start pulse (GSP), a source output enable signal (SOE), and a reference polarity control signal (POL), and sequentially outputs polarity control signals as shown in FIGS. Alternatively, a reference polarity control signal (POL) is output. 25 and 31 shifts the polarity of the data voltage by one liquid crystal cell (one dot) along the vertical line direction for each frame. In addition, the logic circuit 262 generates a horizontal output inversion signal (HINV) for inverting the polarity of the data voltage output from some of the output channels of the data driving circuit to generate a horizontal line every frame. The polarity of the data voltage is shifted by one liquid crystal cell (one dot) along the direction. Such a logic circuit 262 can be incorporated in the timing controller 261.

  Under the control of the timing controller 261, the data driving circuit 263 latches digital video data (RGBodd, RGBeven), and the digital video data (RGBodd, RGBeven) is sent to the polarity control signals (POL / POL2a˜) from the logic circuit 262. In response to POL2d), the analog log positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines (D1 to Dm). In response to the polarity control signals (POL / POL2a to POL2d) from the logic circuit 262, the data driving circuit 263 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods. In addition, the data driving circuit 263 inverts the polarity of the data voltage output through some adjacent output channels in response to the horizontal output inversion signal (HINV) from the logic circuit 262.

  27 and 28 are circuit diagrams showing in detail the logic circuit 262 shown in FIG.

  Referring to FIGS. 27 and 28, the logic circuit 262 includes a frame counter 271, a line counter 272, a POL generation circuit 273, and a multiflexor 274.

  The frame counter 271 indicates the number of frames of an image displayed on the liquid crystal display panel 260 in response to a gate start pulse (GSP) generated once during one frame period and simultaneously with the start of one frame period. Frame count information (Fcnt) to be output. As shown in FIGS. 7 and 15, the frame count information (Fcnt) is 2 beats so that each of the four frame periods can be identified when the polarity pattern of the data voltage is repeated in a period of four frame periods. Generated on information.

  The line counter 272 responds to a source output enable signal (SOE) instructing the output time point of the data voltage from the data driving circuit 263 every horizontal period, and selects a row (or horizontal line) in which data is displayed on the liquid crystal display panel 260. The instructed line count information (Lcnt) is output. Line count information (Fcnt) is generated in 2-beat information.

  The POL generation circuit 273 generates the 1-beat horizontal output inversion signal (HINV) using the frame count information (Fcnt), and then, as shown in FIG. 12, the first POL generation circuit 281, the second POL generation circuit 282, The first to fourth polarity control signals (POL2a to POL2d) are sequentially generated using the first and second inverters (283 and 124) and the multiflexor 285. The logic of the horizontal output inversion signal (HINV) is inverted in units of one frame period as shown in FIG. 16, and the polarity pattern in the horizontal 2-dot and vertical 2-dot directions is shifted in the row direction as shown in FIGS. Thus, the output of the data driving circuit 263 is controlled. In order to generate a polarity pattern as shown in FIG. 25, the horizontal output inversion signal (HINV) is generated at a low logic in the Nth and N + 2th frame periods as shown by the solid line waveform in FIG. Generated high logic in the frame period. In order to generate the polarity pattern as shown in FIG. 31, the horizontal output inversion signal (HINV) is generated at a high logic in the Nth and N + 2th frame periods as shown by the dotted waveform in FIG. 32, and the N + 1th and N + 3th frames. Generated low logic over time. As shown in FIGS. 25 and 31, the horizontal 2-dot inversion method is an inversion method in which a data voltage whose polarity is inverted in units of two horizontally adjacent liquid crystal cells is supplied to the liquid crystal cell. The vertical two-dot inversion method is an inversion method in which a data voltage whose polarity is inverted in two liquid crystal cell units (2 dots) that are vertically adjacent to each other is supplied to the liquid crystal cell as shown in FIGS.

  The first POL generation circuit 281 generates a first polarity control signal (POL2a) whose logic is inverted by line counter information (Lcnt) and frame counter information (Fcnt). As shown in FIGS. 7 and 15, the first polarity control signal (POL2a) is generated at a high logic indicating the positive polarity (+) of the data voltage in the first horizontal line (R1) and the second horizontal line (R2). Thus, the logic is inverted in units of two rows from the first row to the n-th row. The first inverter 283 inverts the first polarity control signal (POL2a) to generate a third polarity control signal (POL2c) in the opposite phase of the first polarity control signal (POL2a). Accordingly, the third polarity control signal (POL2c) is generated in the low logic indicating the negative polarity (-) of the data voltage in the first horizontal line (R1) and the second horizontal line (R2). The logic is inverted in units of 2 lines up to n lines.

  The second POL generation circuit 282 generates a second polarity control signal (POL2b) whose logic is inverted by line counter information (Lcnt) and frame counter information (Fcnt). As shown in FIGS. 7 and 15, the second polarity control signal (POL2b) is generated at a low logic indicating the negative polarity (-) of the data voltage on the first horizontal line (R1). The logic is inverted in units of two lines up to the line. The second inverter 284 inverts the second polarity control signal (POL2b) to generate a fourth polarity control signal (POL2d) in the opposite phase of the second polarity control signal (POL2b). Accordingly, the fourth polarity control signal (POL2d) is generated in a high logic indicating the positive polarity (+) of the data voltage in the first horizontal line (R1), and is logically processed in units of two rows from the second row to the nth row. Is reversed.

  In response to the 2-beat frame count information (Fcnt), the multiflexor 285 outputs the first polarity control signal (POL2a) during the Nth frame period and then performs the second polarity control during the (N + 1) th frame period. After outputting the signal (POL2b), the third polarity control signal (POL2c) is output during the (N + 2) th frame period. The multiflexor 285 outputs the fourth polarity control signal (POL2d) during the (N + 3) th frame period.

  One of the first to fourth polarity control signals (POL2a to POLd) output from the POL generation circuit 273 and the reference polarity control signal (POL) generated by the internal circuit of the timing controller 261 is shown in FIG. As such, it is selected by the multiflexor 274. The multiflexor 274 selects the polarity control signals (POL2a to POL2d, POL) to be supplied to the data driving circuit 263 according to the logic value of the control terminal connected to the POL selection option pin. The POL selection option pin is connected to a control terminal of the multi-flexor 274 and can be selectively connected to a base voltage (GND) or a power supply voltage (Vcc) by a manufacturer or a user. For example, if the POL selection option pin is connected to the base voltage (GND) and the control terminal of the multiflexor 274, the multiflexor 274 is supplied with a selection control signal (SEL) of “0” to its control terminal. When the reference polarity control signal (POL) is output and the POL selection option pin is connected to the power supply voltage (Vcc) and the control terminal of the multiflexor 274, the multiflexor 274 is set to “1” on its control terminal. The selection control signal (SEL) is supplied to output the first to fourth polarity control signals (POL2a to POL2d) from the POL generation circuit 273. The selection control signal (SEL) of the multiflexor 274 can be replaced with a user selection signal input through the user interface or a selection control signal automatically generated according to the data analysis result as in the second embodiment described later. .

  29 and 30 are circuit diagrams showing the data driving circuit 263 in detail.

  29 and 30, each of the data driving circuits 263 includes a plurality of integrated circuits (Integrated Circuits, ICs) driving k (k is an integer smaller than m) data lines (D to Dk). Each of the integrated circuits includes a shift register 291, a data register 292, a first latch 293, a second latch 294, a digital / analog converter (hereinafter referred to as “DAC”) 295, a charge share circuit (Charge Share Circuit) 296, and an output circuit 297.

  The shift register 291 generates a sampling signal by shifting the source start pulse (SSP) from the timing controller 261 by the source sampling clock (SSC). Further, the shift register 291 shifts the source start pulse (SSP) and transmits the carry signal (CAR) to the shift register 291 of the next integrated circuit. The data register 292 temporarily stores odd digital video data (RGBodd) and even digital video data (RGBeven) separated by the timing controller 261 and supplies the stored data (RGBodd, RGBeven) to the first latch 293. The first latch 293 samples the digital video data (RGBeven, RGBodd) from the data register 292 in response to a sampling signal sequentially input from the shift register 291 and outputs the data (RGBeven, RGBodd) as one horizontal line. After latching every minute, data for one horizontal line is output simultaneously. The second latch 294 latches data for one horizontal line input from the first latch 293 and then latches simultaneously with the second latch 294 of another integrated circuit during the low logic period of the source output enable signal (SOE). Output the digital video data.

  As shown in FIG. 14, the DAC 295 includes a P-decoder (PDEC) 301 to which a positive gamma reference voltage (GH) is supplied, an N-decoder (NDEC) 302 to which a negative gamma reference voltage (GL) is supplied, and polarity control. First to fourth multiflexers (303a to 303d) for selecting the output of the P-decoder 301 and the output of the N-decoder 302 in response to the signals (POL / POL2a to POL2d), and the horizontal output inversion signal (HINV) Horizontal output inversion circuits (304a, 304b) for inverting the logic of the polarity control signals (POL / POL2a to POL2d) supplied to the control terminals of the second and fourth multiflexers (303b, 303d) in response to . The P-decoder 301 decodes the digital video data input from the second latch 294 and outputs a positive gamma compensation voltage corresponding to the gradation value of the data. The N-decoder 302 decodes the digital video data input from the second latch 294 and outputs a negative gamma compensation voltage corresponding to the gradation value of the data.

  The multiflexer 303 is controlled by the outputs of the first and third multiflexers (303a, 303c) directly controlled by the polarity control signals (POL / POL2a to POL2d) and the horizontal output inversion circuits (304a, 304b). Second and fourth multiflexors (303b, 303d) are provided. The first multiflexor 303a is responsive to the polarity control signals (POL / POL2a to POL2d) supplied to its non-inverting control terminal, and has a positive gamma compensation voltage and a negative gamma compensation voltage in units of two horizontal periods. Are alternately selected, and the selected positive / negative gamma compensation voltage is output to the analog data voltage. In response to the output of the horizontal output inverting circuit 304a supplied to its non-inverting control terminal, the second multiflexor 303b alternately switches the positive gamma compensation voltage and the negative gamma compensation voltage in units of two horizontal periods. The selected positive / negative gamma compensation voltage is output to the analog data voltage. In response to the polarity control signals (POL / POL2a to POL2d) supplied to its inversion control terminal, the third multiflexor 303c generates a positive gamma compensation voltage and a negative gamma compensation voltage in units of two horizontal periods. By alternately selecting, the selected positive / negative gamma compensation voltage is output as an analog data voltage. The fourth multiflexor 303d alternately selects the positive gamma compensation voltage and the negative gamma compensation voltage in units of two horizontal periods in response to the output of the horizontal output inversion circuit 304b supplied to its own inversion control terminal. Then, the selected positive / negative gamma compensation voltage is output to the analog data voltage.

  The horizontal output inverting circuits (304a, 304b) include switch elements (S1, S2) and an inverter 304. The horizontal output inversion circuits (304a, 304b) are supplied to the non-inversion control terminal of the second multiflexor 303b and the inversion control terminal of the fourth multiflexer 303d in response to the horizontal polarity inversion signal (HINV). Controls the logic value of the control signal. The input terminal of the first switch element (S1) is connected to the polarity control signal supply line 305, and the output terminal of the first switch element (S1) is inverted / non-inverted of the second or fourth multiflexer (303b, 303d). Connected to the control terminal. The non-inverting control terminal of the first switch element (S1) is connected to the horizontal output inverted signal supply line 306. The input terminal of the second switch element (S2) is connected to the polarity control signal supply line 305, and the output terminal of the second switch element (S2) is connected to the inverter 304. The inversion control terminal of the second switch element (S2) is connected to the horizontal output inversion signal supply line 306. The inverter 304 is connected to the output terminal of the second switch element (S2) and the inversion / non-inversion control terminal of the second or fourth multiflexor (303b, 303d).

  Referring to FIGS. 25, 31 and 32, when the horizontal output inversion signal (HINV) is high logic, the second switch element (S2) is turned on and the first switch element (S1) is turned off. Is done. Then, the inverted polarity control signals (POL / POL2a to POL2d) are supplied to the non-inversion control terminal of the second multiflexor 303b, and the polarity control is also inverted to the inversion control terminal of the fourth multiflexor 303d. Signals (POL / POL2a to POL2d) are supplied. As a result, when the polarity control signals (POL / POL2a to POL2d) are high logic and the horizontal output inversion signal (HINV) is high logic, the second multiflexor 303b receives the negative gamma compensation voltage from the N-decoder 302. To the data voltage supplied to the fourth i + 2 data line (D2, D6,..., Dm-2), and the fourth multiflexer 303d outputs the positive gamma compensation voltage from the P-decoder 301 to the fourth i + 4. Output to the data voltage supplied to the data lines (D4, D8,..., Dm). When the polarity control signal (POL / POL2a to POL2d) is low logic and the horizontal output inversion signal (HINV) is high logic, the second multiflexor 303b receives the positive gamma compensation voltage from the P-decoder 301 as the fourth i + 2. The fourth multiflexor 303d outputs the negative gamma compensation voltage from the N-decoder 302 to the fourth i + 4 data line (D2, D6,..., Dm-2). D4, D8,..., Dm).

  When the horizontal output inversion signal (HINV) is low logic, the first switch element (S331) is turned on and the second switch element (S332) is turned off. Then, the non-inverted polarity control signals (POL / POL2a to POL2d) are supplied to the non-inverted control terminals of the second multiflexor 303b, and the non-inverted control terminals of the fourth multiflexor 303d are also not inverted. Polarity control signals (POL / POL2a to POL2d) are supplied. As a result, when the polarity control signals (POL / POL2a to POL2d) are high logic and the horizontal output inversion signal (HINV) is low logic, the second multiflexor 303b receives the positive gamma compensation voltage from the P-decoder 301. Is output to the data voltage supplied to the fourth i + 2 data line (D2, D6,..., Dm-2), and the fourth multiflexor 303d receives the negative gamma compensation voltage from the N-decoder 302 as the fourth i + 4. Output to the data voltage supplied to the data lines (D4, D8,..., Dm). When the polarity control signal (POL / POL2a to POL2d) is low logic and the horizontal output inversion signal (HINV) is low logic, the second multiflexor 303b receives the negative gamma compensation voltage from the N-decoder 302 in the 4th i + 2 data line. The fourth multiflexor 303d outputs the negative gamma compensation voltage from the P-decoder 301 to the fourth i + 4 data line (D4, Dm, Dm-2). D8,..., Dm). Accordingly, the present invention uses the horizontal output inversion signal (HINV) and the polarity control signals (POL / POL2a to POL2d) to display the liquid crystal with the horizontal 2-dot and vertical 2-dot inversion polarity patterns as shown in FIGS. The data voltage supplied to the cell can be controlled.

  FIG. 31 shows another example of the polarity pattern of the data voltage according to the fifth embodiment of the present invention. FIG. 31 illustrates the polarity of the data voltage supplied to the 8 × 7 liquid crystal cells during the Nth to N + 3th frame periods.

  Referring to FIG. 31, during the Nth frame period, the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, and C8) are arranged on the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, and R6). The liquid crystal cell is supplied with a positive (+) data voltage, and the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). ) Is supplied with a negative (−) data voltage. During the Nth frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). (+) Data voltage is supplied. During the Nth frame period, the first liquid crystal cell group charged with the same polarity data voltage from the (N-1) th frame period having the same polarity pattern as that of the (N + 3) th frame period includes the 4i + 1 and 4i + 3 vertical lines (C1,. C3, C5, and C7), and the second liquid crystal cell group that charges the data voltage having the opposite polarity to the polarity of the (N-1) th frame period during the Nth frame period is the 4i + 2 and 4i + 4th. It includes liquid crystal cells arranged on vertical lines (C2, C4, C6, C8).

  During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) have positive polarity (+ ) Is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). The data voltage (−) is supplied. During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) have a negative polarity. A liquid crystal cell arranged on the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) with the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) supplied with the (−) data voltage. Is supplied with a positive (+) data voltage. During the (N + 1) th frame period, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the row direction and the column direction, respectively.

  During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) have positive polarity (+ ) Is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines (R1, R4, R5) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8). The data voltage (−) is supplied. During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) have a negative polarity. A liquid crystal cell arranged on the 4j + 2 and 4j + 3 horizontal lines (R2, R3, R6, R7) with the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) supplied with the data voltage (−). Is supplied with a positive (+) data voltage. During the (N + 2) th frame period, the first liquid crystal cell group that charges data voltages having the same polarity from the (N + 1) th frame period includes liquid crystal cells arranged on the 4i + 1 and 4i + 3 vertical lines (C1, C3, C5, C7). In addition, the second liquid crystal cell group that charges the data voltage having the opposite polarity to the polarity of the (N + 1) th frame period is disposed on the 4i + 2 and 4i + 4 vertical lines (C2, C4, C6, C8) during the (N + 2) th frame period. Includes liquid crystal cell.

  During the (N + 3) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have positive polarity. (+) Data voltage is supplied, and the liquid crystal cells are arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Is supplied with a negative (−) data voltage. During the (N + 3) th frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). (+) Data voltage is supplied. During the (N + 3) th frame period, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the horizontal direction and the vertical direction, respectively.

  In the (N + 4) th frame period, the data voltage is supplied to the liquid crystal cell with the same polarity pattern as the Nth frame period, and in the (N + 5) th frame period, the data voltage is supplied to the liquid crystal cell in the same polarity pattern as the (N + 1) th frame period. The In the (N + 6) th frame period, the data voltage is supplied to the liquid crystal cell with the same polarity pattern as in the (N + 2) th frame period, and in the (N + 7) th frame period, the data voltage is supplied to the liquid crystal cell in the same polarity pattern as the (N + 3) th frame period. Is done.

  FIG. 33 is a flowchart for explaining a driving method of the liquid crystal display device according to the sixth embodiment of the present invention.

  Referring to FIG. 33, the driving method of the liquid crystal display device according to the sixth embodiment of the present invention analyzes input data, and the input data may appear as a DC afterimage such as interlace data or scroll data. Determine whether the data. (S331, S332)

  If it is determined in step S332 that the currently input data is data that can generate a DC afterimage, the present invention sequentially applies the first to fourth polarity control signals (POL2a to POL2d) in units of frame periods. The data voltage driving frequency of the first liquid crystal cell group is controlled to be lower than the data voltage driving frequency of the second liquid crystal cell group during two frame periods. Further, the present invention generates a horizontal output inversion signal (HINV) and controls the polarity of the data voltage charged in the horizontally adjacent liquid crystal cells so as to be different in units of one frame period. (S333)

  If it is determined in step S332 that the currently input data is data in which no DC afterimage appears, the present invention reverses the polarity for each frame period in all frame periods. A control signal (POL) is generated to control the data voltage driving frequencies of the first and second liquid crystal cell groups to be the same. (S334)

  FIG. 34 shows a liquid crystal display device according to a sixth embodiment of the present invention.

  Referring to FIG. 34, the liquid crystal display according to the sixth embodiment of the present invention includes a system 265, a liquid crystal display panel 260, a video analysis circuit 341, a timing controller 261, a logic circuit 342, a data driving circuit 263, and a gate driving circuit. H.264. In this embodiment, the system 265, the liquid crystal display panel 260, the timing controller 261, the gate driving circuit 264, and the data driving circuit 263 are substantially the same as those in the fifth embodiment, so that the same reference numerals are assigned to the detailed description thereof. The explanation is omitted.

  The video analysis circuit 341 determines whether the digital video data of the currently input video can generate a DC afterimage. The video analysis circuit 341 compares data between adjacent lines in one frame video, and if the data between the lines is larger than a predetermined threshold value, the currently input data is determined by interlace data. The video analysis circuit 341 compares the data of each pixel for each frame, detects the moving image and the moving speed of the image in the display image, and if the moving image moves at a preset speed, the moving image is displayed. The included frame data is determined from the scroll data. As a result of such video analysis, the video analysis circuit 341 generates a selection signal (SEL2) for instructing interlace data or scroll data, and uses the selection signal (SEL2) to generate a logic circuit 342 as shown in FIG. To control.

  In response to the first logic value of the selection signal (SEL2) from the video analysis circuit 341, the logic circuit 342 sequentially generates first to fourth polarity control signals (POL2a to POL2d) as shown in FIG. A horizontal output inversion signal (HINV) is generated. The logic circuit 342 transmits the reference polarity control signal (POL) to the data driving circuit 263 as it is when data other than interlace data and scroll data is input in response to the second logic value of the selection signal (SEL2). .

  The data driving circuit 343 latches the digital video data (RGBodd, RGBeven) under the control of the timing controller 261, and the digital video data (RGBodd, RGBeven) is sent to the polarity control signals (POL / POL2a to POL2d) from the logic circuit 342. In response to the analog positive polarity / negative polarity gamma compensation voltage, a positive polarity / negative polarity analog data voltage is generated and the data voltage is supplied to the data lines D1 to Dm. In response to the polarity control signals (POL / POL2a to POL2d) from the logic circuit 342, the data driving circuit 343 inverts the polarity of the data voltage in the polarity pattern as shown in FIGS. Shift the polarity. In addition, the data driving circuit 343 shifts the polarity of the data voltage in the row direction in response to the horizontal output inversion signal (HINV) from the logic circuit 342 as shown in FIG.

  The timing controller 261, the video analysis circuit 341, and the logic circuit 342 can be integrated on one chip.

  FIG. 35 shows a polarity pattern of data voltages supplied to the liquid crystal display device according to the seventh embodiment of the present invention. The polarity of data voltages supplied to 8 × 7 liquid crystal cells during the Nth to (N + 3) th frame periods. FIG.

  Liquid crystal cells arranged in odd horizontal lines (R1, R3, R5, R7) in the 4i (i is a positive integer) +1 and 4i + 4 vertical lines (C1, C4, C5, C8) during the Nth frame period Is supplied with a positive (+) data voltage, and is arranged in odd horizontal lines (R1, R3, R5, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). Is supplied with a negative (−) data voltage. During the Nth frame period, the negative (−) data voltage is applied to the liquid crystal cells arranged on the even horizontal lines (R2, R4, R6) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8). And the positive (+) data voltage is supplied to the liquid crystal cells formed from the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) to the even horizontal lines (R2, R4, R6). Is done. The first liquid crystal cell group for preventing a DC afterimage during the Nth frame period includes liquid crystal cells arranged on even vertical lines, and the second liquid crystal cell group for preventing flicker is arranged on odd vertical lines. Liquid crystal cell.

  During the (N + 1) th frame period, the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have positive (+) polarity. When the data voltage is supplied, the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7) have a negative polarity (−). A data voltage is supplied. During the (N + 1) th frame period, the negative (−) data voltage is applied to the liquid crystal cells arranged on the even horizontal lines (R2, R4, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Is supplied, and a positive (+) data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines (R2, R4, R6) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7). Is done. The first liquid crystal cell group for preventing a DC afterimage during the (N + 1) th frame period includes liquid crystal cells arranged in odd vertical lines, and the second liquid crystal cell group for preventing flicker is arranged in even vertical lines. Liquid crystal cell.

  During the (N + 2) th frame period, the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have a negative polarity (−). The data voltage is supplied, and the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) have positive (+) polarity. A data voltage is supplied. During the (N + 2) th frame period, a positive (+) data voltage is applied to the liquid crystal cells arranged in the even horizontal lines (R2, R4, R6) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8). Is supplied to the liquid crystal cells formed from the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7) to the even horizontal lines (R2, R4, R6). Is done. The first liquid crystal cell group for preventing DC afterimages during the (N + 2) th frame period includes liquid crystal cells arranged in even vertical lines, and the second liquid crystal cell group for preventing flicker is arranged in odd vertical lines. Liquid crystal cell.

  During the (N + 3) th frame period, the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have a negative polarity (−). When the data voltage is supplied, the liquid crystal cells arranged on the odd horizontal lines (R1, R3, R5, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7) have positive (+) polarity. A data voltage is supplied. During the (N + 3) th frame period, a positive (+) data voltage is applied to the liquid crystal cells arranged in the even horizontal lines (R2, R4, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Is supplied, and the negative (−) data voltage is supplied to the liquid crystal cells arranged on the even horizontal lines (R2, R4, R6) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7). Is done. The first liquid crystal cell group for preventing a DC afterimage during the (N + 3) th frame period includes liquid crystal cells arranged on odd vertical lines, and the second liquid crystal cell group for preventing flicker is arranged on even vertical lines. Liquid crystal cell.

  36 to 38 show a liquid crystal display device according to a seventh embodiment of the present invention.

  Referring to FIG. 36, the liquid crystal display device according to the first embodiment of the present invention includes a system 365, a liquid crystal display panel 360, a timing controller 361, a data driving circuit 363, and a gate driving circuit 364. System 365 includes a line memory 366 for storing interlaced data. Since the system 365, the liquid crystal display panel 360, and the gate driving circuit 364 are substantially the same as those of the above-described embodiment, a detailed description thereof will be omitted.

  The timing controller 361 receives timing signals such as a vertical / horizontal synchronization signal (Vsync, Hsync), data enable (Data Enable), and a clock signal (CLK) and controls operation timings of the data driving circuit 363 and the gate driving circuit 364. A control signal for generating Such control signals include gate timing control signals such as a gate start pulse (GSP), a gate shift clock signal (Gate Shift Clock: GSC), and a gate output enable signal (Gate Output Enable: GOE). The control signal includes a source start pulse (source start pulse: SSP), a source sampling clock (source sampling clock: SSC), a source output enable signal (source output enable: SOE), a polarity control signal (polarity: POL2), and a horizontal signal. Includes output inversion signal (HINV). A gate start pulse (GSP) indicates a starting horizontal line where scanning starts within one vertical period in which one screen is displayed. The gate shift clock signal (GSC) is input to a shift register in the gate drive circuit 364, and a pulse width corresponding to the on period of the TFT as a timing control signal for sequentially shifting the gate start pulse (GSP). Generated. The gate output enable signal (GOE) instructs the output of the gate drive circuit 364. A source start pulse (SSP) indicates a start pixel in one horizontal line on which data is displayed. The source sampling clock (SSC) instructs a data latch operation in the data driving circuit 363 with reference to a rising or falling edge. A source output enable signal (Source Output Enable: SOE) instructs the output of the data driving circuit 363. The polarity control signal (POL2) indicates the polarity of the data voltage supplied to the liquid crystal cell (Clc) of the liquid crystal display panel 360. The logic of the polarity control signal (POL2) is inverted in one horizontal period cycle as shown in FIG. 35, or the logic is inverted in two horizontal period cycles as shown in FIG. The horizontal output inversion signal (HINV) is a control signal for inverting a partial output of the data driving circuit 363 and shifting the horizontal polarity pattern of the data voltage in units of frame periods.

  The timing controller 361 separates the input digital video data (RGB) into odd pixel data (RGBodd) and even pixel data (RGBeven) to lower the transmission frequency of the digital video data, and the data (RGBodd, RGBeven). Are supplied to the data driving circuit 363 through six data buses.

  The data driving circuit 363 latches digital video data (RGBod, RGBeven) under the control of the timing controller 361, converts the digital video data with an analog positive / negative gamma compensation voltage, and converts the polarity control signal (POL2). And a data voltage having a polarity selected by the horizontal output inversion signal (HINV) is supplied to the data lines (D1 to Dm). The data driving circuit 363 selects the polarity of the data voltage supplied to the liquid crystal cells arranged along the vertical direction in response to the polarity control signal (POL2). Further, the data driving circuit 363 selects the polarity of the data voltage supplied to the liquid crystal cells arranged along the horizontal direction by the horizontal output inversion signal (HINV). During the Nth and (N + 2) th frame periods, the horizontal output inversion signal (HIND) is generated at a high logic H, and the data driving circuit 363 responds to the horizontal output inversion signal along the horizontal direction as shown in FIG. The polarity of the data voltage supplied to the four liquid crystal cells arranged is selected by “+ −− +” or “− +++ −”. During the (N + 1) th and (N + 3) th frame periods, the horizontal output inversion signal (HINV) is generated at a low logic (L), and in response to the horizontal output inversion signal, the data driving circuit 363 performs a row operation as shown in FIG. The polarity of the data voltage supplied to the four liquid crystal cells arranged in the direction is selected by “+ + − −” or “− − + +”.

  37 and 38 are circuit diagrams illustrating the data driving circuit 363 in detail.

  37 and 38, each of the data driving circuits 363 includes a plurality of integrated circuits (Integrated Circuits, ICs) that drive k (k is an integer smaller than m) data lines (D to Dk). Each integrated circuit includes a shift register 371, a data register 372, a first latch 373, a second latch 374, a DAC 375, a charge share circuit 376, and an output circuit 377.

  The shift register 371 generates a sampling signal by shifting the source start pulse (SSP) from the timing controller 361 by the source sampling clock (SSC). Further, the shift register 371 shifts the source start pulse (SSP) and transmits the carry signal (CAR) to the shift register 371 of the next stage integrated circuit. The data register 372 temporarily stores odd digital video data (RGBodd) and even digital video data (RGBeven) separated by the timing controller 361 and supplies the stored data (RGBodd, RGBeven) to the first latch 373. The first latch 373 samples digital video data (RGBeven, RGBodd) from the data register 372 in response to a sampling signal sequentially input from the shift register 371 and latches the data (RGBeven, RGBodd). The latched data is output simultaneously. The second latch 374 latches the data input from the first latch 373 and then outputs the latched data simultaneously with the second latch 374 of another integrated circuit during the low logic period of the source output enable signal (SOE). To do.

  As shown in FIG. 38, the DAC 375 includes a P-decoder (PDEC) 381 to which a positive gamma reference voltage (GH) is supplied, an N-decoder (NDEC) 382 to which a negative gamma reference voltage (GL) is supplied, and a polarity control signal. In response to (POL2), a multiflexer (383a to 383d) that selects an output of the P-decoder 381 and an output of the N-decoder 382, and a multiflexer (383a) in response to the horizontal output inversion signal (HINV) To 383d) horizontal output inversion circuits (384a, 384b) for inverting the logic of the selection control signal supplied to the control terminals. The P-decoder 381 decodes the digital video data input from the second latch 374 and outputs a positive gamma compensation voltage corresponding to the gradation value of the data. The N-decoder 382 is input from the second latch 374. The digital video data is decoded and a negative gamma compensation voltage corresponding to the gradation value of the data is output.

  The multiflexers 383a to 383d are connected to the 4i + 1 data lines (D1, D5, D9... Dm-3), and output the data voltage to the 4i + 1 multiflexer 383a, the 4i + 2 data lines ( D4, D6, D10... Dm-2) connected to the 4i + 2 multiflexor 383b and the 4i + 3 data lines (D3, D7, D11. A fourth i + 3 multiflexor 383c for outputting the data voltage to the output channel, and a fourth i + 4 multiflexer for outputting the data voltage to the output channel connected to the fourth i + 4 data lines (D4, D8, D12... Dm). 383d. The fourth i + 1 multiflexor 383a selects one of the positive data voltage and the negative data voltage in response to the non-inverted logical value of the polarity control signal (POL2). The fourth i + 2 multiflexor 383b responds to the inverted logic value of the polarity control signal (POL2) whose logic value is selectively inverted by the first horizontal output inverting circuit 384a, and outputs the positive polarity data voltage and the negative polarity data voltage. Select one of them. The fourth i + 3 multiflexor 383c selects one of the positive data voltage and the negative data voltage in response to the inverted logic value of the polarity control signal (POL2). The fourth i + 4 multiflexor 383d is responsive to the non-inverted logic value of the polarity control signal (POL2) whose logic value is selectively inverted by the second horizontal output inverting circuit 384b. Select one of them.

  The horizontal output inverting circuits 384a and 384b are a first horizontal output inverting circuit 384a for selectively inverting the polarity control signal (POL2) supplied to the inverting control terminal of the 4i + 2 multiflexor 383b, and a 4i + 4 multiflexor. A second horizontal output inverting circuit 384b for selectively inverting the polarity control signal (POL2) supplied to the non-inverting control terminal of 383d is provided.

  The first horizontal output inversion circuit 384a inverts the first and second switch elements (S1, S2) to which the polarity control signal (POL2) is supplied in parallel, the second switch element (S2), and the 4i + 2 multiflexor 383b. A first inverter 385a is connected between the control terminals. The first horizontal output inverting circuit 384a is supplied to the inverting control terminal of the 4i + 2 multiflexor 383b during the Nth and N + 2th frame periods in response to a high logic H horizontal output inverting signal (HINV). While maintaining the logic of the control signal (POL2), the logic of the polarity control signal (POL2) supplied to the inversion control terminal of the 4i + 2 multiflexor 383b is inverted during the (N + 1) th and (N + 3) th frame periods.

  The second horizontal output inverting circuit 384b is connected to the third and fourth switch elements (S3, S4), the fourth switch element (S4), and the fourth i + 4 multiflexor 383d to which the polarity control signal (POL2) is supplied in parallel. A second inverter 385b is connected between the inversion control terminals. The third switch element S3 is turned on in response to the high logic H of the horizontal output inversion signal (HINV) to supply the polarity control signal (POL2) to the non-inversion control terminal of the 4i + 4 multiflexor 383d. The fourth switch element (S4) is turned on in response to the low logic (L) of the horizontal output inversion signal (HINV) and supplies the polarity control signal (POL2) to the second inverter 385b to supply the fourth i + 4 multiflex. The inverted polarity control signal (POL2) is supplied to the non-inverting control terminal of the server 383d. Accordingly, the second horizontal output inversion circuit 384b is supplied to the non-inversion control terminal of the 4i + 4 multiflexor 383d during the Nth and N + 2 frame periods in response to the horizontal output inversion signal (HINV) of high logic H. While maintaining the logic of the polarity control signal (POL2), the 4i + 4 multiflexor 383d is switched between the (N + 1) th and (N + 3) th frame periods in response to the horizontal output inversion signal (HINV) of the low logic (L). The logic of the polarity control signal (POL2) supplied to the inversion control terminal is inverted.

  FIG. 39 is a waveform diagram showing a polarity control signal (POL2) and a horizontal output inversion signal (HINV) for controlling the circuit of FIG.

  35 and 38, the logic of the polarity control signal (POL2) is inverted in units of one horizontal period, and the logic of the horizontal output inversion signal (HINV) is inverted in units of one frame period. Therefore, as shown in FIG. 35, the liquid crystal cell is driven in the vertical 1-dot inversion method (V1dot) in the column direction and is driven in the horizontal 2-dot inversion method (H2dot) in the row direction. Here, the polarity of the data voltage is shifted in the row direction every frame by the horizontal output conversion signal.

  FIG. 40 is a flowchart for explaining a driving method of the liquid crystal display device according to the eighth embodiment of the present invention.

  Referring to FIG. 40, the driving method of the liquid crystal display device according to the eighth embodiment of the present invention analyzes input data, and a DC afterimage can appear as the input data is interlaced data or scroll data. Determine whether the data. (S401, S402)

  If it is determined in step S402 that the currently input data is a data that can generate a DC afterimage, the present invention enables the horizontal output inversion signal (HINV). (S403)

  In step S402, if it is determined that the currently input data is data that does not show a DC afterimage, the present invention reverses the polarity of the data voltage charged in all the liquid crystal cells every frame period. The horizontal output inversion signal (HINV) is disabled. (S404)

  FIG. 41 shows a liquid crystal display device according to an eighth embodiment of the present invention.

  Referring to FIG. 41, the liquid crystal display according to the eighth embodiment of the present invention includes a system 365, a liquid crystal display panel 360, a video analysis circuit 412, a timing controller 411, a data driving circuit 363, and a gate driving circuit 364. In this embodiment, the system 365, the liquid crystal display panel 360, the data driving circuit 363, and the gate driving circuit 364 are substantially the same as those of the above-described embodiment of FIG. To do.

  The video analysis circuit 412 determines whether the digital video data of the currently input video can generate a DC afterimage. The video analysis circuit 412 compares the data between adjacent lines in one frame video, and if the data between the lines is larger than a predetermined threshold value, it determines the currently input data from the interlace data. The video analysis circuit 412 compares the data of each pixel in units of frames, detects the moving image and the moving speed of the image in the display image, and when the moving image moves at a preset speed, the moving image is displayed. The included frame data is determined from the scroll data. As a result of such video analysis, the video analysis circuit 412 supplies a signal indicating interlace data or scroll data to the timing controller 411.

  The timing controller 411 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable (Data Enable), and a clock signal (CLK), and controls operation timings of the data driving circuit 363 and the gate driving circuit 364. A control signal for generating Among the data timing control signals, the polarity control signal (POL2) indicates the polarity of the data voltage supplied to the liquid crystal cell (Clc) of the liquid crystal display panel 360. The polarity control signal (POL2) is inverted in logic in one horizontal period as shown in FIG. The horizontal output inversion signal (HINV) is generated from the timing controller 411 when data that can present a direct current afterimage as a result of analysis by the video analysis circuit 412 is input, as shown in FIG. 35, FIG. 38 and FIG. The polarity of one of the data voltages supplied to two adjacent data lines in the horizontal direction is inverted, and the polarity of the data voltage is shifted by one dot in the horizontal direction in units of one frame period.

  The data driving circuit 363 latches digital video data (RGBodd, RGBeven) under the control of the timing controller 411, and converts the digital video data with an analog positive / negative gamma compensation voltage. When data capable of generating a DC afterimage is input, the data driving circuit 363 uses the polarity control signal (POL2) and the horizontal output inversion signal (HINV) to generate two horizontal dots and one vertical dot in as shown in FIG. A data voltage whose polarity is changed by the version method is supplied to the data lines (D1 to Dm). When data that does not show a DC afterimage is input, the data driving circuit 363 determines the polarity of the data voltage only by the polarity control signal (POL2).

  FIG. 42 shows another polarity pattern of the data voltage supplied to the liquid crystal display devices according to the seventh and eighth embodiments of the present invention, and is supplied to 8 × 7 liquid crystal cells during the Nth to N + 3th frame periods. It is the figure which illustrated the polarity of data voltage.

  Referring to FIG. 42, during the Nth frame period, the 4j + 1 and 4i + 4 vertical lines (C1, C4, C5, and C8) are 4j (j is an integer greater than or equal to 0) +1 and the 4j + 2 horizontal lines (R1,. The liquid crystal cells arranged in R2, R5, and R6) are supplied with a positive (+) data voltage, and the 4j + 1 and 4j + 2 horizontal lines in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, and C7). The liquid crystal cells arranged in the lines (R1, R2, R5, R6) are supplied with a negative (−) data voltage. During the Nth frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). (+) Data voltage is supplied. The first liquid crystal cell group for preventing a DC afterimage during the Nth frame period includes liquid crystal cells arranged on even vertical lines, and the second liquid crystal cell group for preventing flicker is arranged on odd vertical lines. Liquid crystal cell.

  During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have positive polarity. The (+) data voltage is supplied and the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7). Is supplied with a negative (−) data voltage. During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have a negative polarity (− ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7). (+) Data voltage is supplied. The first liquid crystal cell group for preventing a DC afterimage during the (N + 1) th frame period includes liquid crystal cells arranged in odd vertical lines, and the second liquid crystal cell group for preventing flicker is arranged in even vertical lines. Liquid crystal cell.

  During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have a negative polarity. A liquid crystal cell arranged on the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, and R6) by the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, and C7) and supplied with the data voltage of (−). Is supplied with a positive (+) data voltage. During the (N + 2) th frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 4 vertical lines (C1, C4, C5, C8) have positive polarity (+ ) Is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 2 and 4i + 3 vertical lines (C2, C3, C6, C7). The data voltage (−) is supplied. The first liquid crystal cell group for preventing DC afterimages during the (N + 2) th frame period includes liquid crystal cells arranged in even vertical lines, and the second liquid crystal cell group for preventing flicker is arranged in odd vertical lines. Liquid crystal cell.

  During the (N + 3) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have negative polarity. The liquid crystal cells arranged on the 4j + 1 and 4j + 2 horizontal lines (R1, R2, R5, R6) on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7) are supplied with the (−) data voltage. Is supplied with a positive (+) data voltage. During the (N + 3) th frame period, the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) have positive polarity (+ ) To the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines (R3, R4, R7) in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C6, C7). The data voltage (−) is supplied. The first liquid crystal cell group for preventing a DC afterimage during the (N + 3) th frame period includes liquid crystal cells arranged on odd vertical lines, and the second liquid crystal cell group for preventing flicker is arranged on even vertical lines. Liquid crystal cell.

  The polarity of the data voltage in FIG. 42 is controlled by a polarity control signal (POL2) whose logic is inverted in units of two horizontal periods and a horizontal output inversion signal (HINV) whose polarity is inverted in units of one frame period.

  As described above, in the liquid crystal display device and the driving method thereof according to the embodiment of the present invention, the driving frequency of the data voltage supplied to the first liquid crystal cell group of the liquid crystal display panel is controlled to be DC within two frame periods. In addition to preventing afterimages and controlling the drive frequency of the data voltage supplied to the second liquid crystal cell group to prevent flicker and improving display quality, frames with irregular polarity patterns are periodically inserted. Thus, the regularity of the position of the first and second liquid crystal cell groups is lowered to minimize the regular luminance change.

  43A to 45B are diagrams illustrating polar patterns of various data voltages applicable to the liquid crystal display device according to the ninth embodiment of the present invention.

  Referring to FIGS. 43A and 43B, during the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group is aligned with the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). And the 4i + 2 vertical line (C1, C2, C5, C6), and the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) are the 4i + 3 and 4i + 4 vertical lines (C3). , C4, C7, C8). The second liquid crystal cell group is disposed in the vertical and horizontal directions with the first liquid crystal cell group interposed therebetween, and the 4i + 3 and 4i + 4 vertical lines (4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, and L7)) ( C3, C4, C7, C8), and the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) and the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). ) Disposed in the liquid crystal cell (Clc). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells in the first liquid crystal cell group and the liquid crystal cells in the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having the same polarity. Therefore, the polarity of the first polarity control signal (POLa) generated during the 4i + 1 frame period is inverted in units of two horizontal periods corresponding to the two horizontal synchronization signals. The data driving circuit supplies two adjacent liquid crystal cells horizontally in the 4i + 1 frame period in response to the first polarity control signal (POLa) in response to the two adjacent liquid crystal cells. The data voltage having the same polarity is output through the output channel, and the polarity of the data voltage is inverted in units of two output channels. In addition, the data driving circuit changes the polarity of the data voltage in units of two horizontal periods in response to the first polarity control signal (POLa) in order to invert the polarity of the data voltage in units of two horizontal periods during the 4i + 1 frame period. Invert. During the 4i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  During the 4i + 2 frame period, the first liquid crystal cell group is disposed on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). A liquid crystal cell (Clc), and a liquid crystal cell (Clc) disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5), and 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having different polarities. Therefore, the polarity of the second polarity control signal (POLb) generated during the 4i + 2 frame period is inverted in units of one horizontal period. In order to invert the polarity of the data voltage in units of one liquid crystal cell in the vertical and horizontal directions during the 4i + 2 frame period, the data driving circuit is connected to the adjacent output channel in response to the second polarity control signal (POLb). Thus, data voltages having different polarities are output and the polarity of the data voltage is inverted in units of one horizontal period. During the 4i + 2 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

  During the 4i + 3 frame period, the first liquid crystal cell group is disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) in the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) including liquid crystal cells (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in the 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells in the first liquid crystal cell group and the liquid crystal cells in the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having the same polarity. The polarity of the data voltage supplied to the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 3 frame period is opposite to the polarity of the data voltage generated during the 4i + 1 frame period. Therefore, the polarity of the third polarity control signal (POLc) generated during the 4i + 3 frame period is inverted every two horizontal periods, and the phase is inverted with respect to the first polarity control signal (POLa). . The data driving circuit supplies two adjacent outputs in response to the third polarity control signal (POLc) in order to supply data voltages having the same polarity to two horizontally adjacent liquid crystal cells during the 4i + 3 frame period. Data voltages having the same polarity are output through the channels, and the polarity of the data voltages is inverted in units of two output channels. In addition, the data driving circuit changes the polarity of the data voltage in units of two horizontal periods in response to the third polarity control signal (POLc) in order to invert the polarity of the data voltage in units of two horizontal periods during the 4i + 3 frame period. Invert. During the 4i + 3 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  During the 4i + 4 frame period, the first liquid crystal cell group is disposed on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). A liquid crystal cell (Clc), and a liquid crystal cell (Clc) disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5), and 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in the 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent thereto are charged with data voltages having different polarities. The polarity of the data voltage supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 4 frame period is opposite to the polarity of the data voltage generated during the 4i + 2 frame period. Therefore, the polarity of the fourth polarity control signal (POLd) generated during the 4i + 4 frame period is inverted in units of one horizontal period, and the phase is inverted with respect to the second polarity control signal (POLb). . In order to invert the polarity of the data voltage in units of one liquid crystal cell in the vertical and horizontal directions during the 4i + 4 frame period, the data driving circuit is connected to the adjacent output channel in response to the fourth polarity control signal (POLd). Thus, data voltages having different polarities are output and the polarity of the data voltage is inverted in units of one horizontal period. During the 4i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

  Referring to FIGS. 44A and 44B, during the 4i + 1 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 horizontal lines (L2, L3, L6, L7) and the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) including liquid crystal cells (Clc), and 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) in 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). A liquid crystal cell (Clc) is disposed. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5), and 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in the 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent thereto are charged with data voltages having different polarities. Therefore, the polarity of the first polarity control signal (POLa) generated during the 4i + 1 frame period is inverted in units of one horizontal period. In order to invert the polarity of the data voltage in the unit of one liquid crystal cell in each of the vertical and horizontal directions during the 4i + 1 frame period, the data driving circuit responds to the first polarity control signal (POLa) to adjacent output channels. Thus, data voltages having different polarities are output and the polarity of the data voltage is inverted in units of one horizontal period. During the 4i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

  During the 4i + 2 frame period, the first liquid crystal cell group is disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) in the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) including liquid crystal cells (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells in the first liquid crystal cell group and the liquid crystal cells in the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having the same polarity. Therefore, the polarity of the second polarity control signal (POLb) generated during the 4i + 2 frame period is inverted every two horizontal periods. The data driving circuit supplies two adjacent outputs in response to the second polarity control signal (POLb) in order to supply data voltages having the same polarity to two horizontally adjacent liquid crystal cells during the 4i + 2 frame period. Data voltages having the same polarity are output through the channels, and the polarity of the data voltages is inverted in units of two output channels. In addition, the data driving circuit changes the polarity of the data voltage in units of two horizontal periods in response to the second polarity control signal (POLb) in order to invert the polarity of the data voltage in units of two horizontal periods during the 4i + 2 frame period. Invert. During the 4i + 2 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  During the 4i + 3 frame period, the first liquid crystal cell group is disposed on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). A liquid crystal cell (Clc), and a liquid crystal cell (Clc) disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5), and 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having different polarities. The polarity of the data voltage supplied to the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 3 frame period is opposite to the polarity of the data voltage generated during the 4i + 1 frame period. For this reason, the polarity of the third polarity control signal (POLc) generated during the 4i + 3 frame period is inverted in the unit of one horizontal period and is inverted with respect to the first polarity control signal (POLa). Generated. In order to invert the polarity of the data voltage in units of one liquid crystal cell in each of the vertical and horizontal directions during the 4i + 3 frame period, the data driving circuit is connected to the adjacent output channel in response to the third polarity control signal (POLc). Data voltages having different polarities are output, and the polarity of the data voltage is inverted in units of one horizontal period. During the 4i + 3 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

  During the 4i + 4 frame period, the first liquid crystal cell group is disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) in the 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) on the 4i + 2 and 4i + 3 horizontal lines (L2, L3, L6, L7). , And 4i + 1 and 4i + 4 horizontal lines (L1, L4, L5) including liquid crystal cells (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Each of the first and second liquid crystal cell groups is arranged in 2 × 2 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 2 liquid crystal cell are contradictory. The liquid crystal cells in the first liquid crystal cell group and the liquid crystal cells in the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having the same polarity. The polarity of the data voltage supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 4 frame period is opposite to the polarity of the data voltage generated during the 4i + 2 frame period. For this reason, the polarity of the fourth polarity control signal (POLd) generated during the 4i + 4 frame period is inverted in the unit of two horizontal periods and inverted to the logic of the second polarity control signal (POLb). Generated. The data driving circuit supplies two adjacent outputs in response to the fourth polarity control signal (POLd) in order to supply data voltages of the same polarity to two horizontally adjacent liquid crystal cells during the 4i + 4 frame period. Data voltages having the same polarity are output through the channels, and the polarity of the data voltages is inverted in units of two output channels. The data driving circuit inverts the polarity of the data voltage in units of two horizontal periods in response to the fourth polarity control signal (POLd) in order to invert the polarity of the data voltage in units of two horizontal periods during the 4i + 4 frame period. Let During the 4i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  Referring to FIGS. 45A and 45B, during the 4i + 1 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7) and the 4i + 1 and 4i + 2 vertical lines (C1, C4, C5, and C6), and the 4i + 2 and 4i + 4 horizontal lines (L2, L4, and L6) include the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, and C8). A liquid crystal cell (Clc) is disposed. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) on the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7). , And 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6), and 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Each of the first and second liquid crystal cell groups is arranged in 2 × 1 liquid crystal cell units adjacent in the horizontal direction. The polarities of adjacent liquid crystal cells in such a 2 × 1 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent to the first liquid crystal cell group are charged with data voltages having different polarities. Therefore, the polarity of the first polarity control signal (POLa) generated during the 4i + 1 frame period is inverted every two horizontal periods. In order to invert the polarity of the data voltage in units of two horizontal periods by supplying data voltages having different polarities to the horizontally adjacent liquid crystal cells during the 4i + 1 frame period, the data driving circuit In response to POLa), the polarity of the data voltage is inverted. During the 4i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1-dot inversion (H1D) and vertical 2-dot inversion (V2D) system.

  During the 4i + 2 frame period, the first liquid crystal cell group is disposed in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) with the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) in the 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) by the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7). , And 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6), and 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8). Each of the first and second liquid crystal cell groups is arranged in 2 × 1 liquid crystal cell units adjacent in the horizontal direction. The polarity of the data voltage charged in such a liquid crystal cell is contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent thereto are charged with data voltages having different polarities. For this reason, the polarity of the second polarity control signal (POLb) generated during the 4i + 2 frame period is inverted in units of two horizontal periods, and is about one horizontal period relative to the first polarity control signal (POLa). Generated in the phase difference. The data driving circuit supplies data voltages having different polarities to horizontally adjacent liquid crystal cells during the 4i + 2 frame period and inverts the polarity of the data voltage in units of two horizontal periods. In response to POLb), the polarity of the data voltage is inverted. During the 4i + 2 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  During the 4i + 3 frame period, the first liquid crystal cell group is disposed on the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, and L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) in the 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystal cells (Clc) arranged on the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) on the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7). , And 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6), and 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6). Each of the first and second liquid crystal cell groups is arranged in 2 × 1 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 1 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent thereto are charged with data voltages having different polarities. The polarity of the data voltage supplied to the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 3 frame period is opposite to the polarity of the data voltage generated during the 4i + 1 frame period. For this reason, the polarity of the third polarity control signal (POLc) generated during the 4i + 3 frame period is inverted every two horizontal periods and is inverted to the logic of the first polarity control signal (POLa). Generated. The data driving circuit supplies two adjacent outputs in response to the third polarity control signal (POLc) in order to supply data voltages having the same polarity to two horizontally adjacent liquid crystal cells during the 4i + 3 frame period. Data voltages having the same polarity are output through the channels, and the polarity of the data voltages is inverted in units of two output channels. In addition, the data driving circuit supplies the data voltages having different polarities to the horizontally adjacent liquid crystal cells during the 4i + 2 frame period and reverses the polarity of the data voltage in units of two horizontal periods. The polarity of the data voltage is inverted in response to the signal (POLc). During the 4i + 3 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1-dot inversion (H1D) and vertical 2-dot inversion (V2D) system.

During the 4i + 4 frame period, the first liquid crystal cell group is arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) with the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7). Including the liquid crystal cell (Clc), including the liquid crystal cell (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) in the 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6). . The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. The second liquid crystal cell includes liquid crystal cells (Clc) arranged in the 4i + 1 and 4i + 2 vertical lines (C1, C2, C5, C6) at the 4i + 1 and 4i + 3 horizontal lines (L1, L3, L5, L7), It includes liquid crystal cells (Clc) arranged in the 4i + 3 and 4i + 4 vertical lines (C3, C4, C7, C8) in the 4i + 2 and 4i + 4 horizontal lines (L2, L4, L6). Each of the first and second liquid crystal cell groups is arranged in 2 × 1 liquid crystal cell units adjacent in the vertical and horizontal directions. The polarities of adjacent liquid crystal cells in such a 2 × 1 liquid crystal cell are contradictory. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group adjacent thereto are charged with data voltages having different polarities. The polarity of the data voltage supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the 4i + 4 frame period is opposite to the polarity of the data voltage generated during the 4i + 2 frame period. For this reason, the polarity of the fourth polarity control signal (POLd) generated during the 4i + 4 frame period is inverted in the unit of two horizontal periods and inverted to the logic of the second polarity control signal (POLb). Generated. In order to invert the polarity of the data voltage in units of two horizontal periods by supplying the data voltages having different polarities to the horizontally adjacent liquid crystal cells during the 4i + 4 frame period, the data driving circuit The polarity of the data voltage is inverted in response to POLd). During the 4i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal 2-dot inversion (H2D) and vertical 2-dot inversion (V2D) system.

  According to the experimental results of measuring the optical waveform by installing an optical sensor on the liquid crystal display panel, if the first liquid crystal cell group is driven to 30 Hz and the second liquid crystal cell group is driven to 60 Hz, as shown in FIG. The optical waveform of the liquid crystal display panel was measured at 60 Hz by the second liquid crystal cell group. This is because the light waveform measured by the liquid crystal display panel is determined by the light conversion period of the second liquid crystal cell group having a higher drive frequency than the first liquid crystal cell having a lower drive frequency within two frame periods.

  FIG. 47 shows a liquid crystal display device according to the ninth embodiment of the present invention.

  47, the liquid crystal display according to the ninth embodiment of the present invention includes a system 475 including a line memory 476, a liquid crystal display panel 100, a timing controller 471, a POL logic circuit 472, a data driving circuit 473, and a gate driving circuit. 474 and a horizontal dot inversion logic circuit 477. Since the system 475, the liquid crystal display panel 100, and the gate driving circuit 474 are substantially the same as those of the above-described embodiment, a detailed description thereof will be omitted.

  The timing controller 471 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable (Data Enable), and a clock signal (CLK), and receives a data driving circuit 473, a gate driving circuit 474, and a POL logic circuit 472. A control signal for controlling the operation timing is generated. Such control signals include a gate start pulse (Gate Start Pulse: GSP), a gate shift clock signal (Gate Shift Clock: GSC), a gate output enable signal (Gate Output Enable: GOE), and a source start pulse (Source Start Pulse: SSP). ), A source sampling clock (SSC), a source output enable signal (Source Output Enable: SOE), and a reference polarity control signal (Polarity: POL).

  The POL logic circuit 472 receives a gate start pulse (GSP), a source output enable signal (SOE), and a reference polarity control signal (POL) and sequentially receives polarity control signals (POLa to POLd) for preventing afterimage and flicker. Or the same reference polarity control signal (POL) is selectively output for each frame. For this purpose, the POL logic circuit 472 includes circuits as shown in FIGS.

  The data driving circuit 473 latches the digital video data (RGBodd, RGBeven) under the control of the timing controller 471, and responds to the polarity control signal (POL / POLa to POLd) from the POL logic circuit 472. The analog positive polarity / negative polarity gamma compensation voltage is converted to generate a positive polarity / negative polarity analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 473 controls the polarity of the data voltage in the vertical direction in response to the polarity control signals (POL / POLa to POLd). Further, in response to the H2 / H1 inversion signal (DINV) from the horizontal dot inversion logic circuit 477, the data driving circuit 473 sets the horizontal polarity of the data voltage to the horizontal 2-dot inversion method (H2) and the horizontal 1-dot inversion. Alternate with Bangsik (H1). In the horizontal 1-dot inversion method (H1), voltages having different polarities are supplied to liquid crystal cells horizontally adjacent within one horizontal period. In the horizontal 2-dot inversion method (H2), the polarity of the data voltage is inverted in the period of two adjacent liquid crystal cells within one horizontal period.

  The H2 / H1 inversion signal (DINV) is inverted in units of one frame period as shown in FIGS. Therefore, the horizontal polarity pattern of the data voltage simultaneously output from the data driving circuit 473 is controlled to be different in units of one horizontal period. For example, as shown in FIGS. 43A and 43B, the data voltage output simultaneously from the data driving circuit 473 has an even frame (Even frame) with an odd frame (Odd Frame) and a horizontal 2-dot inversion method (H2) polarity. Frame) can have a horizontal one-dot inversion method (H1) polarity. Further, as shown in FIGS. 44A to 45B, the data voltage simultaneously output from the data driving circuit 473 has the polarity of the horizontal 1-dot inversion method (H1) in the odd frame and the horizontal 2-dot inversion in the even frame. It can have the polarity of the system (H2).

  In response to the gate start pulse (GSP) from the timing controller 471, the horizontal dot inversion logic circuit 477 generates an H2 / H1 inversion signal (DINV) whose logic is inverted every time the gate start pulse (GSP) is input. Occur. Since the gate start pulse (GSP) is generated once at the same time as the start of the frame during one frame period, the logic of the H2 / H1 inversion signal (DINV) is a unit of one frame period as shown in FIGS. Is inverted.

  The POL logic circuit 472 can be incorporated in the timing controller 471.

  48 and 49 show a liquid crystal display device according to the tenth embodiment of the present invention.

  48, the liquid crystal display device according to the tenth embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 471, a POL logic circuit 482, a data driving circuit 483, and a gate driving circuit 474. In this embodiment, the system 475 including the line memory 476, the liquid crystal display panel 100, the timing controller 471, and the gate driving circuit 474 are substantially the same as those in the ninth embodiment, and therefore, the same reference numerals are assigned to the same. Detailed description is omitted.

  The POL logic circuit 482 receives a gate start pulse (GSP), a source output enable signal (SOE), and a reference polarity control signal (POL) and receives polarity control signals (POLa to POLd) for preventing afterimage and flicker. Output sequentially or selectively output the same reference polarity control signal (POL) every frame. Further, the POL logic circuit 482 outputs an H2 / H1 inversion signal (DINV) for controlling a cycle in which the polarity of the data voltage is inverted in the horizontal direction.

  The data driving circuit 483 latches the digital video data (RGBodd, RGBevne) under the control of the timing controller 471, and responds to the polarity control signal (POL / POLa to POLd) from the POL logic circuit 482. Then, the analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. In response to the polarity control signals (POL / POLa to POLd) from the POL logic circuit 482, the data driving circuit 473 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods. Further, the data driving circuit 473 responds to the H2 / H1 inversion signal (DINV) from the POL logic circuit 482, inverts the polarity of the data voltage supplied to the adjacent data line, or the data in units of two data lines. Invert the polarity of the voltage.

  FIG. 49 is a circuit diagram showing the POL logic circuit 482 in detail.

Referring to FIG. 49, the POL logic circuit 482 includes a frame counter 491, a line counter 492, a POL generation circuit 493, and a multiflexor 494.

  In response to the gate start pulse (GSP), the frame counter 491 outputs 2-beat frame count information (Fcnt) indicating the number of frames of an image displayed on the liquid crystal display panel 100. In response to the source output enable signal (SOE), the line counter 492 outputs 2-beat line count information (Lcnt) indicating a horizontal line displayed on the liquid crystal display panel 100.

  The POL generation circuit 493 uses the frame count information (Fcnt) to generate a 1-beat H2 / H1 inversion signal (DINV) whose logic is inverted in units of one frame period, and uses a circuit as shown in FIG. The polarity control signals (POLa to POLd) are sequentially generated.

  FIG. 50 shows the data driving circuit (473, 483) shown in FIGS. 47 and 49 in detail.

  Referring to FIG. 50, the data driving circuit (473, 483) includes a plurality of data integrated circuits (ICs). Each data integrated circuit drives k (k is an integer smaller than m) data lines (D1 to Dk). For this purpose, each of the data integrated circuits includes a shift register 501, a data register 502, a first latch 503, a second latch 504, a digital / analog converter (hereinafter referred to as “DAC”) 505, a charge share circuit (Charge Share Circuit). 506 and an output circuit 507.

  The shift register 501 generates a sampling signal by shifting the source start pulse (SSP) from the timing controller 471 by the source sampling clock (SSC). The shift register 501 shifts the source start pulse (SSP) and transmits a carry signal (CAR) to the shift register 501 of the next integrated circuit. The data register 502 temporarily stores the odd digital video data (RGBodd) and the even digital video data (RGBeven) separated by the timing controller 471, and supplies the stored data (RGBodd, RGBeven) to the first latch 503. The first latch 503 samples the digital video data (RGBeven, RGBodd) from the data register 502 in response to a sampling signal sequentially input from the shift register 501 and outputs the data (RGBeven, RGBodd) as one horizontal line. After latching one by one, data of one horizontal line is output simultaneously. The second latch 504 latches data for one horizontal line input from the first latch 503 and then latches simultaneously with the second latch 504 of another integrated circuit during the low logic period of the source output enable signal (SOE). Output the digital video data.

  The DAC 505 includes a circuit as shown in FIG. The DAC 505 converts the digital video data from the second latch 504 into positive gamma compensation voltage (GH) or negative gamma compensation in accordance with the polarity control signal (POL / POLa to POLd) and the H2 / H1 inverted signal (DINV). Analog positive polarity / negative polarity data voltage is output by converting with voltage (GL).

  The charge share circuit 506 shorts adjacent data output channels during the high logic period of the source output enable signal (SOE), and outputs an average value of adjacent data voltages to the charge share voltage, or source output. A common voltage (Vcom) is supplied to the data output channel during the high logic period of the enable signal (SOE) to reduce a rapid change in the positive data voltage and the negative data voltage.

  The output circuit 507 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

FIG. 51 shows a first embodiment of the DAC 505 shown in FIG.
The DAC 505 in FIG. 51 outputs a data voltage with the polarity pattern shown in FIGS. 43A and 43B.

  Referring to FIG. 51, the DAC 505 includes a P-decoder (PDEC) 121 to which a positive gamma compensation voltage (GH) is supplied, an N-decoder (NDEC) 122 to which a negative gamma compensation voltage (GL) is supplied, and polarity. Responding to the control signal (POL / POLa to POLd) in response to the multi-flexers (123a to 123d) for selecting the output of the P-decoder 121 and the output of the N-decoder 122 and the H2 / H1 inverted signal (DINV) The horizontal output inversion circuit 510 for inverting the logic of the selection control signal supplied to the control terminal of the multiflexor 493 is included. Since the P-decoder 121 and the N-decoder (NDEC) 122 are substantially the same as those shown in FIG. 12, the same reference numerals are assigned and detailed descriptions thereof are omitted.

  The fourth i + 1 multiflexor 123a responds to the polarity control signal (POL / POLa to POLd) input to its non-inverted control terminal, and has a positive gamma compensation voltage and a negative gamma compensation voltage in units of one horizontal period. Are alternately selected and the selected positive / negative gamma compensation voltage is output as an analog data voltage. In response to the polarity control signal (POL / POLa to POLd) input to its inversion control terminal, the 4i + 2 multiflexor 123b generates a positive gamma compensation voltage and a negative gamma compensation voltage in units of one horizontal period. Alternately selected and selected positive / negative gamma compensation voltage is output as analog data voltage.

  In response to the output of the horizontal output inverting circuit 510 input to its non-inverting control terminal, the fourth i + 3 multiflexor 123c alternately switches the positive gamma compensation voltage and the negative gamma compensation voltage in units of one horizontal period. The selected positive / negative gamma compensation voltage is output to the analog data voltage. The fourth i + 4 multiflexor 123d alternately selects the positive gamma compensation voltage and the negative gamma compensation voltage in units of one horizontal period in response to the output of the horizontal output inversion circuit 510 input to its own inversion control terminal. The selected positive / negative gamma compensation voltage is output as an analog data voltage. In response to the H2 / H1 inversion signal (DINV), the horizontal output inversion circuit 510 changes the polarity of the data voltage supplied to the data line to the horizontal 1-dot inversion system (H1) or the horizontal 2-dot inversion system (H2). The 4i + 3 and the 4i + 4 multiflexers (123c, 173d) are controlled so that the data voltage is output in step (b).

  The horizontal output inverting circuit 510 includes switch elements (S1, S2) and an inverter 511. The horizontal output inversion circuit 510 controls the logical value of the selection control signal supplied to the control terminals of the 4i + 3 multiflexor 123c and the 4i + 4 multiflexor 123d in response to the H2 / H1 inversion signal (DINV). The input terminal of the first switch element (S1) is connected to the polarity control signal supply terminal 181 and the output terminal of the first switch element (S1) is inverted / non-inverted of the 4i + 3 and 4i + 4 multiflexors (123c, 123d). Connected to the inversion control terminal. The inversion control terminal of the first switch element (S1) is connected to the H2 / H1 inversion signal supply terminal. The input terminal of the second switch element (S2) is connected to the polarity control signal supply terminal, and the output terminal of the second switch element (S2) is connected to the inverter 521. The non-inverting control terminal of the second switch element (S2) is connected to the H2 / H1 inverted signal supply terminal. The inverter 511 is connected to the output terminal of the second switch element (S2) and the inverting / non-inverting control terminal of the 4i + 3 or 4i + 4 multiflexor (123c, 123d).

  When the H2 / H1 inversion signal (DINV) is high logic, the second switch element (S2) is turned on and the first switch element (S1) is turned off. Then, the inverted polarity control signal (POL / POLa to POLd) is input to the non-inverting control terminal of the 4i + 3 multiflexor 123c, and the inverted polarity control is input to the inverting control terminal of the 4i + 4 multiflexor 123d. Signals (POL / POLa to POLd) are input.

  When the H2 / H1 inversion signal (DINV) is low logic, the first switch element (S1) is turned on and the second switch element (S2) is turned off. The polarity control signal (POL) is input as it is to the non-inversion control terminal of the 4i + 3 multiflexor 123c, and the polarity control signal (POL) is input as it is to the inversion control terminal of the 4i + 4 multiflexor 123d. .

  Therefore, when the H2 / H1 inversion signal (DINV) and the polarity control signals (POL / POLa to POLd) are generated as shown in FIG. 53, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is as shown in FIG. 43A and 43B, “− + + −” during the 4i + 1 frame period, “− + − +” during the 4i + 2 frame period, and “+ − − +” during the 4i + 3 frame period, It is controlled to “+ − + −” during the 4i + 4th frame period.

  FIG. 52 shows a second embodiment of the DAC 505 shown in FIG. The DAC 505 in FIG. 52 outputs a data voltage with the polarity patterns shown in FIGS. 44A to 45B.

  Referring to FIG. 52, the DAC 505 includes a P-decoder (PDEC) 121, an N-decoder (NDEC) 122, multi-flexors [123 a to 123 d], and a horizontal output inversion circuit 520.

  The fourth i + 3 multiflexor 123c responds to a polarity control signal (POL / POLa to POLd) input to its non-inverted control terminal, and has a positive gamma compensation voltage and a negative polarity in units of one horizontal period or two horizontal periods. Are alternately selected, and the selected positive / negative gamma compensation voltage is output as an analog data voltage. The 4i + 4 multiflexor 123d responds to the polarity control signal (POL / POLa to POLd) input to its own inversion control terminal in response to a positive gamma compensation voltage and a negative polarity in units of one horizontal period or two horizontal periods. By alternately selecting the gamma compensation voltage, the selected positive / negative gamma compensation voltage is output to the analog data voltage.

  The fourth i + 1 multiflexor 123a responds to the output of the horizontal output inversion circuit 520 input to its non-inversion control terminal in response to a positive gamma compensation voltage and a negative gamma compensation in units of one horizontal period or two horizontal periods. The voltage is alternately selected, and the selected positive / negative gamma compensation voltage is output to the analog data voltage. The 4i + 2 multiflexor 123b responds to the output of the horizontal output inversion circuit 520 input to its own inversion control terminal, and has a positive gamma compensation voltage and a negative gamma compensation voltage in units of one horizontal period or two horizontal periods. Are alternately selected, and the selected positive / negative gamma compensation voltage is output to the analog data voltage. In response to the H2 / H1 inversion signal (DINV), the horizontal output inversion circuit 520 changes the polarity of the data voltage supplied to the data line to the horizontal 1-dot inversion system (H1) or the horizontal 2-dot inversion system (H2). The 4i + 1 and 4i + 2 multiflexors (123a, 123b) are controlled so that the data voltage is output in step (b).

  The horizontal output inverting circuit 520 includes switch elements (S1, S2) and an inverter 521. The horizontal output inversion circuit 520 controls the logical value of the selection control signal supplied to the control terminals of the 4i + 1 multiflexor 123a and the 4i + 2 multiflexor 123b in response to the H2 / H1 inversion signal (DINV). The input terminal of the first switch element (S1) is connected to the polarity control signal supply terminal, and the output terminal of the first switch element (S1) is inverted / non-inverted of the 4i + 1 and 4i + 2 multiflexors (123a, 123b). Connected to the control terminal. The inversion control terminal of the first switch element (S1) is connected to the H2 / H1 inversion signal supply terminal. The input terminal of the second switch element (S2) is connected to the polarity control signal supply terminal 181 and the output terminal of the second switch element (S2) is connected to the inverter 521. The non-inverting control terminal of the second switch element (S2) is connected to the H2 / H1 inverted signal supply terminal. The inverter 521 is connected to the output terminal of the second switch element (S2) and the inversion / non-inversion control terminal of the 4i + 1 or 4i + 2 multiflexor (123a, 123b).

  When the H2 / H1 inversion signal (DINV) is high logic, the second switch element (S2) is turned on and the first switch element (S1) is turned off. Then, the inverted polarity control signal (POL / POLa to POLd) is input to the non-inversion control terminal of the 4i + 1 multiflexor 123a, and the inverted polarity control is input to the inversion control terminal of the 4i + 2 multiflexor 123b. Signals (POL / POLa to POLd) are input. When the H2 / H1 inversion signal (DINV) is low logic, the first switch element (S1) is turned on and the second switch element (S2) is turned off. Then, the polarity control signal (POL / POLa to POLd) is inputted as it is to the non-inverting control terminal of the 4i + 1 multiflexor 123a, and the polarity control signal (POL / POLa) is inputted to the inverting control terminal of the 4i + 2 multiflexor 123b. -POLd) are input as they are. Therefore, as shown in FIG. 54 or 55, when the H2 / H1 inversion signal (DINV) and the polarity control signals (POL / POLa to POLd) are generated, the horizontal polarity of the data supplied to the 4i + 1 to 4i + 4 data lines. As shown in FIGS. 44A to 45B, the pattern is “+ − + −” during the 4i + 1 frame period, “− + + −” during the 4i + 2 frame period, and “− + − during the 4i + 3 frame period. “+” Becomes “+ −− +” for the 4i + 4th frame period.

  FIG. 56 is a flowchart for explaining a driving method of the liquid crystal display device according to the eleventh embodiment of the present invention.

  Referring to FIG. 56, the driving method of the liquid crystal display device according to the eleventh embodiment of the present invention analyzes input data, and a DC afterimage can appear as the input data is interlaced data or scroll data. Determine whether the data. (S561, S562)

  If it is determined in step S562 that the currently input data is data that can generate a DC afterimage, the present invention sequentially applies the first to fourth polarity control signals (POLa to POLd) in units of frame periods. The data driving frequency of the first liquid crystal cell group is controlled to be lower than the data driving frequency of the second liquid crystal cell group within two frame periods. Further, the present invention generates an H2 / H1 inversion signal (DINV) whose logic is inverted every frame period so that the horizontal polarity pattern of the data voltage output from the data driving circuit is different for each frame period. Control.

  If it is determined in step S562 that the currently input data is data in which no DC afterimage appears, the present invention generates a reference polarity control signal (POL) in every frame period and generates an H2 / H1 inverted signal. (DINV) is generated with a low logic to control the data driving frequency of all the liquid crystal cells to be the same. (S564)

  FIG. 57 shows a liquid crystal display device according to an eleventh embodiment of the present invention.

  Referring to FIG. 57, the liquid crystal display according to the eleventh embodiment of the present invention includes a system 475, a liquid crystal display panel 100, a video analysis circuit 571, a timing controller 471, a POL logic circuit 572, a data driving circuit 573, and a gate driving. A circuit 474 is provided. In this embodiment, the system 475, the liquid crystal display panel 100, the timing controller 471, and the gate driving circuit 474 are substantially the same as those of the above-described embodiment, and therefore, the same reference numerals are assigned and detailed descriptions thereof are omitted.

  The video analysis circuit 571 determines whether the digital video data of the currently input video can generate a DC afterimage. The video analysis circuit 571 compares the data between adjacent lines in one frame video, and if the data between the lines is larger than a predetermined threshold value, it determines the currently input data from interlaced data. Also, the video analysis circuit 571 compares the data of each pixel in frame units, detects the moving image and the moving speed of the image in the display image, and when the moving image moves at a preset speed, the moving image is displayed. The included frame data is determined from the scroll data. As a result of such video analysis, the video analysis circuit 571 generates a selection signal (SEL2) indicating interlace data or scroll data, and controls the POL logic circuit 572 using the selection signal (SEL2).

  In response to the selection signal (SEL2) from the video analysis circuit 571, the POL logic circuit 572 sequentially generates the first to fourth polarity control signals (POLa to POLd) during the 4i + 1 to 4i + 4 frame periods. , The logic of the H2 / H1 inversion signal (DINV) is inverted in units of one frame period. In response to the selection signal (SEL2), the POL logic circuit 572 transmits the reference polarity control signal (POL) to the data driving circuit 473 as it is when data other than the interlace data and scroll data is input, and the H2 / The logic of the H1 inversion signal (DINV) is maintained at low logic.

  The data driving circuit 573 latches digital video data (RGBodd, RGBeven) under the control of the timing controller 471, and responds to the polarity control signals (POL / POLa to POLd) from the POL logic circuit 182. Then, the analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 573 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signals (POL / POLa to POLd) from the POL logic circuit 572. The data driving circuit 573 responds to the H2 / H1 inversion signal (DINV) from the POL logic circuit 572 to change the polarity of the data voltage to the horizontal 1-dot inversion system (H1) and the horizontal 2-dot inversion system (H2). Control alternately.

  The video analysis circuit 571 and the POL logic circuit 572 can be incorporated in the timing controller 471.

  As described above, the liquid crystal display devices and the driving methods thereof according to the ninth to eleventh embodiments of the present invention reduce the driving frequency of the data voltage supplied to the first liquid crystal cell group of the liquid crystal display panel within two frame periods. In order to prevent DC afterimages and control the drive frequency of the data voltage supplied to the second liquid crystal cell group to be high to prevent flicker and improve display quality, the first liquid crystal cell group and the first liquid crystal cell group The display quality is improved by reducing the size of each of the two liquid crystal cell groups.

  Through the above description, those skilled in the art can make various changes and modifications without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but is determined by the claims.

Claims (9)

A liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied;
A first polarity control signal and a second polarity control signal that is different from the first polarity control signal are generated, and a third polarity control signal that is opposite in phase to the first polarity control signal, and the second polarity control signal A logic circuit for generating a fourth polarity control signal having an opposite phase and generating a horizontal output inversion signal whose logic is inverted in units of one frame period;
In response to the first to fourth polarity control signals, the polarity of the data voltage supplied to the data line is shifted in the column direction of the liquid crystal cell in units of one frame period, and the horizontal output inverted signal is generated. In response, a data driving circuit for shifting the polarity of the data voltage along the horizontal direction of the liquid crystal display panel in units of one frame period;
A gate driving circuit for supplying the scan pulse to the gate line;
The data driving circuit selects one of a positive data voltage and a negative data voltage in response to any one of the first to fourth polarity control signals input to each control terminal. A multiplexer of
A liquid crystal display device comprising: a plurality of horizontal output inversion circuits for inverting polarity control signals applied to some control terminals of the plurality of multiplexers in response to the horizontal output inversion signal. The first to fourth polarity control signals are:
2. The liquid crystal display device according to claim 1, wherein the logic is inverted every two horizontal periods. During the Nth frame period, the liquid crystal cells arranged in the 4j (i is an integer of 0 or more) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 2 vertical lines have positive polarity. A data voltage is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the 4i + 3 and 4i + 4 vertical lines, and in the 4i + 1 and 4i + 2 vertical lines. The negative polarity data voltage is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines, and the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 3 and 4i + 4 vertical lines. Is supplied with a positive data voltage,
During the (N + 1) th frame period, the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the 4i + 2 and 4i + 3 vertical lines are supplied with the positive data voltage, and the 4i + 1 and 4i + 4th. The liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the vertical line are supplied with the negative data voltage, and arranged in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 2 and 4i + 3 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 1 and fourth i + 4 vertical lines. Is supplied
During the (N + 2) th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the 4i + 3 and 4i + 4 vertical lines, and the 4i + 1 and 4i + 2 are supplied. The negative data voltage is supplied to the liquid crystal cells arranged on the 4j + 1 and 4j + 2 horizontal lines in the vertical line, and arranged on the 4j + 3 and 4j + 4 horizontal lines in the 4i + 3 and 4i + 4 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 1 and fourth i + 2 vertical lines. Supplied,
During the (N + 3) th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 4 vertical lines, and the 4i + 2 and 4i + 3 (4i + 2). The liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the vertical line are supplied with the negative data voltage, and arranged in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 1 and 4i + 4 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is applied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 2 and fourth i + 3 vertical lines. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is supplied. The liquid crystal cell is
A first liquid crystal cell group to which a voltage having the same polarity is continuously supplied for two frame periods;
A second liquid crystal cell group to which a voltage of the first polarity and a voltage of the second polarity are continuously supplied during the two frame periods;
The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged along the horizontal direction and the vertical direction in each of the frame periods,
4. The liquid crystal display device according to claim 3, wherein the position of the first liquid crystal cell group and the position of the second liquid crystal cell group change from each other in units of one frame period. During the Nth frame period, the liquid crystal cells arranged in the 4j (j is an integer of 0 or more) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 4 vertical lines have positive polarity. Is supplied to the liquid crystal cells disposed in the 4j + 1 and 4j + 2 horizontal lines of the 4i + 2 and 4i + 3 vertical lines, and the 4i + 1 and 4i + 4 vertical lines are supplied with a negative data voltage. The negative data voltage is supplied to the liquid crystal cells arranged on the 4j + 3 and 4j + 4 horizontal lines, and the 4j + 3 and 4j + 4 horizontal lines are arranged on the 4j + 3 and 4j + 4 horizontal lines. The liquid crystal cell is supplied with the positive data voltage,
During the (N + 1) th frame period, the positive data voltage is supplied to the liquid crystal cells disposed in the 4j + 1 and 4j + 4 horizontal lines in the 4i + 3 and 4i + 4 vertical lines, and the 4i + 1 and 4i + 2 are supplied. The liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the vertical line are supplied with the negative data voltage, and arranged in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 3 and 4i + 4 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 1 and fourth i + 2 vertical lines. Is supplied
During the (N + 2) th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the (4j + 1) th and (4j + 4) horizontal lines in the (4i + 2) th and (4i + 3) th vertical lines, so that the (4i + 1) th and (4i + 4th) th 4th. The liquid crystal cells arranged in the 4j + 1 and 4j + 4 horizontal lines in the vertical line are supplied with the negative data voltage, and arranged in the 4j + 2 and 4j + 3 horizontal lines in the 4i + 2 and 4i + 3 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 horizontal lines in the fourth i + 1 and fourth i + 4 vertical lines. Is supplied
During the (N + 3) th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the (4j + 1) th and (4j + 2) horizontal lines in the (4i + 1) th and (4i + 2) vertical lines, so that the (4i + 3) th and (4i + 4) th 4th. The liquid crystal cells arranged on the 4j + 1 and 4j + 2 horizontal lines on the vertical line are supplied with the negative data voltage, and arranged on the 4j + 3 and 4j + 4 horizontal lines on the 4i + 1 and 4i + 2 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 3 and fourth i + 4 vertical lines. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is supplied. The liquid crystal cell is
A first liquid crystal cell group to which a voltage having the same polarity is continuously supplied between two frame periods;
Including a second liquid crystal cell group in which a voltage having a first polarity and a voltage having a second polarity are continuously supplied between the two frame periods;
Between the Nth frame period and the N + 2 frame period, a first liquid crystal cell group includes liquid crystal cells arranged in the 4i + 1 and 4i + 3 columns, and the second liquid crystal cell group includes the 4i + 2 and 4i + 4 columns. Including a liquid crystal cell arranged in
The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the horizontal direction and the vertical direction between the N + 1 frame period and the N + 3 frame period, respectively. The liquid crystal display device according to claim 5. A liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines to which data voltages are supplied and a plurality of gate lines to which scan pulses are supplied;
A polarity control signal whose logic is periodically inverted, and a control circuit which generates a horizontal output inversion signal for shifting the polarity of the data voltage along the horizontal direction of the liquid crystal display panel in units of one frame period;
In response to the polarity control signal, the polarity of the data voltage is inverted in units of one horizontal period or two horizontal periods, and in response to the horizontal output inversion signal, it is shifted in the horizontal direction and supplied to the data line. A data driving circuit to
A gate driving circuit for supplying the scan pulse to the gate line;
A plurality of multiplexers for selecting one of a positive data voltage and a negative data voltage in response to any one of the polarity control signals input to each control terminal;
A liquid crystal display device comprising: a plurality of horizontal output inversion circuits for inverting polarity control signals applied to some control terminals of the plurality of multiplexers in response to the horizontal output inversion signal. During the Nth frame period, a positive data voltage is supplied to the liquid crystal cells arranged in the odd horizontal lines of the 4i (i is a positive integer) +1 vertical line and the 4i + 4 vertical line, and the 4i + 2 vertical line is supplied. A negative data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines in the 4i + 3 vertical line and the liquid crystal cells arranged on the even horizontal lines in the 4i + 1 vertical line and the 4i + 4 vertical line. The negative data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines in the 4i + 2 vertical line and the 4i + 3 vertical line.
During the (N + 1) th frame period, the positive data voltage is supplied to the liquid crystal cells disposed on the odd horizontal lines of the 4i + 1 vertical line and the 4i + 2 vertical line, and the 4i + 3 vertical line and the 4th i + 3 vertical line The negative polarity data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines with 4i + 4 vertical lines, and the liquid crystal cells arranged on the even horizontal lines with the 4i + 1 vertical lines and the 4i + 2 vertical lines are supplied to the liquid crystal cells. The negative data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines in the 4i + 3 vertical line and the 4i + 4 vertical line,
During the (N + 2) th frame period, the negative data voltage is supplied to the liquid crystal cells disposed on the odd horizontal lines in the 4i + 1 vertical line and the 4i + 4 vertical line, and the 4i + 2 vertical line and the 4th (+ i) vertical line. The positive data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines with 4i + 3 vertical lines, and the liquid crystal cells arranged on the even horizontal lines with the 4i + 1 vertical lines and the 4i + 4 vertical lines are supplied to the liquid crystal cells arranged on the odd horizontal lines. The positive data voltage is supplied, and the negative data voltage is supplied to the liquid crystal cells arranged in the even horizontal lines of the 4i + 2 vertical line and the 4i + 3 vertical line.
During the (N + 3) th frame period, the negative data voltage is supplied to the liquid crystal cells disposed on the odd horizontal lines in the 4i + 1 vertical line and the 4i + 2 vertical line.
The positive data voltage is supplied to the liquid crystal cells disposed on the odd horizontal lines in the 4i + 3 vertical line and the 4i + 4 vertical line, and the even horizontal lines in the 4i + 1 vertical line and the 4i + 2 vertical line. The liquid crystal cells arranged in the line are supplied with the positive data voltage, and the liquid crystal cells arranged in the even horizontal lines of the 4i + 3 vertical line and the 4i + 4 vertical line have the negative data voltage. The liquid crystal display device according to claim 7, wherein the liquid crystal display device is supplied. During the Nth frame period, positive polarity data is supplied to the liquid crystal cells arranged in the 4j (j is a positive integer) +1 and 4j + 2 horizontal lines in the 4i (i is a positive integer) +1 and 4i + 4 vertical lines. A voltage is supplied to the liquid crystal cells disposed in the 4j + 1 and 4j + 2 horizontal lines at the 4i + 2 and 4i + 3 vertical lines, and a negative data voltage is supplied to the liquid crystal cells arranged at the 4i + 1 and 4i + 4 vertical lines. The negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines, and the liquid crystal cells arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 2 and 4i + 3 vertical lines. The positive data voltage is supplied,
During the (N + 1) th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the 4i + 1 and 4i + 2 vertical lines, and the 4i + 3 and 4i + 4 verticals are supplied. The negative polarity data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines in the line, and arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 2 vertical lines. The negative data voltage is supplied to the liquid crystal cell, and the positive data voltage is supplied to the liquid crystal cells arranged on the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 3 and fourth i + 4 vertical lines. ,
During the (N + 2) th frame period, the negative data voltage is supplied to the liquid crystal cells arranged in the (4j + 1) th and (4j + 2) horizontal lines in the (4i + 1) th and (4i + 4) vertical lines, and the (4i + 2) th and (4i + 3) th vertical lines are supplied. The liquid crystal cells arranged on the 4j + 1 and 4j + 2 horizontal lines are supplied with the positive data voltage, and arranged on the 4j + 3 and 4j + 4 horizontal lines on the 4i + 1 and 4i + 4 vertical lines. The positive polarity data voltage is supplied to the liquid crystal cell, and the negative polarity data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 2 and fourth i + 3 vertical lines. ,
During the (N + 3) th frame period, the negative data voltage is supplied to the liquid crystal cells disposed in the (4j + 1) th and (4j + 2) horizontal lines in the (4i + 1) th and (4i + 2) vertical lines, so that the (4i + 3) th and (4i + 4) th vertical lines are supplied. The liquid crystal cells arranged in the 4j + 1 and 4j + 2 horizontal lines are supplied with the positive data voltage, and arranged in the 4j + 3 and 4j + 4 horizontal lines in the 4i + 1 and 4i + 2 vertical lines. The positive polarity data voltage is supplied to the liquid crystal cell, and the negative polarity data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 horizontal lines in the fourth i + 3 and fourth i + 4 vertical lines. The liquid crystal display device according to claim 7.