KR100874641B1 - LCD and its driving method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for improving display quality by preventing direct current afterimage and flicker.

The liquid crystal display includes: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And a controller for generating the polarity control signal differently in units of frame periods, wherein the liquid crystal display panel includes first and second liquid crystal cell groups having different data driving frequencies within two frame periods. The second liquid crystal cell group alternates in the vertical and horizontal directions, and the positions of the second liquid crystal cell are changed in units of one frame period.

Description

Liquid Crystal Display and Driving Method

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

5 is a view for explaining a method of driving a liquid crystal display device according to an embodiment of the present invention;

6 is a waveform diagram showing an effect of preventing direct current afterimage caused by the first liquid crystal cell group shown in FIG. 5.

7A through 10B are diagrams illustrating polar patterns of a data voltage according to various embodiments of the present disclosure.

FIG. 11 is a waveform diagram illustrating an AC value and a DC offset value of a data voltage measured in a liquid crystal display panel to which data voltages as shown in FIGS. 7A to 10B are supplied.

FIG. 12 is a waveform diagram illustrating an optical waveform measured in a liquid crystal display panel to which data voltages as shown in FIGS. 7A to 10B are supplied.

13 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 14 is a block diagram showing details of the POL logic circuit shown in FIG. 13; FIG.

FIG. 15 is a block diagram showing in detail the POL generation circuit shown in FIG. 14; FIG.

16 is a block diagram illustrating a liquid crystal display according to a second embodiment of the present invention.

FIG. 17 is a block diagram illustrating in detail the POL logic circuit shown in FIG. 16; FIG.

18 is a block diagram showing in detail the POL generation circuit shown in FIG.

19 is a block diagram showing in detail the data driving circuit shown in FIG.

20 is a circuit diagram showing in detail the first embodiment of the digital-to-analog converter shown in FIG.

FIG. 21 is a circuit diagram showing details of a first embodiment of the digital-to-analog converter shown in FIG. 19; FIG.

FIG. 22 is a waveform diagram showing a polarity control signal and a horizontal output inversion signal for obtaining the polarity pattern of the data voltage shown in FIGS. 7A and 7B;

FIG. 23 is a waveform diagram showing a polarity control signal and a horizontal output inversion signal for obtaining the polarity pattern of the data voltage shown in FIGS. 8A and 8B.

24 is a waveform diagram showing a polarity control signal and a horizontal output inversion signal for obtaining a polarity pattern of the data voltage shown in FIGS. 9A and 9B.

FIG. 25 is a waveform diagram showing a polarity control signal and a horizontal output inversion signal for obtaining the polarity pattern of the data voltage shown in FIGS. 10A and 10B.

26 is a flowchart for explaining a method of driving a liquid crystal display according to another exemplary embodiment of the present invention.

27 is a block diagram illustrating a liquid crystal display according to a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101: timing controller

102, 132, 202: POL logic circuit 103, 133, 183: data driving circuit

104: gate driving circuit 105: system

106: line memory 111: frame counter

112: line counter 161: shift register

162: data register 163, 164: latch

165: digital-to-analog converter 166: charge share circuit

167: output circuit 171: P-decoder

172: N-decoder 180, 190: horizontal output inverting circuit

201: image analysis circuit S1, S2: switch element

113, 121, 122, 143, 151, 152: POL generating circuit

114, 135, 134, 155, 173a ~ 173d: Multiplexer

123, 124, 153, 154, 174, 194: inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality by preventing direct current afterimage and flicker.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining the data voltage charged in the liquid crystal cell Clc, “D1” denotes a data line to which a data voltage is supplied, and “G1”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One example of such an example is when interlace data voltages are supplied to a liquid crystal display. The interlaced data (hereinafter referred to as "interlace data") includes only the odd line data voltages to be displayed on the liquid crystal cells of the odd horizontal lines in the odd frame period, and is displayed on the liquid crystal cells of the even horizontal lines in the even frame period. Only the data voltage to be included is included.

2 is a waveform diagram illustrating an example of interlace data supplied to a liquid crystal cell Clc. It is assumed that the liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is any one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, a high positive data voltage is supplied only to the liquid crystal cell Clc arranged in the odd horizontal line during the odd frame period. For this reason, like the waveform in the box during the four frame periods, the positive data voltage becomes dominant compared to the negative data voltage, resulting in a direct current afterimage. Figure 3 is an image showing the experimental results of the DC afterimage resulting from the interlace data. When the original image as shown in the left image of FIG. 3 is supplied to the liquid crystal display panel in an interlace manner for a predetermined time, the amplitude of the data voltage whose polarity changes in units of frame periods varies in the odd frame and the even frame. As a result, when a data voltage of 127 gray levels is supplied to all the liquid crystal cells Clc of the liquid crystal display panel after the original image as shown in the left image, the pattern of the original image appears faint as shown in the right image. DC afterimages appear.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, the voltage of the same polarity is repeatedly generated in the liquid crystal cell Clc according to the correlation between the size of the scrolled picture and the scroll speed (moving speed). Accumulation may cause a DC afterimage. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC image persistence that appears when moving the diagonal pattern and the character pattern at a constant speed.

In a liquid crystal display device, not only the display quality of a moving image is deteriorated by the afterimage of DC, but also the display quality is deteriorated by a flicker phenomenon in which the luminance difference is periodically observed by the naked eye. Therefore, in order to improve the display quality of the liquid crystal display device, the flicker phenomenon must be prevented along with the DC residual image.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, the present invention devised to solve the problems of the prior art to improve display quality by preventing direct current afterimage and flicker.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And a controller for generating the polarity control signal differently in units of frame periods, wherein the liquid crystal display panel includes first and second liquid crystal cell groups having different data driving frequencies within two frame periods. The second liquid crystal cell group alternates in the vertical and horizontal directions, and the positions of the second liquid crystal cell are changed in units of one frame period.
The controller controls a polarity of data voltages charged in the horizontally adjacent liquid crystal cells by supplying a horizontal output inversion signal whose logic is inverted in units of one frame period to the data driving circuit.
The horizontal output inversion signal controls the polarity of the data voltages charged in the horizontally neighboring liquid crystal cells for one frame period in a horizontal one dot inversion manner, and then applies the horizontally neighboring liquid crystal cells for the next frame period. The polarity of the data voltages to be charged is controlled by a horizontal two dot inversion method.

Each of the first and second liquid crystal cell groups has a size within 2 × 2 liquid crystal cells.

The data driving frequency of the first liquid crystal cell group is lower than the data driving frequency of the second liquid crystal cell group.

The horizontal output inversion signal inverts logic in units of one frame period, thereby inverting polarities of some data voltages among data voltages output from the data driving circuit.

The data driving circuit includes a plurality of first decoders for converting digital video data into a positive gamma compensation voltage; A plurality of second decoders for converting the digital video data into a negative gamma compensation voltage; A plurality of multiplexers for alternately selecting outputs of the first decoder and the second decoder in response to the polarity control signal; And a horizontal output inverting circuit connected to control terminals of some of the multiplexers and inverting the control signal supplied to the control terminals in units of one frame period in response to the horizontal output inversion signal.

The polarity control signal is generated in a fourth i + 1 frame period and the logic is inverted in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in one horizontal period period; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines in the 4i + 2 and 4i + 3 horizontal lines. And liquid crystal cells Clc arranged in 4i + 3 and 4i + 4 vertical lines in the 4i + 1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group is formed in the vertical and horizontal directions. 1 liquid crystal cell group interposed therebetween, and during the 4i + 2 frame period, the first liquid crystal cell group is disposed on the 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 3 horizontal lines Liquid crystal cells and liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines in the fourth i + 1 and fourth i + 4 horizontal lines, wherein the second liquid crystal cell group is vertical and horizontal directions. The first liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween, and the first liquid crystal cell group is perpendicular to the fourth i + 1 and fourth i + 2 horizontal lines in the fourth i + 2 and fourth i + 3 horizontal lines during the fourth i + 3 frame period. The liquid crystal cells arranged in a line And liquid crystal cells arranged in the fourth i + 3 and fourth i + 4 vertical lines in the fourth i + 1 and fourth i + 4 horizontal lines, and the second liquid crystal cell group includes a first liquid crystal cell group in the vertical and horizontal directions. The first liquid crystal cell group is disposed on the fourth i + 3 and fourth i + 4 vertical lines in the fourth i + 2 and fourth i + 3 horizontal lines during the fourth i + 4 frame period. Cells and liquid crystal cells arranged in the fourth i + 1 and fourth i + 2 vertical lines in the fourth i + 1 and fourth i + 4 horizontal lines, wherein the second liquid crystal cell group is formed in the vertical and horizontal directions. 1 liquid crystal cell group is interposed.

The polarity control signal is generated in a fourth i + 1 frame period and the logic is inverted in one horizontal period period; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in two horizontal period periods; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. During the 4i + 1 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i + 1 and A liquid crystal cell disposed in a fourth i + 1 and a fourth i + 2 vertical line in a fourth i + 4 horizontal line, wherein the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; During the 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines on the fourth i + 2 and fourth i + 3 horizontal lines, and the fourth i + Liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines in the first and fourth horizontal lines, and the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 3 horizontal lines. 4i + 1 and the fourth 4i + 4 horizontal lines including liquid crystal cells arranged in the fourth i + 1 and fourth i + 2 vertical lines, wherein the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i +. Liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines in the first and fourth horizontal lines, and the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. do.

The polarity control signal is generated in a fourth i + 1 frame period and the logic is inverted in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in the two horizontal period periods and having a phase difference by one horizontal period relative to the first polarity control signal; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. During the 4i + 1 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines on the 4i + 1 and 4i + 3 horizontal lines, and the 4i + 2 and A liquid crystal cell disposed in a fourth i + 3 and a fourth i + 4 vertical line in a fourth i + 4 horizontal line, wherein the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; During a 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines on the fourth i + 1 and fourth i + 3 horizontal lines, and the fourth i + And liquid crystal cells disposed on the fourth and fourth i + 1 vertical lines in the second and fourth horizontal lines, respectively, wherein the second liquid crystal cell group includes the first liquid crystal cell group in the vertical and horizontal directions. The first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines in the fourth i + 1 and fourth i + 3 horizontal lines during the fourth i + 3 frame period. , remind 4i + 2 and 4i + 4 horizontal lines including liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines, wherein the second liquid crystal cell group includes the first liquid crystal cell group in the vertical and horizontal directions. The first liquid crystal cell group is disposed between the fourth i + 3 and the fourth i + 4 vertical lines in the fourth i + 1 and fourth i + 3 horizontal lines during the fourth i + 4 frame period. And liquid crystal cells arranged in the fourth i + 1 and fourth i + 2 vertical lines in the fourth i + 2 and fourth i + 4 horizontal lines, and the second liquid crystal cell group includes the liquid crystal cells in the vertical and horizontal directions. The first liquid crystal cell group is disposed therebetween.

The polarity control signal is generated during a fourth i + 1 frame period and a fourth i + 2 frame period, and a first polarity control signal whose logic is inverted in two horizontal period periods; And a second polarity control signal generated during the fourth i + 3 frame period and the fourth i + 4 frame period, the logic being inverted in the second horizontal period, and generated out of phase with respect to the first polarity control signal. During the fourth i + 1 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on vertical lines 4i + 3 and 4i + 4, and the second liquid crystal cell group is vertically divided into 4i + 1 and 4i + 2 vertical lines. The liquid crystal cells arranged in a line, and during the fourth i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the fourth i + 1 and fourth i + 2 vertical lines, and the second liquid crystal cell group Includes liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines, and during the fourth i + 3 frame period, the first liquid crystal cell group is disposed on the fourth i + 3 and fourth i + 4 vertical lines. Liquid crystal cells, wherein the second liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines, and during the fourth i + 4 frame period, the first liquid crystal cell group includes the fourth i The liquid crystal cells may be arranged in the +1 and 4i + 2 vertical lines, and the second liquid crystal cell group may include the liquid crystal cells in the fourth i + 3 and 4i + 4 vertical lines.

The controller may include: a frame counter for counting gate start pulses to generate frame count information indicating a frame number; A line counter for counting a source output enable signal to generate line count information indicating the number of horizontal lines of the liquid crystal display panel; A polarity control signal generation circuit configured to generate different polarity control signals in frame period units based on the frame count information and the line count information; And a multiplexer for selecting the polarity control signals in response to the frame count information.

The liquid crystal display device is connected between the polarity control signal generation circuit and the multiplexer to invert the first polarity control signal generated from the polarity control signal generation circuit for a fourth i + 1 frame period to generate a fourth polarity control signal for a fourth i + 3 frame period. A first inverter for generating three polarity control signals; And a fourth polarity control signal connected to the polarity control signal generation circuit and the multiplexer to invert a second polarity control signal generated from the polarity control signal generation circuit for a fourth i + 2 frame period to invert the second polarity control signal for a fourth i + 4 frame period. It further comprises a second inverter for generating a.

The liquid crystal display device is connected between the polarity control signal generation circuit and the multiplexer to invert a first polarity control signal generated from the polarity control signal generation circuit during a 4i + 1 frame period and a 4i + 2 frame period. And an inverter for generating a second polarity control signal during a 4i + 3 frame period and a 4i + 4 frame period.

The liquid crystal display further includes an image analysis circuit for analyzing the digital video data of the input image and controlling the polarity control signal and the horizontal output inversion signal generated from the controller according to the analysis result.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes supplying the data voltages to the data lines in response to a polarity control signal; Supplying the scan pulse to the gate lines; And generating the polarity control signal differently in units of frame periods, wherein the liquid crystal display panel includes first and second liquid crystal cell groups having different data driving frequencies within two frame periods. The second liquid crystal cell groups alternate in the vertical and horizontal directions and change positions of each other in units of one frame period.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 27.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention varies the driving frequency of the first liquid crystal cell group and the second liquid crystal cell group within two frame periods. The first liquid crystal cell group is driven at a low driving frequency in order to prevent direct current afterimage. In contrast, the second liquid crystal cell group is driven at a relatively high driving frequency to prevent flicker that may be caused by the first liquid crystal cell group. The change in the polar pattern of the data voltage charged in the first liquid crystal cell group corresponds to the driving frequency of the first liquid crystal cell group, and the change in the polar pattern of the data voltage charged in the second liquid crystal cell group corresponds to the driving frequency of the second liquid crystal cell group.

Referring to FIG. 5, in the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, in order to drive the first liquid crystal cell group at a frequency 1/2 lower than that of the second liquid crystal cell group within two frame periods, a unit of two frame periods is used. In addition, the polarity of the data voltages charged in the liquid crystal cell is reversed, and the polarity inversion periods of the data voltages supplied to the liquid crystal cells in the horizontal direction are controlled to be offset from each other. The first liquid crystal cell group and the second liquid crystal cell group are alternately arranged in the vertical direction and the horizontal direction. The positions of the first liquid crystal cell group and the second liquid crystal cell group change each other every one frame period.

The prevention effect of DC afterimage due to the first liquid crystal cell group will be described with reference to FIG. 6.

Referring to FIG. 6, a high data voltage is supplied to an arbitrary liquid crystal cell Clc included in the first liquid crystal cell group during a odd frame period, and a relatively low data voltage is supplied during an even frame period, and the data voltages are two frames. The polarity changes over a period of time. Then, the positive data voltages supplied to the liquid crystal cells Clc of the first liquid crystal cell group and the liquid crystal cells of the first liquid crystal cell group during the third and fourth frame periods as waveforms in the box during the first and second frame periods. The negative data voltages supplied to Clc are neutralized so that voltages of polarities deflected in the liquid crystal cell Clc are not accumulated. Therefore, in the liquid crystal display device of the present invention, the DC residual image does not appear even in the data voltage, for example, the data voltage of the interlaced image, to which the first liquid crystal cell group is applied the high voltage having the predominant polarity in either the odd frame or the even frame.

Although the first liquid crystal cell group can prevent a DC afterimage, flicker may occur because data voltages having the same polarity are supplied to the liquid crystal cell Clc every two frame periods. The polarities of the data voltages charged in the second liquid crystal cell group are inverted in one frame period in which flicker is hardly felt by the naked eye. The driving frequency of the display screen visually felt by this second liquid crystal cell group is recognized as the fast driving frequency of the second liquid crystal cell group.

7A through 10B illustrate various embodiments of polar patterns of data voltages supplied to the first and second liquid crystal cell groups.

First embodiment

7A and 7B, during the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group is formed on the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on the fourth and fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6, respectively, and include the fourth and fourth horizontal lines L1, L4, and L5. ) Includes liquid crystal cells Clc disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions, and the fourth liquid crystal cell group 4i + 3 and 4i + in the fourth and fourth horizontal lines L2, L3, L6, and L7. 4 liquid crystal cells Clc disposed on the vertical lines C3, C4, C7, and C8, and include the fourth i + 1 and the fourth in the fourth and fourth horizontal lines L1, L4, and L5. Liquid crystal cells Clc disposed on 4i + 2 vertical lines C1, C2, C5, and C6. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the neighboring second liquid crystal cell group charge the data voltages of the same polarity. To this end, the polarity of the first polarity control signal POLa generated during the fourth i + 1 frame period is inverted in units of two horizontal periods corresponding to the two horizontal synchronization signals. The data driving circuit supplies two data channels adjacent to each other in response to the first polarity control signal POLa to supply data voltages having the same polarity to two liquid crystal cells horizontally neighboring during the fourth i + 1 frame period. Outputs data voltages of the same polarity and inverts the polarities of the data voltages in units of two output channels. In addition, the data driving circuit inverts the polarities of the data voltages in units of two horizontal periods in response to the first polarity control signal POLa in order to invert the polarities of the data voltages in units of two horizontal periods during the fourth i + 1 frame period. . During the fourth i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

During the 4i + 2 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 vertical lines C3, C4, and 4th in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C7 and C8, and include the fourth and fourth i + 1 and fourth and fourth i + 2 vertical lines C1 and 4i in the fourth and fourth horizontal lines L1, L4, and L5. Liquid crystal cells Clc disposed on C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. To this end, the polarity of the second polarity control signal POLb generated during the fourth i + 2 frame period is inverted in units of one horizontal period. The data driving circuits are arranged in the output channel adjacent to each other in response to the second polarity control signal POLb to invert the polarities of the data voltages in units of one liquid crystal cell in each of the vertical and horizontal directions during the fourth i + 2 frame period. Data voltages having different polarities are output and the polarities of the data voltages are reversed in units of one horizontal period. During the fourth i + 2 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) methods.

During the 4i + 3 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i + 2 vertical lines C1, C2, and 4th in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C5 and C6, and include the 4i + 3 and 4i + 4 vertical lines C3, in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. And liquid crystal cells Clc disposed at C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages of the same polarity. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 3 frame period are opposite to the polarities of the data voltages generated during the fourth i + 1 frame period. To this end, the polarity of the third polarity control signal POLc generated during the fourth i + 3 frame period is inverted in units of two horizontal periods, and the phase is inverted with respect to the first polarity control signal POLa. The data driving circuit supplies two data channels adjacent to each other in response to the third polarity control signal POLc in order to supply data voltages having the same polarity to two liquid crystal cells horizontally neighboring during the fourth i + 3 frame period. Outputs data voltages of the same polarity and inverts the polarities of the data voltages in units of two output channels. In addition, the data driving circuit inverts the polarities of the data voltages in units of two horizontal periods in response to the third polarity control signal POLc in order to invert the polarities of the data voltages in units of two horizontal periods during the fourth i + 3 frame period. Let's do it. During the fourth i + 3 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

During the 4i + 4 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 vertical lines C3, C4, and 4i + 2 in the 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C7 and C8, and include the fourth and fourth i + 1 and fourth and fourth i + 2 vertical lines C1 and 4i in the fourth and fourth horizontal lines L1, L4, and L5. Liquid crystal cells Clc disposed on C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 4 frame period are opposite to the polarities of the data voltages generated during the fourth i + 2 frame period. To this end, the polarity of the fourth polarity control signal POLd generated during the fourth i + 4 frame periods is inverted in units of one horizontal period and the phase is inverted with respect to the second polarity control signal POLb. In order to invert the polarity of the data voltages in units of one liquid crystal cell in each of the vertical and horizontal directions during the fourth i + 4 frame period, the data driving circuits are connected to each other in neighboring output channels in response to the fourth polarity control signal POLd. Data voltages having different polarities are output and the polarities of the data voltages are reversed in units of one horizontal period. During the fourth i + 4 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) methods.

Second embodiment

8A and 8B, during the 4i + 1 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. +4 and liquid crystal cells Clc disposed on vertical lines C3, C4, C7, and C8, and 4i + 1 in 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. And liquid crystal cells Clc disposed on the fourth i + 2 vertical lines C1, C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. To this end, the polarity of the first polarity control signal POLa generated during the fourth i + 1 frame period is inverted in units of one horizontal period. The data driving circuits are connected to each other in neighboring output channels in response to the first polarity control signal POLa in order to invert the polarity of the data voltage in units of one liquid crystal cell in each of the vertical and horizontal directions during the fourth i + 1 frame period. Data voltages having different polarities are output and the polarities of the data voltages are reversed in units of one horizontal period. During the fourth i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

During the 4i + 2 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i + 2 vertical lines C1, C2, and 4th in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C5 and C6, and include the 4i + 3 and 4i + 4 vertical lines C3, in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. And liquid crystal cells Clc disposed at C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the neighboring second liquid crystal cell group charge the data voltages of the same polarity. To this end, the polarity of the second polarity control signal POLb generated during the fourth i + 2 frame period is inverted in units of two horizontal periods. The data driving circuit may apply the same voltage through two neighboring output channels in response to the second polarity control signal POLb to supply data voltages having the same polarity to two liquid crystal cells horizontally neighboring during the fourth i + 2 frame period. Outputs data voltages of polarity and inverts the polarities of data voltages in units of two output channels. In addition, the data driving circuit inverts the polarities of the data voltages in units of two horizontal periods in response to the second polarity control signal POLb to invert the polarities of the data voltages in units of two horizontal periods during the fourth i + 2 frame period. . During the fourth i + 2 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

During the 4i + 3 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 vertical lines C3, C4, and 4th in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C7 and C8, and include the fourth and fourth i + 1 and fourth and fourth i + 2 vertical lines C1 and 4i in the fourth and fourth horizontal lines L1, L4, and L5. Liquid crystal cells Clc disposed on C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 3 frame period are opposite to the polarities of the data voltages generated during the fourth i + 1 frame period. To this end, the polarity of the third polarity control signal POLc generated during the fourth i + 3 frame periods is generated by logic inverted in units of one horizontal period and inverted with respect to the first polarity control signal POLa. The data driving circuits are connected to each other in neighboring output channels in response to the third polarity control signal POLc to invert the polarities of the data voltages in units of one liquid crystal cell in each of the vertical and horizontal directions during the fourth i + 3 frame period. Data voltages having different polarities are output and the polarities of the data voltages are reversed in units of one horizontal period. During the fourth i + 3 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) methods.

During the 4i + 4 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i + 2 vertical lines C1, C2, and 4th in the 4i + 2 and 4i + 3 horizontal lines L2, L3, L6, and L7. Liquid crystal cells Clc disposed on C5 and C6, and include the 4i + 3 and 4i + 4 vertical lines C3, in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. And liquid crystal cells Clc disposed at C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8 in the fourth i + 2 and fourth i + 3 horizontal lines L2, L3, L6, and L7. Cells Clc and are disposed in the 4i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the 4i + 1 and 4i + 4 horizontal lines L1, L4, and L5. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 2 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 2 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the neighboring second liquid crystal cell group charge the data voltages of the same polarity. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 4 frame period are opposite to the polarities of the data voltages generated during the fourth i + 2 frame period. To this end, the fourth polarity control signal POLd generated during the fourth i + 4 frame period is generated with logic inverted in units of two horizontal periods and inverted with respect to the second polarity control signal POLb. The data driving circuit supplies two data channels adjacent to each other in response to the fourth polarity control signal POLd to supply data voltages having the same polarity to two horizontally neighboring liquid crystal cells during the fourth i + 4 frame period. Outputs data voltages of the same polarity and inverts the polarities of the data voltages in units of two output channels. In addition, the data driving circuit inverts the polarities of the data voltages in units of two horizontal periods in response to the fourth polarity control signal POLd to invert the polarities of the data voltages in units of two horizontal periods during the fourth i + 4 frame period. . During the fourth i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

Third embodiment

9A and 9B, during the 4i + 1 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i in the 4i + 1 and 4i + 3 horizontal lines L1, L3, L5, and L7. +2 and liquid crystal cells Clc disposed on vertical lines C1, C2, C5, and C6, and include 4i + 3 and 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. The liquid crystal cells Clc are disposed on the fourth i + 4 vertical lines C3, C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8 in the fourth i + 1 and fourth i + 3 horizontal lines L1, L3, L5, and L7. Cells Clc and are disposed in 4i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 1 liquid crystal cells adjacent to each other in the horizontal direction. Polarities of neighboring liquid crystal cells in the 2 × 1 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. To this end, the polarity of the first polarity control signal POLa generated during the fourth i + 1 frame period is inverted in units of two horizontal periods. The data driving circuit supplies the data voltages having different polarities to the liquid crystal cells horizontally neighboring during the fourth i + 1 frame period and inverts the polarities of the data voltages in units of two horizontal periods. In response, the polarities of the data voltages are reversed. During the fourth i + 1 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 2 dot inversion (V2D) methods.

During the 4i + 2 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 vertical lines C3, C4, and 4i + 1 and 4i + 3 horizontal lines L1, L3, L5, and L7. Liquid crystal cells Clc disposed on C7 and C8, and include 4i + 1 and 4i + 2 vertical lines C1, in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Liquid crystal cells Clc disposed on C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 1 and fourth i + 3 horizontal lines L1, L3, L5, and L7. Cells Clc, and include the 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Arranged liquid crystal cells (Clc). Each of the first and second liquid crystal cell groups is disposed in units of 2 × 1 liquid crystal cells adjacent to each other in the horizontal direction. Polarities of data voltages charged in neighboring liquid crystal cells in the 2 × 1 liquid crystal cells are opposite to each other. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. To this end, the polarity of the second polarity control signal POLb generated during the fourth i + 2 frame period is inverted in units of two horizontal periods and is generated with a phase difference of one horizontal period relative to the first polarity control signal POLa. . The data driving circuit supplies the data voltages having different polarities to the liquid crystal cells horizontally adjacent to each other during the 4i + 2 frame period and inverts the polarity of the data voltage in units of 2 horizontal periods. In response, the polarities of the data voltages are reversed. During the fourth i + 2 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

During the 4i + 3 frame period, the first liquid crystal cell group includes the 4i + 1 and 4i + 2 vertical lines C1, C2, and 4th in the 4i + 1 and 4i + 3 horizontal lines L1, L3, L5, and L7. Liquid crystal cells Clc disposed on C5 and C6, and include 4i + 3 and 4i + 4 vertical lines C3, in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. And liquid crystal cells Clc disposed at C4, C7, and C8. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell group includes liquid crystals disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8 in the fourth i + 1 and fourth i + 3 horizontal lines L1, L3, L5, and L7. Cells Clc and are disposed in 4i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 1 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 1 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 3 frame period are opposite to the polarities of the data voltages generated during the fourth i + 1 frame period. To this end, the third polarity control signal POLc generated during the fourth i + 3 frame period is generated with logic inverted in units of two horizontal periods and inverted with respect to the first polarity control signal POLa. The data driving circuit supplies two data channels adjacent to each other in response to the third polarity control signal POLc in order to supply data voltages having the same polarity to two liquid crystal cells horizontally neighboring during the fourth i + 3 frame period. Outputs data voltages of the same polarity and inverts the polarities of the data voltages in units of two output channels. In addition, the data driving circuit supplies a data voltage having different polarities to the liquid crystal cells horizontally neighboring during the fourth i + 2 frame period and inverts the polarity of the data voltage in units of two horizontal periods. In response to POLc), the polarities of the data voltages are reversed. During the fourth i + 3 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 2 dot inversion (V2D) methods.

During the 4i + 4 frame period, the first liquid crystal cell group includes the 4i + 3 and 4i + 4 vertical lines C3, C4, and 4th in the 4i + 1 and 4i + 3 horizontal lines L1, L3, L5, and L7. Liquid crystal cells Clc disposed on C7 and C8, and include 4i + 1 and 4i + 2 vertical lines C1, in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Liquid crystal cells Clc disposed on C2, C5, and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed in the vertical and horizontal directions. The second liquid crystal cell is a liquid crystal disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the fourth i + 1 and fourth i + 3 horizontal lines L1, L3, L5, and L7. Cells Clc and are disposed on 4i + 3 and 4i + 4 vertical lines C3, C4, C7, and C8 in the 4i + 2 and 4i + 4 horizontal lines L2, L4, and L6. Liquid crystal cells Clc. Each of the first and second liquid crystal cell groups is disposed in units of 2 × 1 liquid crystal cells neighboring each other in the vertical and horizontal directions. Polarities of neighboring liquid crystal cells in the 2 × 1 liquid crystal cells are opposite. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group adjacent thereto charge the data voltages having different polarities. The polarities of the data voltages supplied to each of the liquid crystal cells of the first and second liquid crystal cell groups during the fourth i + 4 frame period are opposite to the polarities of the data voltages generated during the fourth i + 2 frame period. To this end, the fourth polarity control signal POLd generated during the fourth i + 4 frame period is generated with logic inverted in units of two horizontal periods and inverted with respect to the second polarity control signal POLb. The data driving circuit supplies the data voltages having different polarities to the liquid crystal cells horizontally neighboring the fourth i + 4 frame periods and inverts the polarities of the data voltages in units of two horizontal periods. In response, the polarities of the data voltages are reversed. During the fourth i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical two dot inversion (V2D) method.

Fourth embodiment

10A and 10B, during the fourth i + 1 frame period, the first liquid crystal cell group includes liquid crystal cells Clc disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8. ). The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween. The second liquid crystal cell group includes liquid crystal cells Clc disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6. Polarities of the data voltages charged in the liquid crystal cells of the first and second liquid crystal cell groups are reversed at intervals of one dot (or one liquid crystal cell) in the vertical and horizontal directions. To this end, the polarity of the second polarity control signal POL2a generated during the fourth i + 1 frame period is inverted in units of one horizontal period. The data driving circuit supplies the data voltages having different polarities to the liquid crystal cells horizontally adjacent to each other during the fourth i + 1 frame period and inverts the polarity of the data voltage in units of one horizontal period. In response, the polarities of the data voltages are reversed. During the fourth i + 1 frame period, the first and second liquid crystal cell groups are driven in a horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) system.

During the fourth i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells Clc disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5 and C6. The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween. The second liquid crystal cell group includes liquid crystal cells Clc arranged on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8. Two liquid crystal cells horizontally adjacent to each other at the boundary of the first and second liquid crystal cell groups are supplied with data voltages of the same polarity, and other liquid crystal cells are spaced one dot (or one liquid crystal cell) in the horizontal and vertical directions. Is reversed. To this end, the polarity of the second polarity control signal POL2a generated during the fourth i + 2 frame period is inverted in units of one horizontal period. The second a polarity control signal POL2a generated during the fourth i + 2 frame period has the same phase as the polarity control signal generated during the fourth i + 1 frame period. The data driving circuit inverts the polarities of the data voltages in response to the second polarity control signal POL2a during the fourth i + 2 frame period. During the fourth i + 2 frame period, the first and second liquid crystal cell groups are driven in the horizontal two dot inversion (H2D) and vertical one dot inversion (V1D) methods.

The polarity pattern of the data voltage supplied in the fourth i + 3 frame period is opposite to the polarity pattern of the fourth i + 1 frame period. During the fourth i + 3 frame period, the first liquid crystal cell group includes the liquid crystal cells Clc disposed on the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7, and C8 in the same manner as the fourth i + 1 frame period. ). The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween. The second liquid crystal cell group includes liquid crystal cells Clc disposed on the fourth i + 1 and fourth i + 2 vertical lines C1, C2, C5, and C6 in the same manner as the fourth i + 1 frame period. Polarities of the data voltages charged in the liquid crystal cells of the first and second liquid crystal cell groups are inverted at intervals of one dot in the vertical and horizontal directions. To this end, the second-b polarity control signal POL2b generated during the fourth i + 3 frame period is inverted in one horizontal period and is generated in the reverse phase of the second-a polarity control signal POL2a. The data driving circuit inverts the polarities of the data voltages in response to the second b polarity control signal POL2b. During the fourth i + 3 frame period, the first and second liquid crystal cell groups are driven in the horizontal 1 dot inversion (H1D) and vertical 1 dot inversion (V1D) methods.

The polar pattern of the data voltage supplied in the fourth i + 4 frame period is opposite to the polar pattern of the fourth i + 2 frame period. During the 4i + 4 frame period, the first liquid crystal cell group includes the liquid crystal cells Clc arranged in the fourth i + 1 and 4i + 2 vertical lines C1, C2, C5, and C6 in the same manner as the 4i + 2 frame period. ). The second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween. The second liquid crystal cell group includes liquid crystal cells Clc arranged in the fourth i + 3 and fourth i + 4 vertical lines C3, C4, C7 and C8, similarly to the fourth i + 2 frame period. Two liquid crystal cells horizontally adjacent to each other at the boundary of the first and second liquid crystal cell groups are supplied with data voltages of the same polarity, and other liquid crystal cells are spaced one dot (or one liquid crystal cell) in the horizontal and vertical directions. Is reversed. To this end, the polarity of the second b polarity control signal POL2b generated during the fourth i + 4 frame periods is inverted in units of one horizontal period. The second b polarity control signal POL2b generated during the fourth i + 4 frame period has the same phase as the polarity control signal generated during the fourth i + 3 frame period. The data driving circuit inverts the polarities of the data voltages in response to the second b polarity control signal POL2b for the fourth i + 4 frame periods. During the fourth i + 4 frame period, the first and second liquid crystal cell groups are driven in a horizontal two dot inversion (H2D) and a vertical one dot inversion (V1D) system.

Since the liquid crystal cells Clc of the first liquid crystal cell group have a relatively long polarity change period, they may make flicker visible when spatially concentrated. Accordingly, in the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the liquid crystal cells Clc of the first liquid crystal cell group include only two liquid crystal cells in the horizontal direction as shown in FIGS. 7A to 10B. .

Since the liquid crystal cells Clc of the first liquid crystal cell group have a relatively long polarity change period, when their positions are the same for three or more frame periods, wave noise may be caused by causing a luminance difference with other horizontal lines. Accordingly, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention controls the first liquid crystal cell group to the second liquid crystal cell group and the second liquid crystal cell group to the first liquid crystal cell group as shown in FIGS. 7A to 9B.

FIG. 11 illustrates an experimental result of supplying a data voltage of 127 gray levels to a liquid crystal display panel in the same polar pattern as FIGS. 7A to 10B and measuring a voltage waveform of the liquid crystal display panel. In this experiment, the liquid crystal display panel is driven at a frequency of 60 Hz due to the second liquid crystal cell group. If all of the liquid crystal cells of the liquid crystal display panel are driven by the liquid crystal cells of the first liquid crystal cell group, the driving frequency is lowered to the 30 Hz frequency, resulting in 30 Hz flicker. The AC voltage value AC of the data voltage, that is, the amplitude was 30.35 mV, and the DC offset value DC between the center of the AC voltage and the ground voltage GND was measured to be 1.389V. In addition, as a result of measuring the optical waveform by installing an optical sensor on the specimen liquid crystal display panel in this experiment, the optical waveform of the liquid crystal display panel was also measured at 60 Hz due to the second liquid crystal cell group as shown in FIG. 12. This is because the optical waveform measured in the liquid crystal display panel is determined by the light conversion period of the second liquid crystal cell group in which the driving frequency is faster than the first liquid crystal cell in which the driving frequency is slow in two frame periods.

13 to 15 illustrate a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 13, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a POL logic circuit 102, a data driving circuit 103, and a gate driving circuit. 104 is provided.

In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The m data lines D1 to Dm and the n gate lines G1 to Gn cross the lower glass substrate of the liquid crystal display panel 100. The liquid crystal display panel 100 includes m × n liquid crystal cells Clc arranged in a matrix form by the cross structure of the data lines D1 to Dm and the n gate lines G1 to Gn. As described above, the liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group driven at different data voltage frequencies. The lower glass substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. Polarizing plates having optical axes orthogonal to each other are attached to the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 100 in contact with the liquid crystal.

The timing controller 101 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable, clock signal (CLK), and the like. And control signals for controlling the operation timing of the POL logic circuit 102. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). It includes a source sampling clock (SSC), a source output enable signal (SOE), and a reference polarity control signal (POL). The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit and is a timing control signal for sequentially shifting the gate start pulse GSP, and is generated with a pulse width corresponding to the ON period of the TFT. The gate output enable signal GOE indicates the output of the gate driving circuit 104. The source start pulse SSP indicates a start pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs the latching operation of data in the data driving circuit 103 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. The reference polarity control signal Polar (POL) indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The reference polarity control signal POL is generated as either a polarity control signal of one dot inversion in which logic is inverted in one horizontal period or a polarity control signal of two dot inversion in which logic is inverted in two horizontal periods.

In addition, the timing controller 101 separates the input digital video data RGB into the odd pixel data RGBodd and the even pixel data RGBeven in order to lower the transmission frequency of the digital video data, and the data RGBodd and RGBeven. Is supplied to the data driving circuit 103 through the six data buses.

The POL logic circuit 102 receives a gate start pulse GSP, a source output enable signal SOE, and a reference polarity control signal POL, and polarity control signals POLa to POLd (preventing afterimage and flicker). POL2a and POL2b)) are sequentially output or optionally, the same reference polarity control signal POL is output every frame.

The data driving circuit 103 latches the digital video data RGBodd and RGBeven under the control of the timing controller 101, and polarizes the digital video data from the POL logic circuit 102 to the polarity control signals POL / POLa to POLd (POL2a). , POL2b)) to convert the analog positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and supply the data voltage to the data lines D1 to Dm. The data driving circuit 103 controls the polarity of the data voltage in the vertical direction in response to the polarity control signals POL / POLa to POLd (POL2a and POL2b). In addition, in the case of using a data driving integrated circuit including the H1D / H2D switching option pin 103a, the data driving circuit 103 connects the H1D / H2D switching option pin 103a to the power supply voltage source Vcc to supply the data voltage. The horizontal polarity can be switched between the horizontal two dot inversion method and the horizontal two dot inversion method by one frame period. That is, when the H1D / H2D switching option pin 103a is connected to the power supply voltage source Vcc, the polarity of the data voltage is inverted (H2D) in units of two liquid crystal cells horizontally neighboring during the odd frame period (or even frame period). During the even frame period (or odd frame period), the polarity is inverted (H1D) in units of one liquid crystal cell in the horizontal direction.

The gate driving circuit 104 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. Comprised of a plurality of gate drive integrated circuit including a sequentially output scan pulses having a pulse width of approximately one horizontal period.

The POL logic circuit 102 may be embedded in the timing controller 101.

The liquid crystal display according to the first embodiment of the present invention further includes a system 105 for supplying digital video data RGB and timing signals Vsync, Hsync, DE, and CLK to the timing controller 101.

The system 105 extracts video data from a broadcast signal or an image source input from an external device, including a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and converts the video data into digital. Supply to timing controller 101. The interlace broadcast signal received by the system 106 is stored in the line memory and then output. The video data of the interlace broadcast signal exists only in the odd line in the odd frame period and only in the even line in the even frame period. Accordingly, when the system 105 receives the interlace broadcast signal, the system 105 generates even line data of the odd frame period and odd line line data of the even frame as an average value or black data value of valid data stored in the line memory 106. The system 105 supplies timing signals Vsync, Hsync, DE, CLK and power to the timing controller 101 together with the digital video data.

14 and 15 are circuit diagrams showing the POL logic circuit 102 in detail.

14 and 15, the POL logic circuit 102 includes a frame counter 111, a line counter 112, a POL generating circuit 113, and a multiplexer 114.

The frame counter 111 is a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 in response to the gate start pulse GSP, which is generated once during one frame period and coincided with the start of one frame period. Outputs information Fcnt. The frame count information Fcnt is generated as 2-bit information so that each of the four frame periods can be identified when it is assumed that the polarity pattern of the data voltage is repeated in four frame period periods as shown in FIGS. 7A to 10B.

The line counter 112 displays line count information Lcnt indicating a horizontal line to be displayed on the liquid crystal display panel 100 in response to a source output enable signal SOE indicating a time point at which data voltages are supplied to each horizontal line. Outputs The line count information Fcnt is two-bit information because the polarity of the data voltage displayed on the liquid crystal display panel 100 is inverted in one or two horizontal line periods as shown in the polarity pattern of the data voltage as shown in FIGS. 7A to 10B. Is caused by.

As a timing signal supplied to the frame counter 111 and the line counter 112, a clock generated from the internal oscillator of the timing controller 101 may be used. However, since the clock has a high frequency, the timing controller 101 and the POL logic circuit may be used. It is possible to increase electromagnetic interference (EMI) between the 102. According to the present invention, the timing of the operation of the frame counter 111 and the line counter 112 may be controlled by the gate start pulse GSP and the source output enable signal SOE having a smaller frequency than the clock generated by the internal oscillator of the timing controller 101. The increase in EMI between the timing controller 101 and the POL logic circuit 102 can be minimized by using the signal.

The POL generating circuit 113 includes a first POL generating circuit 121, a second POL generating circuit 122, first and second inverters 123 and 124, and a multiplexer 125 as shown in FIG. 15. The first to fourth polarity control signals POLa to POLd are sequentially generated.

The first POL generating circuit 121 generates the first polarity control signals POLa, POLa, and POLa shown in FIGS. 7A to 10B. The first embodiment of the first POL generation circuit 121 generates the first polarity control signal POLa in which logics H and L are inverted in units of two horizontal periods based on the line counter information Lcnt. The first polarity control signal POLa generated in this first embodiment includes the polarity control signal POLa shown in Figs. 7A and 7B, 9A and 9B. The second embodiment of the first POL generation circuit 121 generates the first polarity control signal POLa in which logics H and L are inverted in units of one horizontal period based on the line counter information Lcnt. The first polarity control signal POLa generated in this second embodiment includes the polarity control signals POLa and POL2a shown in Figs. 8A and 8B, 10A and 10B. The first inverter 123 inverts the first polarity control signal POLa to generate a third polarity control signal POLc generated as an inverse phase of the first polarity control signal POLa. Accordingly, the logic inversion period of the third polarity control signal POLc is determined according to the logic inversion period of the first polarity control signal POLa output from the first POL generation circuit 121 and is illustrated in FIGS. 7A to 9B. A third polarity control signal POLc, POLc, and POLc, or a second polarity control signal POL2b shown in FIGS. 10A and 10B.

The second POL generation circuit 122 generates the second polarity control signals POLb, POLb, and POLb shown in FIGS. 7A to 9B. The first embodiment of the second POL generation circuit 122 generates a second polarity control signal POLb in which logics H and L are inverted in units of one horizontal period based on the line counter information Lcnt. The second polarity control signal POLb generated in this first embodiment includes the second polarity control signal POLb shown in Figs. 7A and 7B. The second embodiment of the second POL generation circuit 122 generates a second polarity control signal POLb in which logics H and L are inverted in units of two horizontal periods based on the line counter information Lcnt. The second polarity control signal POLb generated in this second embodiment includes the second polarity control signals POLb and POLb shown in Figs. 8A and 8B, 9A and 9B. The second inverter 124 inverts the second polarity control signal POLb to generate the fourth polarity control signal POLd which is generated in the inverse phase of the second polarity control signal POLb. Accordingly, the logic inversion period of the fourth polarity control signal POLd is determined according to the logic inversion period of the second polarity control signal POLb output from the second POL generation circuit 122 and is illustrated in FIGS. 7A to 9B. One of the fourth polarity control signals POLc, POLc, and POLc is included. In the case of the polarity control signal for controlling the polarity pattern as shown in FIGS. 10A and 10B, the second POL generation circuit 122 and the inverter 124 connected to the output terminal thereof are not necessary.

The multiplexer 125 outputs the first polarity control signal POLa during the fourth i + 1 frame period in response to the two-bit frame count information Fcnt, and then outputs the second polarity control signal during the fourth i + 2 frame period. After outputting POLb, the third polarity control signal POLc is output during the fourth i + 3 frame period. The multiplexer 145 outputs the fourth polarity control signal POLd during the fourth i + 4 frame period.

One of the first to fourth polarity control signals POLa to POLd output from the POL generation circuit 113 and the reference polarity control signal POL generated by the internal circuit of the timing controller 101 are illustrated in FIG. It is selected by the multiplexer 114 as shown in 13. The multiplexer 114 selects the polarity control signals POLa to POLd and POL to be supplied to the data driving circuit 103 according to the logic value of the control terminal connected to the POL selection option pin. The POL selection option pin may be connected to the control terminal of the multiplexer 114 and may be selectively connected to the ground voltage GND or the power supply voltage Vcc by the manufacturer or the user. For example, when the POL selection option pin is connected to the base voltage GND and the control terminal of the multiplexer 114, the multiplexer 114 is supplied with a selection control signal SEL of "0" to its control terminal so that the reference polarity control signal is provided. (POL) is output, and when the POL selection option pin is connected to the control voltage of the power supply voltage Vcc and the multiplexer 114, the multiplexer 114 supplies a selection control signal SEL of '1' to its control terminal. To output polarity control signals POLa to POLd from the POL generating circuit 113. The selection control signal SEL of the multiplexer 114 may be replaced with a selection control signal automatically generated from the system 105 or the timing controller 101 according to a user selection signal input through a user interface or an analysis result of data. have.

16 to 20 show a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 16, the liquid crystal display according to the second exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a POL logic circuit 132, a data driving circuit 133, and a gate driving circuit. 104 is provided. In the second embodiment, the liquid crystal display panel 100, the timing controller 101, and the gate driving circuit 104 are substantially the same as the first embodiment described above, and the same reference numerals are used to omit the detailed description thereof. Shall be.

The POL logic circuit 132 receives the gate start pulse GSP, the source output enable signal SOE, and the reference polarity control signal POL, and polarity control signals POLa to POLd (preventing afterimage and flicker). Or POL2a and POL2b)) sequentially or selectively output the same reference polarity control signal POL every frame. In addition, the POL logic circuit 132 outputs a horizontal output inversion signal HINV for controlling a period in which the polarities of the data voltages are inverted in the horizontal direction.

The data driving circuit 133 latches the digital video data RGBodd and RGBevne under the control of the timing controller 101 and transmits the digital video data to the polarity control signals POL / POLa to POLd from the POL logic circuit 132. In response, an analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 103 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signals POL / POLa to POLd (POL2a and POL2b) from the POL logic circuit 132. In addition, the data driving circuit 103 inverts the polarities of the data voltages to be supplied to the neighboring data lines in response to the horizontal output inversion signal HINV from the POL logic circuit 132, or in units of two data lines. Reverse the polarity of the data voltages.

17 and 18 are circuit diagrams illustrating the POL logic circuit 132 in detail.

17 and 18, the POL logic circuit 132 includes a frame counter 141, a line counter 142, a POL generation circuit 143, and a multiplexer 144.

The frame counter 141 is a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 in response to the gate start pulse GSP, which is generated once during one frame period and coincided with the start of one frame period. Outputs information Fcnt. The frame count information Fcnt is generated as 2-bit information so that each of the four frame periods can be identified when it is assumed that the polarity pattern of the data voltage is repeated in four frame period periods as shown in FIGS. 7A to 9B.

The line counter 142 is line count information Lcnt indicating a horizontal line to be displayed on the liquid crystal display panel 100 in response to a source output enable signal SOE indicating a time point at which data voltages are supplied to each horizontal line. Outputs The line count information Fcnt is two-bit information because the polarity of the data voltage displayed on the liquid crystal display panel 100 is inverted in one or two horizontal line periods as shown in the polarity pattern of the data voltage as shown in FIGS. 7A to 10B. Is caused by.

The POL generation circuit 143 generates a 1-bit horizontal output inversion signal HINV whose logic is inverted in units of one frame period by using the frame count information Fcnt, and the first POL generation circuit 151 as shown in FIG. And sequentially generating polarity control signals POLa to POLd (or POL2a and POL2b), including the second POL generating circuit 152, the first and second inverters 153 and 154, and the multiplexer 155. . In the horizontal output inversion signal HINV, the logic is inverted in units of one frame period so that the polarities of the data voltages charged in horizontally adjacent liquid crystal cells as shown in FIGS. Or the horizontal two dot inversion method) and the horizontal two dot inversion method (or the horizontal one dot inversion method) in the even frame period. The horizontal 1 dot inversion method H1dot supplies voltages of different polarities to liquid crystal cells that are horizontally neighboring within one horizontal period. The horizontal two dot inversion method (H2dot) inverts the polarities of the data voltages in a period of two adjacent liquid crystal cells within one horizontal period.

The first POL generation circuit 151 generates the first polarity control signals POLa, POLa, and POLa shown in FIGS. 7A to 9B or the second polarity control signal POL2a shown in FIGS. 10A and 10B. The first embodiment of the first POL generation circuit 151 generates the first polarity control signal POLa in which logics H and L are inverted in units of two horizontal periods based on the line counter information Lcnt. The first polarity control signal POLa generated in this first embodiment includes the first polarity control signals POLa and POLa shown in FIGS. 7A and 7B, 9A and 9B. The second embodiment of the first POL generation circuit 151 generates the first polarity control signal POLa in which logics H and L are inverted in units of one horizontal period based on the line counter information Lcnt. The first polarity control signal POLa generated in this second embodiment includes the polarity control signals POLa and POL2a shown in Figs. 8A and 8B, 10A and 10B. The first inverter 153 inverts the first polarity control signal POLa or the second polarity control signal POL2a and generates a third polarity control signal POLc generated by reverse phase of the polarity control signals POLa and POL2a. Alternatively, the second b polarity control signal POL2b is generated. Accordingly, the logic inversion period of the third polarity control signal POLc is determined according to the logic inversion period of the first polarity control signal POLa output from the first POL generation circuit 151 and is illustrated in FIGS. 7A to 10B. The third polarity control signal POLc or the second polarity control signal POL2b is included.

The second POL generation circuit 152 generates the second polarity control signal POLb shown in FIGS. 7A to 9B. The first embodiment of the second POL generation circuit 152 generates a second polarity control signal POLb in which logics H and L are inverted in units of one horizontal period based on the line counter information Lcnt. The second polarity control signal POLb generated in this first embodiment includes the second polarity control signal POLb shown in Figs. 7A and 7B. The second embodiment of the second POL generation circuit 152 generates a second polarity control signal POLb in which logics H and L are inverted in units of two horizontal periods based on the line counter information Lcnt. The second polarity control signal POLb generated in this second embodiment includes the second polarity control signals POLb and POLb shown in Figs. 8A and 8B, 9A and 9B. The second inverter 154 inverts the second polarity control signal POLb to generate the fourth polarity control signal POLd which is generated in the inverse phase of the second polarity control signal POLb. Accordingly, the logic inversion period of the fourth polarity control signal POLd is determined according to the logic inversion period of the second polarity control signal POLb output from the second POL generation circuit 152 and is illustrated in FIGS. 7A to 9B. One of the fourth polarity control signals POLc, POLc, and POLc is included. In the case of the polarity control signal for controlling the polarity pattern as shown in FIGS. 10A and 10B, the second POL generation circuit 152 and the inverter 154 connected to the output terminal thereof are not necessary.

The multiplexer 155 outputs the first polarity control signal POLa during the 4i + 1 frame period in response to the 2-bit frame count information Fcnt, and then outputs the second polarity control signal during the 4i + 2 frame period. After outputting POLb, the third polarity control signal POLc is output during the fourth i + 3 frame period. The multiplexer 155 outputs the fourth polarity control signal POLd during the fourth i + 4 frame period.

One of the polarity control signals POLa to POLd (or POL2a and POL2b) output from the POL generation circuit 143 and the reference polarity control signal POL generated by the internal circuit of the timing controller 101 It is selected by the multiplexer 144 as shown in FIG. The multiplexer 144 selects the polarity control signals POLa to POLd and POL to be supplied to the data driving circuit 103 according to the logic value of the control terminal connected to the POL selection option pin. The POL selection option pin may be connected to the control terminal of the multiplexer 144 and may be selectively connected to the ground voltage GND or the power supply voltage Vcc by the manufacturer or the user. For example, when the POL selection option pin is connected to the base voltage GND and the control terminal of the multiplexer 144, the multiplexer 144 is supplied with a selection control signal SEL of "0" to its control terminal so that the reference polarity control signal is provided. (POL) is output, and when the POL selection option pin is connected to the control voltage of the power supply voltage Vcc and the multiplexer 144, the multiplexer 144 is supplied with a selection control signal SEL of '1' to its control terminal. The polarity control signals POLa to POLd from the POL generation circuit 143 are output. The selection control signal SEL of the multiplexer 144 may be replaced by a selection control signal automatically generated from the system 105 or the timing controller 101 according to a user selection signal input through a user interface, or a result of data analysis. have.

19 shows a data driving circuit 133.

Referring to FIG. 19, the data driving circuit 133 includes a plurality of integrated circuits (ICs) for driving k data lines D1 to Dk (k is an integer smaller than m), respectively. Each of the circuits includes a shift register 161, a data register 162, a first latch 163, a second latch 164, a digital-to-analog converter (hereinafter referred to as a “DAC”) 165, and a charge share circuit ( Charge Share Circuit) 166 and the output circuit 167.

The shift register 161 shifts the source start pulse SSP from the timing controller 101 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register 161 shifts the source start pulse SSP to transfer the carry signal CAR to the shift register 161 of the next integrated circuit. The data register 162 temporarily stores odd digital video data RGBodd and even digital video data RGBeven separated by the timing controller 101 and stores the stored data RGBodd and RGBeven in the first latch 163. Supply. The first latch 163 samples the digital video data RGBeven and RGBodd from the data register 162 in response to a sampling signal sequentially input from the shift register 161, and the data (RGBeven and RGBodd). After latching by one horizontal line, data of one horizontal line is output simultaneously. The second latch 164 latches one horizontal line of data input from the first latch 163 and then second latches 164 of other integrated circuits during the low logic period of the source output enable signal SOE. And latched digital video data at the same time.

The DAC 165 is configured with a circuit as shown in FIG. 20 or 21. The DAC 165 receives the digital video data from the second latch 164 in response to the polarity control signals POL / POLa to POLd (POL2a and POL2b) and the horizontal output inversion signal HINV. ) Or negative gamma compensation voltage (GL) to convert to analog positive / negative data voltage.

The charge share circuit 166 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE to output the average value of the neighboring data voltages as the charge share voltage, or the source output enable signal. During the high logic period of SOE, the common voltage Vcom is supplied to the data output channels to reduce the sudden change of the positive data voltage and the negative data voltage.

The output circuit 167 includes a buffer to minimize attenuation of the analog data voltage supplied to the data lines D1 to Dk.

20 shows a first embodiment of a DAC 165. The DAC 165 of FIG. 20 outputs a data voltage in a polar pattern shown in FIGS. 7A and 7B, 8A and 8B, and 9A and 9B.

Referring to FIG. 20, the DAC 165 according to the first embodiment of the present invention may include a P-decoder (PDEC) 171 to which a positive gamma compensation voltage GH is supplied and a negative gamma compensation voltage GL. Multiplexers 173a to select an output of the P-decoder 171 and an output of the N-decoder 172 in response to the supplied N-decoder (NDEC) 172 and the polarity control signals POL / POLa to POLd. 173d), the horizontal output inverting circuit 180 inverts the logic of the selection control signal supplied to the control terminal of the multiplexer 123 in response to the horizontal output inverting signal HINV.

The P-decoder 171 decodes the digital video data input from the second latch 164 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder 172 uses the second latch ( The digital video data input from 164 is decoded, and a negative gamma compensation voltage corresponding to the gray scale value of the data is output.

The multiplexer 173 is controlled by the outputs of the 4i + 3 and 4i + 4 multiplexers 173c and 173d controlled by the polarity control signals POL / POLa to POLd and the horizontal output inverting circuit 180. 4i + 1 and 4i + 2 multiplexers 173a and 173b.

In response to the polarity control signal (POL / POLa to POLd) input to its non-inverting control terminal, the fourth i + 3 multiplexer 173c has a positive gamma compensation voltage and a negative polarity in units of one horizontal period or two horizontal periods. The gamma compensation voltage is alternately selected and the selected positive / negative gamma compensation voltage is output as an analog data voltage. In response to the polarity control signals POL / POLa to POLd input to the inversion control terminal of the 4i + 4 multiplexer 173d, the positive gamma compensation voltage and the negative gamma compensation are performed in units of one horizontal period or two horizontal periods. Select voltage alternately and output selected positive / negative gamma compensation voltage as analog data voltage.

In response to the output of the horizontal output inverting circuit 180 input to its non-inverting control terminal, the fourth i + 1 multiplexer 173a has a positive gamma compensation voltage and a negative gamma compensation in units of one horizontal period or two horizontal periods. Select voltage alternately and output selected positive / negative gamma compensation voltage as analog data voltage. In response to the output of the horizontal output inversion circuit 180 input to its inversion control terminal, the fourth i + 2 multiplexer 173b has a positive gamma compensation voltage and a negative gamma compensation voltage in units of one horizontal period or two horizontal periods. Alternately select and output the selected positive / negative gamma compensation voltage as analog data voltage. The horizontal output inverting circuit 180 converts the polarities of the day voltages to be supplied to the data lines in response to the horizontal output inversion signal HINV in a horizontal 1 dot inversion method (H1dot) or in a horizontal 2 dot inversion method (H2dot). The fourth i + 1 and fourth i + 2 multiplexers 173a and 173b are controlled to output data voltages.

The horizontal output inverting circuit 180 includes switch elements S1 and S2 and an inverter 174. The horizontal output inverting circuit 180 supplies a logic value of the selection control signal supplied to the control terminals of the fourth i + 1 multiplexer 173a and the fourth i + 2 multiplexer 173b in response to the horizontal output inverting signal HINV. To control. The input terminal of the first switch element S1 is connected to the polarity control signal supply terminal 181 and the output terminal of the first switch element S1 is inverted of the 4i + 1 and 4i + 2 multiplexers 173a and 173b. It is connected to the non-inverting control terminal. The inversion control terminal of the first switch element S1 is connected to the horizontal output inversion signal supply terminal 182. The input terminal of the second switch element S2 is connected to the polarity control signal supply terminal 181 and the output terminal of the second switch element S2 is connected to the inverter 174. The non-inverting control terminal of the second switch element S2 is connected to the horizontal output inverted signal supply terminal 182. The inverter 174 is connected to the output terminal of the second switch element S2 and the inverting / non-inverting control terminals of the 4i + 1 or 4i + 2 multiplexers 173a and 173b.

When the horizontal output inversion signal HINV is high, the second switch element S2 is turned on and the first switch element S1 is turned off. Then, the inverted polarity control signals POL / POLa to POLd are input to the non-inverting control terminal of the 4i + 1 multiplexer 173a, and the inverted polarity control signal to the inversion control terminal of the 4i + 2 multiplexer 173b. (POL / POLa to POLd) are input. When the horizontal output inversion signal HINV is low, the first switch element S1 is turned on and the second switch element S2 is turned off. Then, the polarity control signals POL / POLa to POLd are input directly to the non-inverting control terminal of the 4i + 1 multiplexer 173a, and the polarity control signals POL to the inverting control terminal of the 4i + 2 multiplexer 173b. / POLa ~ POLd) is entered as is. Therefore, when the horizontal output inversion signal HINV and the polarity control signals POLa to POLd are generated as shown in FIG. 22, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is illustrated in FIG. 7A. 7b, "-+ +-" for the 4i + 1 frame period, "-+ +-" for the 4i + 2 frame period, and "+--+" for the 4i + 3 frame period. &Quot; +-+-" during the fourth i + 4 frame period. If the horizontal output inversion signal HINV and the polarity control signals POLa to POLd are generated as shown in FIG. 23, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is illustrated in FIGS. 8A and FIG. 8i to "+--+" for the 4i + 1 frame period, to "-+ +-" for the 4i + 2 frame period, to "+--+" for the 4i + 3 frame period, 4i It becomes " +-+-" for +4 frame period. If the horizontal output inversion signal HINV and the polarity control signals POLa to POLd are generated as shown in FIG. 23, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is illustrated in FIGS. 8A and FIG. 4i + 1 frame period as "+-+-", 4i + 2 frame period as "-+ +-", 4i + 3 frame period as "-+-+", 4i It becomes " +--+ " for +4 frame period. If the horizontal output inversion signal HINV and the polarity control signals POLa to POLd are generated as shown in FIG. 24, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is illustrated in FIGS. 9A and FIG. 4i + 1 frame period as "+-+-", 4i + 2 frame period as "-+ +-", 4i + 3 frame period as "-+-+", 4i It becomes "+--+" for +4 frame period.

21 shows a second embodiment of the DAC 165. The DAC 165 of FIG. 21 outputs a data voltage in the polar pattern shown in FIGS. 10A and 10B.

Referring to FIG. 21, the DAC 165 according to the second embodiment of the present invention may include a P-decoder (PDEC) 171 to which a positive gamma compensation voltage (GH) is supplied and a negative gamma compensation voltage (GL). Multiplexers 173a to select an output of the P-decoder 171 and an output of the N-decoder 172 in response to the supplied N-decoder (NDEC) 172 and the polarity control signals POL / POLa to POLd. 173d), a horizontal output inversion circuit 190 for inverting the logic of the selection control signal supplied to the control terminal of the multiplexer 123 in response to the horizontal output inversion signal HINV.

The P-decoder 171 decodes the digital video data input from the second latch 164 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder 172 uses the second latch ( The digital video data input from 164 is decoded, and a negative gamma compensation voltage corresponding to the gray scale value of the data is output.

The multiplexer 173 is controlled by the outputs of the 4i + 1 and 4i + 2 multiplexers 173a and 173b controlled by the polarity control signals POL / POL2a and POL2b and the output of the horizontal output inverting circuit 190. 4i + 3 and 4i + 4 multiplexers 173c and 173d.

The fourth i + 1 multiplexer 173a alternates the positive gamma compensation voltage and the negative gamma compensation voltage in units of one horizontal period in response to the polarity control signals POL / POL2a and POL2b input to its non-inverting control terminal. Select and output the selected positive / negative gamma compensation voltage as analog data voltage. The fourth i + 2 multiplexer 173b alternates the positive and negative gamma compensation voltages in one horizontal period in response to the polarity control signals POL / POL2a and POL2b input to its inversion control terminal. Select and output the selected positive / negative gamma compensation voltage as analog data voltage.

The fourth i + 3 multiplexer 173c alternates the positive gamma compensation voltage and the negative gamma compensation voltage in units of one horizontal period in response to the output of the horizontal output inverting circuit 190 input to its non-inverting control terminal. Select and output the selected positive / negative gamma compensation voltage as analog data voltage. The fourth i + 4 multiplexer 173d alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in units of one horizontal period in response to the output of the horizontal output inversion circuit 190 input to its inversion control terminal. Then, the selected positive / negative gamma compensation voltage is output as an analog data voltage. The horizontal output inverting circuit 190 changes the polarity of the day voltages to be supplied to the data lines in response to the horizontal output inverting signal HINV in a horizontal 1 dot inversion method (H1dot) or in a horizontal 2 dot inversion method (H2dot). The fourth i + 3 and fourth i + 4 multiplexers 173c and 173d are controlled to output data voltages.

The horizontal output inverting circuit 190 includes switch elements S1 and S2 and an inverter 194. The horizontal output inverting circuit 190 controls the logic value of the selection control signal supplied to the control terminals of the fourth i + 3 multiplexer 173c and the fourth i + 4 multiplexer 173d in response to the horizontal output inverting signal HINV. do. The input terminal of the first switch element S1 is connected to the polarity control signal supply terminal 181 and the output terminal of the first switch element S1 is inverted of the 4i + 3 and 4i + 4 multiplexers 173c and 173d. It is connected to the non-inverting control terminal. The inversion control terminal of the first switch element S1 is connected to the horizontal output inversion signal supply terminal 182. The input terminal of the second switch element S2 is connected to the polarity control signal supply terminal 181 and the output terminal of the second switch element S2 is connected to the inverter 174. The non-inverting control terminal of the second switch element S2 is connected to the horizontal output inverted signal supply terminal 182. The inverter 194 is connected to the output terminal of the second switch element S2 and the inverting / non-inverting control terminals of the 4i + 1 or 4i + 2 multiplexers 173a and 173b.

When the horizontal output inversion signal HINV is high, the second switch element S2 is turned on and the first switch element S1 is turned off. Then, the inverted polarity control signals POL / POL2a and POL2b are input to the non-inverting control terminal of the 4i + 3 multiplexer 173c, and the inverted polarity control signal to the inverting control terminal of the 4i + 4 multiplexer 173d. (POL / POL2a, POL2b) are input. When the horizontal output inversion signal HINV is low, the first switch element S1 is turned on and the second switch element S2 is turned off. Then, the polarity control signals POL / POL2a and POL2b are directly input to the non-inverting control terminal of the 4i + 3 multiplexer 173c, and the polarity control signals POL to the inverting control terminal of the 4i + 4 multiplexer 173d. / POL2a, POL2b) are input as it is. Therefore, when the horizontal output inversion signal HINV and the polarity control signals POLa to POLd are generated as shown in FIG. 25, the horizontal polarity pattern of the data supplied to the 4i + 1 to 4i + 4 data lines is shown in FIG. 10A. And "+-+-" during the 4i + 1 frame period, "+--+" during the 4i + 2 frame period, and "-+-+" during the 4i + 3 frame period, as shown in FIG. 10B. &Quot;-+ +-" during the fourth i + 4 frame period.

26 is a flowchart illustrating a method of driving a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 20, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention analyzes the input data and determines whether the input data is data capable of generating a DC residual image such as interlace data or scroll data. (S1, S2)

In operation S2, when it is determined that the currently input data is data that may cause a DC residual image, the present invention may provide the first to fourth polarity control signals POLa to POLd or the second and second polarity control signals in frame period units. (POL2a, POL2b) are generated sequentially to control the data driving frequency of the first liquid crystal cell group lower than the data driving frequency of the second liquid crystal cell group within two frame periods. In addition, the present invention generates a horizontal output inversion signal (HINV) in which logic is inverted every one frame period, thereby differently controlling the horizontal polarity pattern of the data voltage output from the data driving circuit in units of one frame period.

In the step S2, if it is determined that the current input data is the data after which the DC residual image does not appear, the present invention generates the reference polarity control signal POL and generates the horizontal output inversion signal HINV in low logic in every frame period. The data driving frequency of the liquid crystal cells is controlled to be the same (S4).

27 shows a liquid crystal display according to a third embodiment of the present invention.

Referring to FIG. 27, a liquid crystal display according to a third exemplary embodiment of the present invention includes a system 105, a liquid crystal display panel 100, an image analysis circuit 201, a timing controller 101, and a POL logic circuit 202. , A data driver circuit 203, and a gate driver circuit 104. In this embodiment, the system 105, the liquid crystal display panel 100, the timing controller 101, and the gate driving circuit 104 are substantially the same as the above-described embodiments, and the same reference numerals are used to describe the detailed description thereof. It will be omitted.

The image analysis circuit 201 determines whether DC residual image may occur with respect to the digital video data of the currently input image. The image analysis circuit 201 compares data between neighboring lines in one frame image, and when the data between the lines is larger than a predetermined threshold value, the image analysis circuit 201 determines the currently input data as interlace data. In addition, the image analysis circuit 201 compares data of each pixel on a frame-by-frame basis to detect a moving image in the display image and a moving speed of the image, and if the moving image moves at a preset speed, the moving image is included. The frame data is determined to be scroll data. As a result of the image analysis, the image analysis circuit 201 generates a selection signal SEL2 indicating interlace data or scroll data and uses the selection signal SEL2 to generate the POL logic circuit (see FIG. 14 and FIG. 17). 202 is controlled.

In response to the selection signal SEL2 from the image analysis circuit 201, the POL logic circuit 202 generates the first to fourth polarity control signals during the 4i + 1 to 4i + 4 frame periods as shown in FIGS. 14 and 17. (POLa to POLd) or second and second polarity control signals POL2a and POL2b are sequentially generated and the logic of the horizontal output inversion signal HINV is inverted in units of one frame period. In addition, the POL logic circuit 202 transfers the reference polarity control signal POL to the data driving circuit 103 as it is when data other than interlace data and scroll data are input in response to the selection signal SEL2, and outputs the horizontal output. The logic of the inverted signal HINV is kept low.

The data driving circuit 203 latches the digital video data (RGBodd, RGBeven) under the control of the timing controller 101, and polarizes the digital video data from the POL logic circuit 182 (POL / POLa to POLd (POL2a). POL2b)) is converted into an analog positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and supplies the data voltage to the data lines D1 to Dm. The data driving circuit 203 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signals POL / POLa to POLd (POL2a and POL2b) from the POL logic circuit 202. . In addition, the data driving circuit 203 may change the polarity of the data voltages in response to the horizontal output inversion signal HINV from the POL logic circuit 202 to the horizontal 1 dot inversion method H1dot and the horizontal 2 dot inversion method H2dot. Control alternately).

The image analysis circuit 201 and the POL logic circuit 202 may be embedded in the timing controller 101.

As described above, the liquid crystal display device and the driving method thereof according to the embodiment of the present invention to control the drive frequency of the data voltage supplied to the first liquid crystal cell group of the liquid crystal display panel within two frame periods to prevent the afterimage In addition, the display frequency can be improved by controlling the driving frequency of the data voltage supplied to the second liquid crystal cell group to a high level, and the display quality can be improved by controlling the size of each of the first and second liquid crystal cell groups to be smaller. Let's do it.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (28)

A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And And a controller for generating the polarity control signal differently in units of frame periods. The liquid crystal display panel includes first and second liquid crystal cell groups having different data driving frequencies within two frame periods, wherein the first liquid crystal cell group and the second liquid crystal cell group are alternated in the vertical and horizontal directions and in units of one frame period. The positions of each other change, The controller controls a polarity of data voltages charged in the horizontally adjacent liquid crystal cells by supplying a horizontal output inversion signal whose logic is inverted in units of one frame period to the data driving circuit. The horizontal output inversion signal controls the polarity of the data voltages charged in the horizontally neighboring liquid crystal cells for one frame period in a horizontal one dot inversion manner, and then applies the horizontally neighboring liquid crystal cells for the next frame period. And controlling the polarity of the data voltages to be charged in a horizontal two dot inversion scheme. The method of claim 1, And each of the first and second liquid crystal cell groups has a size within 2x2 liquid crystal cells. The method of claim 1, The data driving frequency of the first liquid crystal cell group is lower than the data driving frequency of the second liquid crystal cell group. The method of claim 3, wherein The horizontal output inversion signal is, And inverting polarities of some of the data voltages among the data voltages output from the data driving circuit. The method of claim 4, wherein The data driving circuit, A plurality of first decoders for converting digital video data into a positive gamma compensation voltage; A plurality of second decoders for converting the digital video data into a negative gamma compensation voltage; A plurality of multiplexers for alternately selecting outputs of the first decoder and the second decoder in response to the polarity control signal; And And a horizontal output inverting circuit connected to control terminals of some of the multiplexers and inverting the control signal supplied to the control terminals in units of one frame period in response to the horizontal output inversion signal. Display. The method of claim 5, wherein The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in one horizontal period period; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 6, During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines in the 4i + 2 and 4i + 3 horizontal lines. And liquid crystal cells Clc arranged in 4i + 3 and 4i + 4 vertical lines in the 4i + 1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group is formed in the vertical and horizontal directions. 1 liquid crystal cell group disposed between, During the fourth i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines on the fourth i + 2 and fourth i + 3 horizontal lines, and the fourth i ++. Liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines in the first and fourth i + 4 horizontal lines, and the second liquid crystal cell group is disposed with the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. , During the 4i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i. Liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines in the +1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group has the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; Will be placed, During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i. Liquid crystal cells arranged on the fourth i + 1 and the fourth i + 2 vertical lines in the +1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group has the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. Liquid crystal display, characterized in that arranged. The method of claim 5, wherein The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in one horizontal period period; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in two horizontal period periods; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 8, During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 3 horizontal lines. And liquid crystal cells arranged on 4i + 1 and 4i + 2 vertical lines in the 4i + 1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group includes the first liquid crystal cell group in the vertical and horizontal directions. Placed in between, During the fourth i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines on the fourth i + 2 and fourth i + 3 horizontal lines, and the fourth i Liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines in the +1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group has the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; Will be placed, During the fourth i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines in the fourth i + 2 and fourth i + 3 horizontal lines and the fourth i; Liquid crystal cells arranged on the fourth i + 1 and the fourth i + 2 vertical lines in the +1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group has the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions. Will be placed, During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines on the 4i + 2 and 4i + 3 horizontal lines, and the 4i. Liquid crystal cells arranged on the fourth i + 3 and fourth i + 4 vertical lines in the +1 and 4i + 4 horizontal lines, wherein the second liquid crystal cell group has the first liquid crystal cell group interposed therebetween in the vertical and horizontal directions; Liquid crystal display, characterized in that arranged. The method of claim 5, wherein The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in the two horizontal period periods and having a phase difference by one horizontal period relative to the first polarity control signal; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 10, During the 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 1 and 4i + 2 vertical lines in the 4i + 1 and 4i + 3 horizontal lines. And liquid crystal cells arranged on 4i + 3 and 4i + 4 vertical lines in the 4i + 2 and 4i + 4 horizontal lines, and the second liquid crystal cell group includes the first liquid crystal cell group in the vertical and horizontal directions. Placed in between, During the 4i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines on the 4i + 1 and 4i + 3 horizontal lines, and the 4i. Liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines in +2 and 4i + 4 horizontal lines, and the second liquid crystal cell group intersects the first liquid crystal cell group in the vertical and horizontal directions. Placed in the During the fourth i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines on the fourth i + 1 and fourth i + 3 horizontal lines, and the fourth i Liquid crystal cells arranged on the fourth and fourth i + 3 vertical lines in the +2 and 4i + 4 horizontal lines, and the second liquid crystal cell group intersects the first liquid crystal cell group in the vertical and horizontal directions. Placed in the During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the 4i + 3 and 4i + 4 vertical lines in the 4i + 1 and 4i + 3 horizontal lines, and the 4i. Liquid crystal cells arranged on the fourth i + 1 and fourth i + 2 vertical lines in +2 and 4i + 4 horizontal lines, and the second liquid crystal cell group intersects the first liquid crystal cell group in the vertical and horizontal directions. Liquid crystal display device, characterized in that disposed in the. The method of claim 5, wherein The polarity control signal is A first polarity control signal generated during a fourth i + 1 frame period and a fourth i + 2 frame period and inverting logic in two horizontal period periods; And And a second polarity control signal generated during a fourth i + 3 frame period and a fourth i + 4 frame period, the logic being inverted in the second horizontal period period, and generated out of phase with respect to the first polarity control signal. Liquid crystal display device. The method of claim 12, During a 4i + 1 (i is an integer greater than or equal to 0) frame period, the first liquid crystal cell group includes liquid crystal cells arranged on vertical lines 4i + 3 and 4i + 4, and the second liquid crystal cell group is a 4i + group. Liquid crystal cells arranged on the first and fourth i + 2 vertical lines, During the fourth i + 2 frame period, the first liquid crystal cell group includes liquid crystal cells arranged in the fourth i + 1 and fourth i + 2 vertical lines, and the second liquid crystal cell group includes the fourth i + 3 and fourth i +. 4 liquid crystal cells arranged in a vertical line, During the fourth i + 3 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on vertical lines 4i + 3 and 4i + 4, and the second liquid crystal cell group includes the fourth i + 1 and fourth i + 2. It includes liquid crystal cells arranged in a vertical line, During the 4i + 4 frame period, the first liquid crystal cell group includes liquid crystal cells arranged on the fourth i + 1 and 4i + 2 vertical lines, and the second liquid crystal cell group includes the fourth i + 3 and fourth i +. 4. A liquid crystal display comprising liquid crystal cells arranged on four vertical lines. The method of claim 1, The controller, A frame counter for counting the gate start pulses to generate frame count information indicating the number of frames; A line counter for counting a source output enable signal to generate line count information indicating the number of horizontal lines of the liquid crystal display panel; A polarity control signal generation circuit configured to generate different polarity control signals in frame period units based on the frame count information and the line count information; And And a multiplexer for selecting the polarity control signals in response to the frame count information. The method of claim 14, Connected between the polarity control signal generation circuit and the multiplexer to invert a first polarity control signal generated from the polarity control signal generation circuit for a fourth i + 1 frame period to generate a third polarity control signal for a fourth i + 3 frame period; Generating a first inverter; And Connected between the polarity control signal generation circuit and the multiplexer to invert a second polarity control signal generated from the polarity control signal generation circuit for a fourth i + 2 frame period to thereby generate a fourth polarity control signal for a fourth i + 4 frame period; And a second inverter for generating. The method of claim 14, A fourth i + 3 frame period connected between the polarity control signal generating circuit and the multiplexer to invert a first polarity control signal generated from the polarity control signal generating circuit during a 4i + 1 frame period and a 4i + 2 frame period; And an inverter for generating a second polarity control signal during a 4i + 4 frame period. The method of claim 4, wherein And an image analysis circuit for analyzing the digital video data of the input image and controlling the polarity control signal and the horizontal output inversion signal generated from the controller according to the analysis result. A method of driving a liquid crystal display device having a plurality of data lines supplied with data voltages from a data driving circuit and a plurality of gate lines supplied with scan pulses from a gate driving circuit and having a liquid crystal display panel having a plurality of liquid crystal cells. In Supplying the data voltages to the data lines in response to a polarity control signal; Supplying the scan pulse to the gate lines; Generating the polarity control signal differently in units of frame periods; And Supplying a horizontal output inversion signal whose logic is inverted in units of one frame period to the data driving circuit to control polarities of data voltages charged in the horizontally adjacent liquid crystal cells; The liquid crystal display panel includes first and second liquid crystal cell groups having different data driving frequencies within two frame periods, wherein the first liquid crystal cell group and the second liquid crystal cell group are alternated in the vertical and horizontal directions and in units of one frame period. The positions of each other change, The horizontal output inversion signal controls the polarity of the data voltages charged in the horizontally neighboring liquid crystal cells for one frame period in a horizontal one dot inversion manner, and then applies the horizontally neighboring liquid crystal cells for the next frame period. A method of driving a liquid crystal display device, characterized in that the polarity of the data voltages to be charged is controlled by a horizontal two dot inversion method. The method of claim 18, And each of the first and second liquid crystal cell groups has a size within 2x2 liquid crystal cells. The method of claim 18, The data driving frequency of the first liquid crystal cell group is lower than the data driving frequency of the second liquid crystal cell group. The method of claim 20, The horizontal output inversion signal is, And inverting polarities of some of the data voltages among the data voltages output from the data driving circuit. The method of claim 20, The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in one horizontal period period; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 20, The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in one horizontal period period; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in two horizontal period periods; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 20, The polarity control signal is A first polarity control signal generated in a fourth i + 1 frame period and inverting logic in two horizontal period periods; A second polarity control signal generated in a fourth i + 2 frame period and inverting logic in the two horizontal period periods and having a phase difference by one horizontal period relative to the first polarity control signal; A third polarity control signal generated in a fourth i + 3 frame period and generated out of phase with respect to the first polarity control signal; And And a fourth polarity control signal generated in a fourth i + 4 frame period and generated out of phase with respect to the second polarity control signal. The method of claim 20, The polarity control signal is A first polarity control signal generated during a fourth i + 1 frame period and a fourth i + 2 frame period and inverting logic in two horizontal period periods; And And a second polarity control signal generated during a fourth i + 3 frame period and a fourth i + 4 frame period, the logic being inverted in the second horizontal period period, and generated out of phase with respect to the first polarity control signal. A method of driving a liquid crystal display device. The method of claim 21, And analyzing the digital video data of the input image and controlling the polarity control signal and the horizontal output inversion signal according to the analysis result. The method of claim 1, The data driving circuit converts the polarity of the data voltage in a horizontal one dot inversion manner during the one frame period in response to the low logic of the horizontal output inversion signal and in the next frame in response to the high logic of the horizontal output inversion signal. And converting the polarity of the data voltage during the horizontal two-dot inversion method. The method of claim 18, The data driving circuit converts the polarity of the data voltage in a horizontal one dot inversion manner during the one frame period in response to the low logic of the horizontal output inversion signal and in the next frame in response to the high logic of the horizontal output inversion signal. And converting the polarity of the data voltage in the horizontal two-dot inversion method for a period of time.

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