KR20090073262A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to raise the display quality by preventing the direct current after image or smudge. A liquid crystal display comprises an LCD panel(70), a data driving circuit(73), a gate driving circuit(74), and a timing controller(71). The LCD panel has the gate lines(G1 to Gn), the data lines(D1 to Dm) and a liquid crystal cell(C1c). The data driving circuit inverts the polarity of data voltage which is supplied to the data line in response to the first and second polarity control signal groups. The gate driving circuit supplies the gate pulse to the gate line. The timing controller controls the data driving circuit and the gate driving circuit by generating the polarity control signal. Each of first and second polarity control signal groups has the different polarity control signals.

Description

Liquid Crystal Display and Driving Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for preventing display afterimages and stains to improve display quality.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in portable information equipment, office equipment, computer, etc., and is also rapidly replaced by a cathode ray tube.

As shown in FIG. 1, a liquid crystal display device actively controls data by switching data voltages supplied to liquid crystal cells using thin film transistors (TFTs) formed in each liquid crystal cell (Clc), thereby improving display quality of moving images. Can be. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One example of such an example is when interlace data voltages are supplied to a liquid crystal display. The interlace method includes only the odd line data voltages to be displayed on the liquid crystal cells of the odd horizontal lines during the odd frame period, and includes only the data voltages to be displayed on the liquid crystal cells of the even horizontal lines during the even frame period.

2 is a waveform diagram illustrating an example of an interlaced data voltage supplied to a liquid crystal cell Clc. This example assumes that the liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, since the high polarity data voltage is supplied only to the liquid crystal cell Clc disposed on the odd horizontal line during the odd frame period, the positive data voltage becomes negative data voltage like the waveform in the box during the four frame periods. It is predominant compared to that of the direct current afterimage. Figure 3 is an image showing the experimental results of the DC afterimage resulting from the interlace data. When the original image as shown in the left image of FIG. 3 is supplied to the LCD panel for a predetermined time in an interlaced manner, the data voltage whose polarity changes in units of frame periods is remarkably changed in the odd and even frames as shown in FIG. When a data voltage of an intermediate gray level, for example, 127 gray levels is supplied to all the liquid crystal cells Clc of the liquid crystal display panel after the original image as shown in the figure, a direct current afterimage with a faint pattern of the original image appears as shown in the right image.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, the voltage of the same polarity is repeatedly generated in the liquid crystal cell Clc according to the correlation between the size of the scrolled picture and the scroll speed (moving speed). Accumulation may cause a DC afterimage. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC afterimage appearing when moving the diagonal pattern and the character pattern at a constant speed.

In the LCD, spots may appear on the display image. When a DC voltage of the same polarity is applied to the liquid crystal layer for a long time, impurity ions in the liquid crystal layer are divided along the polarity of the liquid crystal, and ions having different polarities are accumulated in the pixel electrode and the common electrode in the liquid crystal cell. When a direct current voltage is applied to the liquid crystal layer for a long time, the alignment film deteriorates while the accumulation amount of ions increases, and as a result, the alignment characteristic of the liquid crystal deteriorates. For this reason, staining occurs when a DC voltage is applied to the liquid crystal display for a long time. In order to improve the problem of unevenness, a method of developing a liquid crystal material having a low dielectric constant or improving an alignment material or an alignment method has been devised. However, this method requires a lot of time and cost to develop the material, and lowering the dielectric constant of the liquid crystal may cause another problem that the driving characteristics of the liquid crystal deteriorate. Experimentally found that the appearance time of the stain is faster the more impurities are ionized in the liquid crystal layer and the larger the acceleration factor. Acceleration factors include temperature, time, and direct currentization of liquid crystals. Therefore, spots appear faster as the temperature is applied or the longer the DC voltage of the same polarity is applied to the liquid crystal layer, the worse it becomes. Since stains appear irregularly even between panels manufactured through the same manufacturing line, a new material development or process improvement method cannot be solved, and a driving method of suppressing direct current of liquid crystal is most effective.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which are designed to solve the problems of the prior art and improve display quality by preventing direct current afterimage and stain.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of liquid crystal cells; A data driving circuit for inverting polarities of data voltages supplied to the data lines in response to a first polarity control signal group and a second polarity control signal group; A gate driving circuit supplying gate pulses to the gate lines; And a timing controller generating the polarity control signal and controlling the data driving circuit and the gate driving circuit.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a first polarity control signal group and a second polarity control signal group; Inverting the polarity of the data voltages supplied to the data lines in response to the polarity control signal groups; And supplying a gate pulse to the gate lines.

Each of the first and second polarity control signal groups includes a plurality of polarity control signals having different phases, and the second polarity control signal group excludes any one of the polarity control signals of the first polarity control signal group. Polarity control signals.

The liquid crystal display according to the exemplary embodiment of the present invention and its driving method generate a polarity control signal to be generated thereafter, instead of blocking any one of a plurality of polarity control signals generated with a predetermined rule every N frame periods. By dividing and driving the liquid crystal cells into the first liquid crystal cell group and the second liquid crystal cell group, DC afterimage is prevented, and all liquid crystal cells are operated only with the second liquid crystal cell group every N frame periods, thereby increasing liquidity of the liquid crystal and preventing stains.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 17.

5 and 6 are views for explaining the principle of suppressing the direct current of the liquid crystal in the liquid crystal display according to the embodiment of the present invention.

Referring to FIG. 5, the present invention shifts the phase of the polarity control signal to control the polarity reversal timing of the data voltages charged in the first and second liquid crystal cell groups. In the liquid crystal display of the present invention, a liquid crystal cell of a first liquid crystal cell group to which data voltages of the same polarity are supplied for two frame periods and a liquid crystal cell of a second liquid crystal cell group to which data voltages of different polarity are supplied for two frame periods are adjacent to each other. Done. The positions of the liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group are changed every frame period, and all liquid crystal cells are stored in the N (N is an integer greater than or equal to 8 or less) frame periods among M frame periods. 2 is operated as a group of liquid crystal cells to charge the data voltage having a polarity opposite to the polarity of the data voltage charged in the previous frame. In other words, the present invention periodically increases the fluidity of the liquid crystal molecules by driving the positions of the first liquid crystal cell group and the second liquid crystal cell group differently every frame and reversing the polarity of the voltages charged in all liquid crystal cells every N frame periods. Let's do it. Therefore, even if the input data is maintained in the same image data for a long time, the afterimage can be prevented and the spot can be prevented by suppressing the direct current of the liquid crystal.

Referring to FIG. 6, when the interlaced data in which the high data voltage is supplied to the liquid crystal cell during the odd frame period is displayed on the liquid crystal display, the present invention provides a polarity in the period of two frame periods to the liquid crystal cells of the first and second liquid crystal cell groups. The inverted data voltage is supplied. Then, like the waveforms in the box, the positive data voltages supplied to the liquid crystal cell during the Nth frame period and the N + 1th frame period and the negative polarity supplied to the same liquid crystal cell during the N + 2 and N + 3th frame periods. The data voltages are neutralized so that voltages of polarized polarities are not accumulated in the liquid crystal cell. Therefore, the liquid crystal display device of the present invention can prevent the direct current of the liquid crystal when the interlace data is supplied, thereby preventing the after-image residual image and stain.

7 to 9 illustrate a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 70, a timing controller 71, a logic circuit 72, a data driving circuit 73, and a gate driving circuit 74. It is provided.

In the liquid crystal display panel 70, a liquid crystal layer is formed between two glass substrates. The m data lines D1 to Dm and the n gate lines G1 to Gn cross the lower glass substrate of the liquid crystal display panel 70. The liquid crystal display panel 70 includes m × n liquid crystal cells Clc arranged in a matrix form by the cross structure of the data lines D1 to Dm and the n gate lines G1 to Gn. The liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group. The lower glass substrate of the liquid crystal display panel 70 has data lines D1 to Dm, gate lines G1 to Gn, a pixel electrode 1 of a liquid crystal cell Clc connected to a TFT, a TFT, and a storage capacitor. (Cst) and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 70. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. Polarizing plates having an optical axis orthogonal to each other are attached to the upper glass substrate and the lower glass substrate of the liquid crystal display panel 70, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface of the liquid crystal display panel 70.

The timing controller 71 separates the input digital video data RGB inputted from the video source 75 into odd pixel data RGBodd and even pixel data RGBeven in order to lower the transmission frequency of the digital video data. (RGBodd, RGBeven) are supplied to the data driving circuit 73 through six data buses. In addition, the timing controller 71 receives timing signals such as vertical / horizontal synchronization signals Vsync and Hsync, data enable, and clock signal CLK input from the video source 75. Control signals 73 for controlling the operation timing of the gate driver circuit 74 and the logic circuit 72 are generated. The video source 75 includes a scaler mounted on a system board, converts video data input from an external video device or video data of a broadcast signal received as a wireless signal into digital data and transmits the digital data to the timing controller 71. At the same time, the timing signals are transmitted to the timing controller 71. The control signals generated by the timing controller 71 include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start. It includes a pulse (Source Start Pulse: SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable: SOE), and a polarity control signal (Polarity: POL). The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit 74 to generate a pulse width corresponding to the ON period of the TFT as a timing control signal for sequentially shifting the gate start pulse GSP. do. The gate output enable signal GOE indicates the output of the gate driving circuit 74. The source start pulse SSP indicates a start pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs a latch operation of data in the data driving circuit 73 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 73. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 70. The polarity control signal POL is generated as either a polarity control signal of one dot inversion in which logic is inverted in one horizontal period or a polarity control signal of two dot inversion in which logic is inverted in two horizontal periods. In the following embodiment, the polarity control signal POL is generated as a polarity control signal of two dot inversion in which logic is inverted in two horizontal period periods.

The logic circuit 72 receives the gate start pulse GSP and the source output enable signal SOE to determine the frame and line of the image that is currently displayed, and as shown in FIGS. 11, 13, 15, and 17, FIG. Generate a polarity control signal group whose phase is shifted by one horizontal period every frame during the frame period, and repeat the output of the polarity control signal group for a certain period of time, and then periodically generate another polarity control signal group during the three frame periods. do.

The data driving circuit 73 latches the digital video data RGBodd and RGBeven under the control of the timing controller 71 and transmits the digital video data RGBodd and RGBeven to the polarity control signal POL from the logic circuit 72. In response, an analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 73 inverts the polarity of the data voltage in response to the polarity control signal POL from the logic circuit 72.

The gate driving circuit 74 includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, an output buffer, and the like. The gate driving circuit 74 is composed of a plurality of gate drive integrated circuits and sequentially outputs gate pulses (or scan pulses) having a pulse width of approximately one horizontal period.

8 and 9 are circuit diagrams showing the logic circuit 72 in detail.

Referring to FIG. 8, the logic circuit 72 includes a frame counter 81, a line counter 82, and a POL generation circuit 83.

The frame counter 81 is a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 70 in response to the gate start pulse GSP, which is generated once during one frame period and generated at the same time as the start of one frame period. Outputs information Fcnt.

The line counter 82 is a row in which the data is to be displayed in the liquid crystal display panel 70 in response to the source output enable signal SOE indicative of the output point of the data voltage from the data driving circuit 73 every horizontal period ( Or line count information Lcnt indicating a horizontal line).

As shown in FIG. 9, the POL generating circuit 83 may include a first POL generating circuit 91, a second POL generating circuit 92, first and second inverters 93 and 94, a multiplexer 95, and a frame controller ( 96, polarity control signals as shown in FIGS. 11, 13, 15, and 17 are generated.

The first POL generating circuit 91 generates a first polarity control signal POL # 1 whose logic is inverted according to the line counter information Lcnt and the frame counter information Fcnt. The first polarity control signal POL # 1 is inverted in two horizontal periods so that the liquid crystal cells vertically arranged side by side charge the data voltage whose polarity is inverted in a vertical two dot inversion scheme. The first inverter 93 inverts the first polarity control signal POL # 1 to generate the third polarity control signal POL # 3 in the reverse phase of the first polarity control signal POL # 1.

The second POL generation circuit 92 generates a second polarity control signal POL # 2 whose logic is inverted according to the line counter information Lcnt and the frame counter information Fcnt. The second polarity control signal POL # 2 is generated in a phase in which the phase of the first polarity control signal POL # 1 is shifted by approximately one horizontal period. The second inverter 94 inverts the second polarity control signal POL # 2 to generate the fourth polarity control signal POL # 4 in the reverse phase of the second polarity control signal POL # 2.

The multiplexer 95 may control the first polarity control signal POL # 1, the second polarity control signal POL # 2, the third polarity control signal POL # 3, for four frame periods under the control of the frame controller 96. The polarity control signal POL # 4 is sequentially output in order, and after a predetermined time elapses, the polarity control signal to be output thereafter instead of blocking any one of the four polarity control signals for three frame periods. Print them out in advance.

The frame controller 96 receives the line counter information Lcnt and the frame counter information Fcnt to determine the frames and lines of the currently displayed image. The frame controller 96 controls the multiplexer 95 by generating a selection signal for controlling the multiplexer 95 as a result of the determination of the frame and the line. Under the control of the frame controller 96, the multiplexer 95 generates polarity control signals as shown in Figs. 11, 13, 15, and 17.

10 and 11 illustrate a method of driving a liquid crystal display according to a first embodiment of the present invention.

10 and 11, the liquid crystal cells include a liquid crystal cell of a first liquid crystal cell group and a liquid crystal cell of a second liquid crystal cell group disposed adjacent to each other. "+" Is the liquid crystal cells charged with the positive data voltage, and "-" is the liquid crystal cells of the negative data voltage. The horizontal axis represents frame period (time), and the vertical axis represents lines (display surface).

The logic circuit 72 sequentially outputs the first polarity control signal group POL_FGDG1 # 1 to FGDG1 # 4 as shown in FIG. 11. The logic of the first polarity control signal POL_FGDG1 # 1 of the first polarity control signal group is inverted in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods. Repeat for a period of time. The second polarity control signal POL_FGDG1 # 2 of the first polarity control signal group is generated so as to have a phase difference by one horizontal period compared to the first polarity control signal POL_FGDG1 # 1, and high logic-> low logic for four horizontal periods. The logic is reversed in the order of-> low logic-> high logic and repeats this for 1 frame period. The third polarity control signal POL_FGDG1 # 3 of the first polarity control signal group is generated with an inverse phase of the first polarity control signal POL_FGDG1 # 1 and is low logic-> low logic-> high logic- for 4 horizontal periods. The logic is reversed in the order of> high logic and repeats this for one frame period. The fourth polarity control signal POL_FGDG1 # 4 of the first polarity control signal group is generated with an inverse phase of the second polarity control signal POL_FGDG1 # 2 and is low logic-> high logic-> high logic- for four horizontal periods. The logic is reversed in the order of low logic and is repeated for one frame period.

Subsequently, the logic circuit 72 repeats the output of the first polarity control signal group POL_FGDG1 # 1 to FGDG1 # 4 for a predetermined time, and then the first polarity control signal for the N-3 to N-1th frame periods. The second polarity control signal group POL_FGDG2 # 1 to FGDG2 # 3 without the fourth polarity control signal POL_FGDG1 # 4 is sequentially output from the groups POL_FGDG1 # 1 to FGDG1 # 4. The first polarity control signal POL_FGDG2 # 1 of the second polarity control signal group is generated in the same phase as the first polarity control signal POL_FGDG1 # 1 of the first polarity control signal group. The second polarity control signal POL_FGDG2 # 2 of the second polarity control signal group is generated in the same phase as the second polarity control signal POL_FGDG1 # 2 of the first polarity control signal group. The third polarity control signal POL_FGDG1 # 3 of the third polarity control signal group is generated in the same phase as the third polarity control signal POL_FGDG1 # 3 of the first polarity control signal group.

Subsequently, the logic circuit 72 repeatedly outputs the first polarity control signal group POL_FGDG1 # 1 to FGDG1 # 4 for the N to 2N-4 frame periods, and thereafter, for the second N-3 to 2N-1 frame periods. Outputs the second polarity control signal group POL_FGDG2 # 1 to FGDG2 # 3.

In response to the polarity control signal of FIG. 11, the data driving circuit 73 outputs the data voltage of FIG. 10. As a result, the liquid crystal cells are charged with a first liquid crystal cell group that charges the same data voltage as the data voltage charged in the previous frame period in the current frame period and a data voltage having a polarity opposite to the data voltage charged in the previous frame period. 2 divided into liquid crystal cell group. Except for the N and second N frame periods represented by the N frame periods of the first liquid crystal cell group and the second liquid crystal cell group, positions of each other are changed every frame. All liquid crystal cells operate as the second liquid crystal cell group during the N-th and the second-N frame periods.

Accordingly, the liquid crystal display device and the driving method thereof according to an embodiment of the present invention can reduce the afterimage after the operation by dividing the liquid crystal cell into the first and second liquid crystal cell group, and the data supplied to all liquid crystal cells in N frame periods. By reversing the polarity of the voltage to increase the fluidity of the liquid crystal molecules can be prevented staining.

12 and 13 illustrate a method of driving a liquid crystal display according to a second exemplary embodiment of the present invention.

12 and 13, the logic circuit 72 sequentially outputs the third polarity control signal groups POL_FGDG3 # 1 to FGDG3 # 4. The logic of the first polarity control signal POL_FGDG3 # 1 of the third polarity control signal group is inverted in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods and repeats this for 1 frame period. . The second polarity control signal POL_FGDG3 # 2 of the third polarity control signal group is generated to have a phase difference by one horizontal period compared to the first polarity control signal POL_FGDG3 # 1, and is low logic-> high for four horizontal periods. The logic is reversed in the order of logic-> high logic-> low logic and this is repeated for one frame period. The third polarity control signal POL_FGDG3 # 3 of the third polarity control signal group is generated with an inverse phase of the first polarity control signal POL_FGDG3 # 1, and is low logic-> low logic-> high logic- for four horizontal periods. The logic is reversed in the order of> high logic and repeats this for one frame period. The fourth polarity control signal POL_FGDG3 # 4 of the third polarity control signal group is generated with an inverse phase of the second polarity control signal POL_FGDG3 # 2, and during the four horizontal periods, high logic-> low logic-> low logic- The logic is reversed in the order of> high logic and repeats this for one frame period.

Subsequently, the logic circuit 72 repeats the output of the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for a predetermined time, and then the third polarity control signal for the N-3 to N-1th frame periods. The fourth polarity control signal group POL_FGDG4 # 1 to FGDG4 # 3 without the third polarity control signal POL_FGDG3 # 3 is sequentially output from the groups POL_FGDG3 # 1 to FGDG3 # 4. The first polarity control signal POL_FGDG4 # 1 of the fourth polarity control signal group is generated in the same phase as the first polarity control signal POL_FGDG3 # 1 of the third polarity control signal group. The second polarity control signal POL_FGDG4 # 2 of the fourth polarity control signal group is generated in the same phase as the second polarity control signal POL_FGDG3 # 2 of the third polarity control signal group. The third polarity control signal POL_FGDG4 # 3 of the fourth polarity control signal group is generated in the same phase as the fourth polarity control signal POL_FGDG3 # 4 of the third polarity control signal group.

Subsequently, the logic circuit 72 repeatedly outputs the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for the N to 2N-4 frame periods, and thereafter, for the second N-3 to 2N-1 frame periods. Outputs the fourth polarity control signal group POL_FGDG4 # 1 to FGDG4 # 3.

In response to the polarity control signal as shown in FIG. 13, the data driving circuit 73 outputs the data voltage as shown in FIG. 12. As a result, the positions of the first liquid crystal cell group and the second liquid crystal cell group are changed in each frame except for the N-1 and 2N-1 frame periods represented by the N frame period. All liquid crystal cells operate as the second liquid crystal cell group during the N-1 and 2N-1 frame periods.

14 and 15 illustrate a driving method of a liquid crystal display according to a third exemplary embodiment of the present invention.

14 and 15, the logic circuit 72 sequentially outputs the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 in the same manner as in the above-described second embodiment.

Subsequently, the logic circuit 72 repeats the output of the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for a predetermined time, and then the third polarity control signal for the N-3 to N-1th frame periods. The fifth polarity control signal group POL_FGDG5 # 1 to FGDG5 # 3 without the second polarity control signal POL_FGDG3 # 2 is sequentially output from the groups POL_FGDG3 # 1 to FGDG3 # 4. The first polarity control signal POL_FGDG5 # 1 of the fifth polarity control signal group is generated in the same phase as the first polarity control signal POL_FGDG3 # 1 of the third polarity control signal group. The second polarity control signal POL_FGDG5 # 2 of the fifth polarity control signal group is generated in the same phase as the third polarity control signal POL_FGDG3 # 3 of the third polarity control signal group. The third polarity control signal POL_FGDG5 # 3 of the fifth polarity control signal group is generated in the same phase as the fourth polarity control signal POL_FGDG3 # 4 of the third polarity control signal group.

Subsequently, the logic circuit 72 repeatedly outputs the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for the N to 2N-4 frame periods, and thereafter, for the second N-3 to 2N-1 frame periods. While outputting the fifth polarity control signal group POL_FGDG5 # 1 to FGDG5 # 3.

In response to the polarity control signal of FIG. 15, the data driving circuit 73 outputs the data voltage of FIG. 14. As a result, the positions of the first liquid crystal cell group and the second liquid crystal cell group are changed in each frame except for the N-2 and 2N-2 frame periods represented by N frame periods. All liquid crystal cells operate as the second liquid crystal cell group during the N-2 and 2N-2 frame periods.

16 and 17 illustrate a method of driving a liquid crystal display according to a fourth exemplary embodiment of the present invention.

16 and 17, the logic circuit 72 sequentially outputs the third polarity control signal groups POL_FGDG3 # 1 to FGDG3 # 4 in the same manner as in the second and third embodiments described above.

Subsequently, the logic circuit 72 repeats the output of the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for a predetermined time, and then the third polarity control signal for the N-3 to N-1th frame periods. The sixth polarity control signal group POL_FGDG6 # 1 to FGDG6 # 3 without the first polarity control signal POL_FGDG3 # 1 is sequentially output from the groups POL_FGDG3 # 1 to FGDG3 # 4. The first polarity control signal POL_FGDG6 # 1 of the sixth polarity control signal group is generated in the same phase as the second polarity control signal POL_FGDG3 # 2 of the third polarity control signal group. The second polarity control signal POL_FGDG6 # 2 of the sixth polarity control signal group is generated in the same phase as the third polarity control signal POL_FGDG3 # 3 of the third polarity control signal group. The third polarity control signal POL_FGDG5 # 3 of the sixth polarity control signal group is generated in the same phase as the fourth polarity control signal POL_FGDG3 # 4 of the third polarity control signal group.

Subsequently, the logic circuit 72 repeatedly outputs the third polarity control signal group POL_FGDG3 # 1 to FGDG3 # 4 for the N to 2N-4 frame periods, and thereafter, for the second N-3 to 2N-1 frame periods. Outputs the sixth polarity control signal group (POL_FGDG6 # 1 to FGDG6 # 3).

In response to the polarity control signal of FIG. 17, the data driving circuit 73 outputs the data voltage of FIG. 16. As a result, the positions of the first liquid crystal cell group and the second liquid crystal cell group are changed in each frame except for the N-3 and 2N-3 frame periods represented by the N frame period. All liquid crystal cells operate as the second liquid crystal cell group during the N-3 and 2N-3 frame periods.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

FIG. 5 is a view for explaining a principle that a DC afterimage does not appear in scroll data when the method of driving a liquid crystal display according to an exemplary embodiment of the present invention is applied. FIG.

Fig. 6 is a waveform diagram showing the effect of suppressing direct currentization of liquid crystal on interlaced data.

7 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing details of the logic circuit shown in FIG. 7; FIG.

9 is a block diagram showing in detail the POL generation circuit shown in FIG.

FIG. 10 is a view illustrating polarities of data voltages charged in liquid crystal cells in a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 11 is a waveform diagram showing polarity control signals for controlling the polarity of the data voltage shown in FIG.

12 is a view showing polarities of data voltages charged in liquid crystal cells in a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 13 is a waveform diagram showing polarity control signals for controlling the polarity of the data voltage shown in FIG.

14 is a view illustrating polarities of data voltages charged in liquid crystal cells in a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 15 is a waveform diagram showing polarity control signals for controlling the polarity of the data voltage shown in FIG.

16 is a view illustrating polarities of data voltages charged in liquid crystal cells in a liquid crystal display according to a fourth exemplary embodiment of the present invention.

17 is a waveform diagram showing polarity control signals for controlling the polarity of the data voltage shown in FIG.

<Explanation of symbols for main parts of drawing>

70: liquid crystal display panel 71: timing controller

72: logic circuit 73: data drive circuit

74: gate driving circuit 81: frame counter

82: line counters 83, 91, 92: POL generation circuit

93, 94: Inverter

95: multiplexer

Claims (16)

A liquid crystal display panel having a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of liquid crystal cells; A data driving circuit for inverting polarities of data voltages supplied to the data lines in response to a first polarity control signal group and a second polarity control signal group; A gate driving circuit supplying gate pulses to the gate lines; And A timing controller generating the polarity control signal and controlling the data driving circuit and the gate driving circuit; Each of the first and second polarity control signal groups includes a plurality of polarity control signals having different phases, and the second polarity control signal group excludes any one of the polarity control signals of the first polarity control signal group. And a polarity control signal. The method of claim 1, The liquid crystal cells, A first liquid crystal cell group charging a data voltage having the same polarity as that of the data voltage charged in the previous frame period; And A second liquid crystal cell group charging a data voltage having a polarity opposite to that of the data voltage charged in the previous frame period; Wherein the first and second liquid crystal cell groups are shifted from one another in every frame period for a predetermined time period, and the liquid crystal cells operate only in the second liquid crystal cell group at every N frame period. The method of claim 1, The first polarity control signal group, A first polarity control signal inverting logic in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods and repeating this for 1 frame period; A second polarity control signal inverting logic in the order of high logic-> low logic-> low logic-> high logic for the four horizontal periods and repeating this for one frame period; A third polarity control signal inverting logic in the order of low logic-> low logic-> high logic-> high logic for the four horizontal periods and repeating this for one frame period; And And a fourth polarity control signal inverting logic in the order of low logic-> high logic-> high logic-> low logic for the four horizontal periods and repeating the logic for one frame period. The method of claim 3, wherein The second polarity control signal group, And the first polarity control signal, the second polarity control signal, and the third polarity control signal. The method of claim 1, The first polarity control signal group, A first polarity control signal inverting logic in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods and repeating this for 1 frame period; A second polarity control signal inverting logic in the order of low logic-> high logic-> high logic-> low logic for the four horizontal periods and repeating this for one frame period; A third polarity control signal inverting logic in the order of low logic-> low logic-> high logic-> high logic for the four horizontal periods and repeating this for one frame period; And And a fourth polarity control signal inverting logic in the order of high logic-> low logic-> low logic-> high logic for the four horizontal periods and repeating the logic for one frame period. The method of claim 5, wherein The second polarity control signal group, And the first polarity control signal, the second polarity control signal, and the fourth polarity control signal. The method of claim 5, wherein The second polarity control signal group, And the first polarity control signal, the third polarity control signal, and the fourth polarity control signal. The method of claim 5, wherein The second polarity control signal group, And the second polarity control signal, the third polarity control signal, and the fourth polarity control signal. A method of driving a liquid crystal display device having a liquid crystal display panel having a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells, Generating a first polarity control signal group and a second polarity control signal group; Inverting the polarity of the data voltages supplied to the data lines in response to the polarity control signal groups; And Supplying a gate pulse to the gate lines; Each of the first and second polarity control signal groups includes a plurality of polarity control signals having different phases, and the second polarity control signal group excludes any one of the polarity control signals of the first polarity control signal group. A driving method of a liquid crystal display device comprising polarity control signals. The method of claim 9, The liquid crystal cells, A first liquid crystal cell group charging a data voltage having the same polarity as that of the data voltage charged in the previous frame period; And A second liquid crystal cell group charging a data voltage having a polarity opposite to that of the data voltage charged in the previous frame period; Wherein the first and second liquid crystal cell groups are shifted from one another in every frame period for a predetermined time period, and the liquid crystal cells operate only in the second liquid crystal cell group at every N frame period. The method of claim 9, The first polarity control signal group, A first polarity control signal inverting logic in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods and repeating this for 1 frame period; A second polarity control signal inverting logic in the order of high logic-> low logic-> low logic-> high logic for the four horizontal periods and repeating this for one frame period; A third polarity control signal inverting logic in the order of low logic-> low logic-> high logic-> high logic for the four horizontal periods and repeating this for one frame period; And And a fourth polarity control signal in which logic is inverted in the order of low logic-> high logic-> high logic-> low logic for the four horizontal periods and repeats this for one frame period. Driving method. The method of claim 11, The second polarity control signal group, And the first polarity control signal, the second polarity control signal, and the third polarity control signal. The method of claim 9, The first polarity control signal group, A first polarity control signal inverting logic in the order of high logic-> high logic-> low logic-> low logic for 4 horizontal periods and repeating this for 1 frame period; A second polarity control signal inverting logic in the order of low logic-> high logic-> high logic-> low logic for the four horizontal periods and repeating this for one frame period; A third polarity control signal inverting logic in the order of low logic-> low logic-> high logic-> high logic for the four horizontal periods and repeating this for one frame period; And And a fourth polarity control signal inverting logic in the order of high logic-> low logic-> low logic-> high logic for the four horizontal periods and repeating the same for one frame period. Way. The method of claim 13, The second polarity control signal group, And the first polarity control signal, the second polarity control signal, and the fourth polarity control signal. The method of claim 13, The second polarity control signal group, And the first polarity control signal, the third polarity control signal, and the fourth polarity control signal. The method of claim 13, The second polarity control signal group, And the second polarity control signal, the third polarity control signal, and the fourth polarity control signal.

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