KR100855037B1 - Method for forming the DRAM cell - Google Patents

Method for forming the DRAM cell Download PDF

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KR100855037B1
KR100855037B1 KR1020020036228A KR20020036228A KR100855037B1 KR 100855037 B1 KR100855037 B1 KR 100855037B1 KR 1020020036228 A KR1020020036228 A KR 1020020036228A KR 20020036228 A KR20020036228 A KR 20020036228A KR 100855037 B1 KR100855037 B1 KR 100855037B1
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capacitor
forming
bit line
word line
dram
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KR20040001128A (en
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전성도
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 디램 메모리 셀의 제조방법에 관한 것으로, 특히 기존의 비트라인 콘택을 중심으로 워드라인이 양쪽에 배치되고, 바로 인접하여 모스 커패시터가 배치되어있는 구조에 있어서, 평탄 커패시터 플레이트와 워드라인을 하나로 통합하여 셀면적을 줄이도록 하는 것으로 워드라인 영역의 게이트절연막을 두껍게 형성하여 커패시터 플레이트 중 워드라인을 사용될 부분의 하부 문턱전압을 높여 대기상태일 때 커패시터와 비트라인과의 격리가 가능하도록 하는 것을 특징으로 하여, 기존의 공정 단계에서 간단히 레이아웃의 변경만으로 평판 구조의 디램 셀 면적을 줄일 수 있어 반도체소자의 제조 수율을 향상 시킬수 있는 기술이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM memory cell. In particular, in a structure in which word lines are disposed on both sides of a conventional bit line contact and MOS capacitors are disposed immediately adjacent to each other, a flat capacitor plate and a word line are provided. In order to reduce the cell area by integrating into one, the gate insulation layer in the word line region is formed thick so that the lower threshold voltage of the word line portion of the capacitor plate is used to increase the isolation between the capacitor and the bit line in the standby state. As a feature, it is possible to reduce the area of the DRAM cell of the flat plate structure by simply changing the layout in the existing process step, thereby improving the manufacturing yield of semiconductor devices.

커패시터, 플레이트, 워드라인, 디램 셀Capacitors, Plates, Word Lines, DRAM Cells

Description

디램 셀의 제조방법{Method for forming the DRAM cell}Manufacturing method of DRAM cell {Method for forming the DRAM cell}

도 1은 종래 기술에 따른 디램 셀을 설명하기 위해 디램 메모리 셀 어레이를 나타낸 평면도이다.1 is a plan view illustrating a DRAM memory cell array to describe a DRAM cell according to the related art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 디램 셀의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a DRAM cell according to an exemplary embodiment of the present invention.

-- 도면의 주요부분에 대한 부호의 설명 -- -Explanation of symbols for the main parts of the drawing-

100 : 실리콘 기판 102 : 소자분리막100 silicon substrate 102 device isolation film

104 : 워드라인의 게이트산화막104: gate oxide film of word line

106 : 커패시터의 절연막106: insulating film of the capacitor

108 : 커패시터 전극 110 : 스페이서108: capacitor electrode 110: spacer

112 : 소오스/드레인 114 : 실리사이드층112 source / drain 114 silicide layer

116 : 층간절연막 118 : 금속플러그116: interlayer insulating film 118: metal plug

120 : 비트라인120: bit line

본 발명은 디램 셀의 제조방법에 관한 것으로, 보다 상세하게는 평탄 커패시터 플레이트와 워드라인을 하나로 통합하여 평판 구조의 디램 셀 면적을 줄일 수 있어 반도체소자의 제조 수율을 향상 시킬 수 있도록 하는 디램 셀의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a DRAM cell, and more particularly, to a DRAM cell having a flat capacitor plate and a word line integrated into one to reduce the area of a DRAM cell having a flat plate structure, thereby improving a manufacturing yield of a semiconductor device. It relates to a manufacturing method.

일반적으로 MOS(Metal-Oxide-Semiconductor, 이하 MOS 이라 칭함)형 DRAM(Dynamic Random Access Memory, 이하 DRAM 이라 칭함)은 하나의 MOS 트랜지스터 및 하나의 커패시터로 이루어진 메모리 셀(Memory Cell)을 갖는다.In general, a MOS (Metal-Oxide-Semiconductor) type DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) has a memory cell consisting of one MOS transistor and one capacitor.

최근 반도체 집적회로 공정 기술이 발달함에 따라 반도체 기판 상에 제조되는 소자의 최소 선폭 길이는 더욱 미세화되고, 단위 면적당 집적도는 증가하고 있다. 한편, 메모리 셀의 집적도가 증가함에 따라서 전하 저장용 셀 커패시터가 점유 할 수 있는 공간은 더욱 좁아지게 되므로, 단위 면적당 정전 용량이 증대된 셀 커패시터의 개발이 필수적이다.With the recent development of semiconductor integrated circuit processing technology, the minimum line width length of devices fabricated on a semiconductor substrate is further miniaturized, and the degree of integration per unit area is increasing. On the other hand, as the density of memory cells increases, the space that can be occupied by the cell capacitor for charge storage becomes narrower. Therefore, it is essential to develop a cell capacitor with increased capacitance per unit area.

도 1은 종래 기술에 따른 디램 셀의 제조방법에 의해 제조된 디램 셀의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a DRAM cell manufactured by a DRAM cell manufacturing method according to the prior art.

도 1에 도시된 바와 같이, 비트라인 콘택(5)을 중심으로 얇은 게이트산화막(3)을 기반으로 구성된 워드라인(7)이 양쪽에 형성되고, 이 워드라인(7)에 인접하여 모스 커패시터(8)가 형성된다. As shown in FIG. 1, word lines 7 formed on the basis of the bit line contacts 5 based on the thin gate oxide film 3 are formed on both sides thereof, and adjacent to the word lines 7, a MOS capacitor ( 8) is formed.                         

또한, 상기 워드라인(7)과 모스 커패시터(8) 사이는 게이트 스페이서(11)로 격리되어 있고, 그 격리된 부분에 셀 정션(12)이 형성되어있다.In addition, the word line 7 and the MOS capacitor 8 are separated by a gate spacer 11, and a cell junction 12 is formed in the isolated portion.

그러나, 상기와 같은 종래의 디램 메모리 셀의 구조는 워드라인(7)과 모스 커패시터(8) 격리를 위해 스페이서(11)를 형성하여야 할 추가 면적이 필요한 문제점이 있었다.However, the conventional DRAM memory cell has a problem in that an additional area for forming the spacer 11 is required to isolate the word line 7 and the MOS capacitor 8.

또한, 상기 워드라인(7)과 모스 커패시터(8) 사이를 격리한 부분에 셀 정션(12)이 형성됨으로써, 디램 동작 시, 셀 정션(12)으로 흐르게 되는 누설전류에 의해 디램 리프레쉬 특성을 악화시키는 문제점이 있었다.
In addition, since the cell junction 12 is formed in an area between the word line 7 and the MOS capacitor 8, the DRAM refresh characteristic is deteriorated due to leakage current flowing to the cell junction 12 during the DRAM operation. There was a problem letting.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 기존의 공정 단계에서 간단히 레이아웃의 변경만으로 평판 구조의 디램 셀 면적을 줄일 수 있도록 하는 디램 셀의 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, an object of the present invention is to provide a method for manufacturing a DRAM cell to reduce the DRAM cell area of the flat plate structure simply by changing the layout in the existing process step. .

상기 목적을 달성하기 위하여, 본 발명은 소자분리막이 형성된 반도체기판 상에, 트랜지스터 영역에는 제1 산화막을, 커패시터 영역에는 제1 산화막보다 얇은 제2 산화막을 각각 형성하는 단계와, 반도체기판 상에 워드라인 및 커패시터의 상부전극으로 사용될 전극막 패턴을 형성하는 단계와, 전극막 패턴의 측벽에 절연막 스페이서를 형성하는 단계와, 반도체기판에 불순물을 주입하여 소오스/드레인을 형성하는 단계와, 소오스/드레인이 형성된 결과물 상에 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 비트라인 콘택홀을 형성하는 단계, 및 비트라인 콘택홀을 통해 소오스/드레인과 접속된 비트라인을 형성하는 단계를 포함하는 것을 특징으로 하는 디램 셀의 제조방법을 제공한다.
상기 제1 산화막은 상기 제2 산화막 보다 10~100배 두껍게 형성할 수 있다.
상기 전극막 패턴은 워드라인과 커패시터의 상부전극으로 공통으로 사용된다.In order to achieve the above object, the present invention comprises the steps of forming a first oxide film in the transistor region, a second oxide film thinner than the first oxide film in the capacitor region, respectively, on the semiconductor substrate on which the device isolation film is formed; Forming an electrode film pattern to be used as an upper electrode of lines and capacitors, forming an insulating film spacer on the sidewalls of the electrode film pattern, implanting impurities into the semiconductor substrate to form a source / drain, and / or source / drain Forming an interlayer insulating film on the formed product, etching the interlayer insulating film to form a bit line contact hole, and forming a bit line connected to the source / drain through the bit line contact hole. Provided is a method for manufacturing a DRAM cell.
The first oxide film may be formed 10 to 100 times thicker than the second oxide film.
The electrode film pattern is commonly used as an upper electrode of a word line and a capacitor.

상기 전극막 패턴의 한쪽 끝부분이 상기 제1 산화막의 끝부분과 일치하도록 형성할 수 있다.One end of the electrode film pattern may be formed to coincide with the end of the first oxide film.

삭제delete

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 디램 셀의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a DRAM cell according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 실리콘기판(100) 내에 소자간 격리를 위한 소자분리막(102)을 형성하고, 듀얼 게이트 산화 마스크(미도시함)를 사용하여 트랜지스터 영역의 실리콘기판(100) 상에 두꺼운 산화막(104)을 형성한 후, 커패시터 영역에의 실리콘기판(100) 상에는 얇은 산화막(106)을 형성한다.As shown in FIG. 2A, a device isolation layer 102 is formed in the silicon substrate 100 for isolation between devices, and a dual gate oxide mask (not shown) is used on the silicon substrate 100 in the transistor region. After the thick oxide film 104 is formed, a thin oxide film 106 is formed on the silicon substrate 100 in the capacitor region.

상기 듀얼 산화막은 트랜지스터 영역의 산화막(104)이 커패시터 영역의 산화막(106) 보다 10~100배 더 두껍게 형성한다. 즉, 동작 전압이 커패시터에 인가되었을 경우, 두껍게 형성된 산화막(104)으로 인해 문턱전압이 동작 전압보다 높게 형성되어 동작 전압 이하에서 커패시터 하부전극의 전하가 빠져나가지 못하도록 구성된다.In the dual oxide film, the oxide film 104 in the transistor region is formed to be 10 to 100 times thicker than the oxide film 106 in the capacitor region. That is, when the operating voltage is applied to the capacitor, the threshold voltage is formed higher than the operating voltage due to the thick oxide film 104 is configured to prevent the charge of the lower electrode of the capacitor to escape below the operating voltage.

그리고, 데이터를 읽거나 쓸 때 커패시터 영역의 산화막(106)에 인가되는 전압은 트랜지스터의 문턱전압보다 더 크게 인가하여 트랜지스터가 턴온(Turn On)되게 한다.When the data is read or written, the voltage applied to the oxide film 106 in the capacitor region is greater than the threshold voltage of the transistor so that the transistor is turned on.

이어서, 도 2b에 도시된 바와 같이, 결과물 상에 워드라인과 커패시터의 전극 형성을 위한 다결정실리콘을 증착한 후, 노광 및 식각 공정을 진행하여 전극막 패턴(108)을 형성한다. 이때, 상기 전극막 패턴(108)의 끝부분이 트랜지스터 영역의 산화막(104)의 끝부분과 일치되도록 형성한다. 상기 전극막 패턴(108)은 워드라인과 커패시터의 상부전극으로 공통으로 사용된다.Subsequently, as illustrated in FIG. 2B, polycrystalline silicon for forming the electrode of the word line and the capacitor is deposited on the resultant, and then an electrode layer pattern 108 is formed by performing an exposure and etching process. In this case, an end portion of the electrode layer pattern 108 is formed to coincide with an end portion of the oxide layer 104 in the transistor region. The electrode film pattern 108 is commonly used as an upper electrode of a word line and a capacitor.

그 후, 상기 결과물 상에 절연물을 증착한 후, 이방성 건식 식각 공정을 진행하여 전극막 패턴의 측벽에 스페이서(110)를 형성한다.Thereafter, after depositing an insulating material on the resultant, an anisotropic dry etching process is performed to form spacers 110 on sidewalls of the electrode film pattern.

그리고, 도 2c에 도시된 바와 같이, 상기 실리콘기판(100) 내에 이온 주입 공정을 실시하여 소오스/드레인(112)을 형성한 후, 상기 전극막 패턴(108) 상부에 상기 전극막 패턴(108)의 저항을 낮추기 위한 실리사이드층(114)을 형성한다.As shown in FIG. 2C, after the ion implantation process is performed in the silicon substrate 100 to form a source / drain 112, the electrode layer pattern 108 is formed on the electrode layer pattern 108. The silicide layer 114 is formed to lower the resistance.

이어서, 상기 결과물 전체에 후속 공정에 의해 형성될 비트라인과 커패시터 전극 간의 절연을 위해 층간절연막(116)을 증착하고, 그 층간절연막(116) 상에 비트라인 콘택 형성을 위한 감광막 패턴(미도시함)을 형성한 후, 이를 식각마스크로 식각하여 비트라인 콘택홀(미도시함)을 형성한다.Subsequently, an interlayer insulating film 116 is deposited on the entire resultant to insulate between the bit line and the capacitor electrode to be formed by a subsequent process, and a photoresist pattern (not shown) for forming a bit line contact on the interlayer insulating film 116. ), And then etched with an etching mask to form a bit line contact hole (not shown).

그 후, 상기 비트라인 콘택홀(미도시함)을 금속으로 매립하여 금속플러그(118)를 형성한 후, 결과물 전체에 금속을 증착하여 비트라인(120)을 형성한다.Thereafter, the bit line contact hole (not shown) is filled with metal to form a metal plug 118, and then metal is deposited on the entire resultant to form the bit line 120.

상기한 바와 같이, 본 발명에 따른 디램 셀의 제조방법을 이용하게 되면, 평판 커패시터 플레이트와 워드라인이 하나로 통합되어 기존의 공정 단계에서 간단히 레이아웃의 변경만으로 평판 구조의 디램 셀 면적을 줄일 수 있어 반도체소자의 제조 수율을 향상시킬 수 있을 뿐만 아니라, 워드라인의 게이트절연막을 두껍게 형성하여 워드라인으로 사용될 부분의 문턱전압을 높여 대기상태일 때 커패시터와 비트라인과의 격리가 가능하도록 하여, 디램 동작 시 셀 정션으로 흐르게 되는 누설전류를 방지하여 리프레쉬 특성을 향상시킬 수 있다.As described above, when the DRAM cell manufacturing method according to the present invention is used, the flat plate capacitor plate and the word line are integrated into one, so that the DRAM cell area of the flat plate structure can be reduced by simply changing the layout in an existing process step. In addition to improving the fabrication yield of the device, the gate insulating layer of the word line is formed thicker to increase the threshold voltage of the portion to be used as the word line, so that the capacitor and the bit line can be isolated in the standby state. The refresh characteristics can be improved by preventing leakage current flowing to the cell junction.

Claims (5)

소자분리막이 형성된 반도체기판 상에, 트랜지스터 영역에는 제1 산화막을, 커패시터 영역에는 상기 제1 산화막보다 얇은 제2 산화막을 각각 형성하는 단계;Forming a first oxide film in the transistor region and a second oxide film thinner than the first oxide film in the capacitor region on the semiconductor substrate on which the device isolation film is formed; 상기 반도체기판 상에 워드라인 및 커패시터의 상부전극으로 사용될 전극막 패턴을 형성하는 단계;Forming an electrode film pattern to be used as an upper electrode of a word line and a capacitor on the semiconductor substrate; 상기 전극막 패턴의 측벽에 절연막 스페이서를 형성하는 단계;Forming an insulating film spacer on sidewalls of the electrode film pattern; 상기 반도체기판에 불순물을 주입하여 소오스/드레인을 형성하는 단계;Implanting impurities into the semiconductor substrate to form a source / drain; 상기 소오스/드레인이 형성된 결과물 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the resultant material on which the source / drain is formed; 상기 층간절연막을 식각하여 비트라인 콘택홀을 형성하는 단계; 및Etching the interlayer insulating layer to form a bit line contact hole; And 상기 비트라인 콘택홀을 통해 상기 소오스/드레인과 접속된 비트라인을 형성하는 단계를 포함하는 것을 특징으로 하는 디램 메모리 셀의 제조방법.And forming a bit line connected to the source / drain through the bit line contact hole. 삭제delete 제1항에 있어서, The method of claim 1, 상기 제1 산화막은 상기 제2 산화막 보다 10~100배 두껍게 형성하는 것을 특징으로 하는 디램 메모리 셀의 제조방법.And the first oxide layer is formed 10 to 100 times thicker than the second oxide layer. 제1항에 있어서,The method of claim 1, 상기 전극막 패턴은 워드라인과 커패시터의 상부전극으로 공통으로 사용되는 것을 특징으로 하는 디램 메모리 셀의 제조방법.The electrode film pattern is a method of manufacturing a DRAM memory cell, characterized in that commonly used as the upper electrode of the word line and the capacitor. 제1항에 있어서,The method of claim 1, 상기 전극막 패턴의 한쪽 끝부분이 상기 제1 산화막의 끝부분과 일치하도록 형성하는 것을 특징으로 하는 디램 메모리 셀의 제조방법.And forming one end of the electrode film pattern to coincide with the end of the first oxide film.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945875A (en) * 1995-07-28 1997-02-14 Nec Corp Semiconductor memory device and manufacture thereof
KR20000026819A (en) * 1998-10-23 2000-05-15 김영환 Method of manufacturing dual gate oxide layer
KR20010008436A (en) * 1998-12-30 2001-02-05 김영환 Method for manufacturing hybrid semiconductor device
KR20010111864A (en) * 2000-06-14 2001-12-20 윤종용 Capacitor in dynamic random access memory device and method of manufacturing the same
KR20020038471A (en) * 2000-11-17 2002-05-23 아끼구사 나오유끼 Non-volatile semiconductor memory device and fabrication method of the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945875A (en) * 1995-07-28 1997-02-14 Nec Corp Semiconductor memory device and manufacture thereof
KR20000026819A (en) * 1998-10-23 2000-05-15 김영환 Method of manufacturing dual gate oxide layer
KR20010008436A (en) * 1998-12-30 2001-02-05 김영환 Method for manufacturing hybrid semiconductor device
KR20010111864A (en) * 2000-06-14 2001-12-20 윤종용 Capacitor in dynamic random access memory device and method of manufacturing the same
KR20020038471A (en) * 2000-11-17 2002-05-23 아끼구사 나오유끼 Non-volatile semiconductor memory device and fabrication method of the same

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