JPH0945875A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device having a TEG which is capable of measuring the characteristics of a storage node electrode of fin structure. SOLUTION: A spacer insulating film is formed on an interlayer insulating film 121, a part of the spacer insulating film is separated from a region where a TEG is predetermined to be formed, and a spacer insulating film is left unremoved on a region where a memory cell array is predetermined to be formed. A node contact hole is formed, a polycrystalline silicon film is formed, and a storage node electrode 128, a polycrystalline silicon film pattern 129ba and the like are formed by patterning the polycrystalline silicon film. The spacer insulating film 122a is removed by isotropic etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a stacked type DRAM having a characteristic measuring element (TEG) and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a DRAM in which a memory cell consists of one MOS transistor and one capacitance element, the occupied area of the memory cell has been gradually reduced as its integration becomes higher. Further, in the DRAM, in order to have resistance to a soft error generated by α particles, it is required that the capacitance element has a capacitance value above a certain value even if the area occupied by the memory cell is reduced. Therefore, it is important how to secure a necessary accumulated charge capacity with a limited occupation area.

This technical problem tends to be solved by devising the shape of the storage node electrode (lower electrode) of the capacitive element three-dimensionally. As a result, the effective opposing area between the cell plate electrode (upper electrode) of the capacitive element and the storage node electrode increases. As one example thereof, there is a so-called fin structure storage node electrode disclosed in Japanese Patent Laid-Open No. 1-270344. In the storage node electrode of this structure, not only the top and side surfaces of this electrode but also the bottom surface face the cell plate electrode via the capacitive insulating film. Further, as the shape of these storage node electrodes becomes three-dimensional, a so-called COB structure (ca) in which a capacitive element is formed above the bit line is formed.
There is a tendency to adopt "acceptor-over-bit-line".

On the other hand, the semiconductor memory device is also provided with a characteristic measuring element (TEG) relating to each component. As a matter of course, the TEG relating to the conductive film forming the storage node electrode is required. These TEGs are used for measuring the misalignment between the node contact hole and the storage node electrode, measuring the sheet resistance of this conductor film, or checking the short circuit between two adjacent storage node electrodes. Is required.

FIG. 12, which is a schematic plan view of a DRAM, and D
13 is a partially enlarged plan schematic view of the RAM, FIG. 14 is a schematic sectional view taken along the line AA in FIG. 12, and a schematic sectional view taken along the line BB, CC line, DD line and EE line in FIG. Referring also to FIG. 15, which is a COB structure having a TEG relating to a conductor film forming a storage node electrode and having a stacked storage node electrode having a fin structure based on the above publication. Conventional DRA
M is as follows.

A memory cell array 302 is provided on a P-type silicon substrate 301. The memory cell array 302 includes memory cells 303 arranged in a matrix.
And is driven by peripheral circuits such as an X decoder 304 and a Y decoder 304. Furthermore, a P-type silicon substrate 30
1 is provided with TEGs 307A, 307B, 307C and the like [FIG. 12].

The memory cell 303 consists of one MOS transistor and one capacitive element. In one MOS transistor, the word line 313 provided on the P-type silicon substrate 301 via the gate oxide film 312 is used as a gate electrode, and the N-type source / drain regions 314A and 314B provided on the surface of the P-type silicon substrate 301. have. Each MOS transistor is isolated by a field oxide film 311 provided on the surface of the P-type silicon substrate 301. The word line 313 is connected to the X decoder 304. MOS transistors are
It is covered with a silicon oxide film 315, a (first) interlayer insulating film 316. Bit line 318 provided on interlayer insulating film 316 via bit contact hole 317 penetrating interlayer insulating film 316 and silicon oxide film 315.
Are connected to the N-type source / drain region 314A. Further, these bit lines 318 are connected to the Y decoder 30.
5 [FIG. 12, FIG. 13 (a), FIG. 14,
FIG. 15 (a)].

The interlayer insulating film 316 is covered with a (second) interlayer insulating film 321. At least the upper surface of the interlayer insulating film 321 is made of, for example, a silicon nitride film. The storage element provided on the interlayer insulating film 321 includes a storage node electrode 328 made of (a pattern of) an N-type polycrystalline silicon film, a capacitance insulating film 331, and a cell plate made of, for example, an N-type polycrystalline silicon film. It is composed of an electrode 332. Node contact hole 32 penetrating the interlayer insulating film 321, the interlayer insulating film 316, and the silicon oxide film 315.
The storage node electrode 328 is connected to the N-type source / drain region 314B through 5A. The bottom surfaces of these storage node electrodes 328 and the upper surface of the interlayer insulating film 321 (except for the portion of the node contact holes 325A) do not directly contact (due to the fin structure), and voids with a predetermined interval are formed. Has been formed. This space is narrower than the space between two adjacent storage node electrodes 328. These voids are filled with the capacitive insulating film 331 and the cell plate electrode 332.
2, FIG. 13 (a), FIG. 14 and FIG. 15 (b)].

The TEG 307A is a TEG for measuring the positional deviation between the node contact hole 325A and the storage node electrode 328, and a plurality of contact holes 325 formed at the same time as the node contact hole 325A.
B and the storage node electrode 328 and a plurality of polycrystalline silicon film patterns 329a in the same layer. Contact hole 325B and polycrystalline silicon film pattern 329a
Are arranged with a required interval. The contact hole 325B has an interlayer insulating film 321 and an interlayer insulating film 31.
6, silicon oxide film 315 and field oxide film 31
Although it penetrates 1 to reach the surface of the P-type silicon substrate 301, the bottom of the contact hole 325B may be in the field oxide film 311 in some cases. The size of the contact hole 325B is sufficiently larger than the size of the node contact hole 325A, the design value of the length of the short side of the contact hole 325B matches the width of the storage node electrode 328, and the length of the long side of the contact hole 325B. The length is sufficiently longer than the length of the storage node electrode 328. The width of the polycrystalline silicon film pattern 329 a matches the width of the storage node electrode 328, and the polycrystalline silicon film pattern 329 a
The length of a matches the length of the long side of the contact hole 325B [FIG. 12, FIG. 13 (b), FIG. 14].

The TEG 307B is a TEG for measuring the sheet resistance of the polycrystalline silicon film forming the storage node electrode 328.
28, and is composed of, for example, polycrystalline silicon film patterns 329ba, 329bb, 329bc of three kinds of widths in the same layer. Polycrystalline silicon film pattern 329ba, 329
At both ends of bb and 329bc, probe pads made of a polycrystalline silicon film pattern of several tens of μm square are provided. The width of the polycrystalline silicon film pattern 329ba matches the width of the storage node electrode 328. The widths of the polycrystalline silicon films 329bb and 329bc are, for example, twice or four times the width of the storage node electrode 328. The sheet resistance is preferably measured before forming the capacitive insulating film 331 (immediately after forming the storage node electrode 328 and the like) [FIG. 12, FIG. 13 (c),
FIG. 15 (c)].

The TEG 307C is a TEG for checking a short circuit between the storage node electrodes 328,
N-type diffusion layer 314C formed simultaneously with N-type source / drain regions 314A and 314B and a plurality of contact holes 325 formed simultaneously with node contact holes 325A.
C and storage node electrode 328 and polycrystalline silicon film patterns 329ca and 329cb in the same layer. Polycrystalline silicon film pattern 329ca, 329
The width of cb is wider than the width of the storage node electrode 328, and the distance between the polycrystalline silicon film pattern 329ca and the polycrystalline silicon film pattern 329cb is equal to the distance between two adjacent storage node electrodes 328. The lengths of the polycrystalline silicon film patterns 329ca and 329cb are sufficiently long and may be set in the order of 1 mm. The size of the contact hole 325C is equal to the size of the storage node electrode 328. For the purpose of the TEG 307C, it is preferable that the polycrystalline silicon film pattern 329cb is also connected to the N-type diffusion layer through the contact hole. With such a structure, whether the short-circuit check between the N-type diffusion layers or the storage node is performed. It is difficult to distinguish whether it is a short circuit check between the electrodes 328. The short circuit check between the storage node electrodes 328 is also performed before forming the capacitance insulating film 331 (immediately after the storage node electrodes 328 and the like are formed) [FIG. 12, FIG. 13 (d), FIG. 15].
(D)].

Referring to FIGS. 12 to 15 and FIGS. 16 and 17 which are schematic sectional views of the manufacturing process along the line FF in FIG. 12, the conventional DRAM described above is formed as follows.

First, a field oxide film 311 is formed in the element isolation region on the surface of the P-type silicon substrate 301, and a gate oxide film 312 is formed in the element formation region. After forming the word line 313 that also serves as a gate electrode, an N-type source is formed in the area where the memory cell array 302 is to be formed in the element forming area.
The drain regions 314A and 314B are formed, and the N-type diffusion layer 314C is formed in the TEG307C formation planned region of the element formation region. After forming a silicon oxide film (HTO film) 315 by high temperature vapor deposition on the entire surface, for example, BP
An interlayer insulating film 316 is formed by depositing an SG film, reflow, depositing a silicon oxide film, and the like. Next, by a known photolithography process, the interlayer insulating film 316 and the silicon oxide film 315 are sequentially etched to reach the N-type source / drain regions 314A and the bit contact holes 317.
Then, the bit line 318 is formed on the interlayer insulating film 316. For example, the interlayer insulating film 321 is formed by depositing a BPSG film, reflow, depositing a silicon nitride film, or the like. Further, a spacer insulating film 322 made of a PSG film having a predetermined thickness is formed on the entire surface [FIGS. 12 to 15 and 16 (a)].

Next, the spacer insulating film 322, the interlayer insulating film 321, and the interlayer insulating film 3 are formed in the region where the memory cell array 302 is to be formed by a known photolithography process.
16 and the silicon oxide film 315 are sequentially etched to form a node contact hole 325A reaching the N-type source / drain region 314B, and a spacer insulating film 322, an interlayer insulating film 321, and a region where the TEG 307B is to be formed.
The interlayer insulating film 316, the silicon oxide film 315, and the field oxide film 311 are sequentially etched to form a contact hole 325B reaching the P-type silicon substrate 301.
In the region where G307C is to be formed, the spacer insulating film 322,
The interlayer insulating film 321, the interlayer insulating film 316, and the silicon oxide film 315 are sequentially etched to form a contact hole 325C reaching the N-type diffusion layer 314C [FIGS.
5, FIG. 16 (b)].

Next, an N-type polycrystalline silicon film 327 having a required film thickness is formed on the entire surface [FIG. 16 (c)]. Next, the polycrystalline silicon film 32 is formed by a known photolithography process.
7 is patterned to form the storage node electrode 32.
8, polycrystalline silicon film patterns 329a, 329ba,
329bb, 329bc, 329ca, 329cb and the like are formed [FIGS. 12 to 15 and FIG. 17 (a)]. continue,
The spacer insulating film 322 is removed by, for example, isotropic wet etching with diluted hydrofluoric acid [FIGS.
5, FIG. 17 (b)]. After that, for example, a capacitor insulating film 331 including a silicon nitride film, a cell plate electrode 332 including an N-type polycrystalline silicon film, and the like are formed,
A DRAM having a desired TEG can be obtained [FIGS. 12 to 15].

[0016]

In the conventional DRAM described above, the polycrystalline silicon film 32 (which is a conductor film) in the same layer is used.
7, the storage node electrode 328 (which is the first conductor film pattern) and the polycrystalline silicon film pattern 32 which constitutes the TEG (which is the second conductor film pattern) 32
After forming 9a and the like, the spacer insulating film 322 is removed by isotropic etching.

When the spacer insulating film 322 is removed by isotropic etching, a polycrystalline silicon film pattern 329 is formed.
In the polycrystalline silicon film pattern having a narrow width such as ba or 329bb, the spacer insulating film 322 immediately below is completely removed. Incidentally, these polycrystalline silicon film patterns 329b
At the pad portions provided at both ends of a and 329bb (the width of these pads is sufficiently wide), the spacer insulating film remains except for the pad peripheral portion. Similarly, except for the peripheral portions, respectively, the spacer insulating film 323b remains just below the polycrystalline silicon film pattern 329bc, and the spacer insulating film 323c remains just below the polycrystalline silicon film patterns 329ca and 329cb. In a narrow pattern such as the polycrystalline silicon film pattern 329ba, a complete lacking portion 339 occurs. Polycrystalline silicon film pattern 329b
In the case where the width is wide to some extent as shown in b, or the contact hole 325A like the polycrystalline silicon film pattern 329a.
In the case of the pattern connected to the P-type silicon substrate 301 via, the occurrence of complete missing portions is somewhat reduced. However, the polycrystalline silicon film patterns 329a, 32
Also in 9bb, 329bc, 329ca, and 329cb, it is difficult to prevent partial omission in the peripheral portion of these patterns. Except for these missing portions, a polysilicon film of the same layer as the cell plate electrode 332 is formed between the bottom surface of the polysilicon film pattern 329a and the top surface of the interlayer insulation film 321 via the capacitor insulation film 331. 332a remains, and the polycrystalline silicon film pattern 329b
The polycrystalline silicon film 332b is left between the bottom surfaces of the b and 329bc and the upper surface of the interlayer insulating film 321, and the polycrystalline silicon film 332b is left between the bottom surfaces of the polycrystalline silicon film patterns 329ca and 329cb and the upper surface of the interlayer insulating film 321 respectively. The polycrystalline silicon film 332c remains (see FIGS. 14, 15C, 15D, and 17B).

Based on the events described above, the problems of the present invention are as follows.

First, the first problem is that the TEG (particularly the sheet resistance measuring TEG, the short circuit checking TEG) itself does not function sufficiently. In the conductor film pattern (for example, the polycrystalline silicon film pattern 329ba) of the TEG for measuring the sheet resistance (for example, TEG307B), the sheet resistance cannot be measured if a complete missing portion occurs. Further, when a partial dropout occurs, the measured sheet resistance value becomes higher than the actual sheet resistance value. In addition, a TEG for checking a short circuit (for example, TEG307
If a partial loss in C) occurs, the data will be shifted in the direction that is not short-circuited.

The second problem is a problem caused by redeposition of a conductor film piece (for example, a polycrystalline silicon piece) due to the above-mentioned lack. These conductor film pieces are
It also occurs from. These conductive film pieces tend to adhere between the storage node electrodes to easily cause a short circuit in the memory cell. In addition, these conductor film pieces are T
The same is true when it is attached between two conductor film patterns of EG (for example, TEG307C).

Therefore, the object of the present invention is to
It has a TEG relating to the conductor film that constitutes the node electrode,
In a DRAM having a COB structure, a fin structure, and a stacked type storage node electrode, a D having a structure in which a TEG functions sufficiently and a short circuit between memory cells is less likely to occur.
A RAM and a manufacturing method thereof are provided.

[0022]

In the semiconductor memory device of the present invention, a gate electrode also serving as a word line is provided on a P-type silicon substrate via a gate oxide film and a surface of the P-type silicon substrate. 1 from one MOS transistor composed of N-type source / drain regions and one stacked capacitive element composed of a storage node electrode including a first conductor film pattern, a capacitive insulating film and a cell plate electrode On the P-type silicon substrate, an element dedicated to characteristic measurement is formed on which two memory cells are formed and which further includes a second conductor film pattern in the same layer as the conductor film forming the first conductor film pattern. A semiconductor memory device provided, wherein a node contact hole that covers the surface of the MOS transistor and reaches one of the N-type source / drain regions is provided. And a bit line connected to one of the N-type source / drain regions through the node contact hole is provided on the first interlayer insulating film. The bit line and the first interlayer insulating film are covered with a second interlayer insulating film having at least an upper surface made of a silicon oxide film or a silicon nitride film,
The storage node electrode is connected to the other of the N-type source / drain regions through a node contact hole provided through the second and first interlayer insulating films, and the bottom surface of the storage node electrode is connected. And an upper surface of the second interlayer insulating film, a void portion having a distance smaller than a distance between two adjacent storage node electrodes is provided, and the second conductor film pattern has the second interlayer insulating film. It is provided in direct contact with the upper surface of the insulating film.

Preferably, conductor film spacers are provided on the side surfaces of the first and second conductor film patterns, respectively. Further, at least one of the second conductor film patterns is provided on the front surface of the former type silicon substrate through a contact hole provided through the second and first interlayer insulating films. It is connected to the mold diffusion layer.

First Method of Manufacturing Semiconductor Memory Device of the Present Invention
In this mode, a field oxide film is formed in an element isolation region on the surface of a P-type silicon substrate, a gate oxide film is formed in an element formation region, and a gate electrode also serving as a word line is formed. An N-type source / drain region is formed in the memory cell array formation planned region, and at least one N-type diffusion layer is formed in the device-dedicated device-dedicated region for characteristic measurement of these device formation regions, and the first interlayer is formed on the entire surface. An insulating film is formed, a bit contact hole reaching one of the N-type source / drain regions is formed in the first interlayer insulating film, and the N-type source / drain is formed through the bit-contact hole. Forming a bit line connected to one of the regions, and covering at least the bit line and the first interlayer insulating film, at least the upper surface of which is a silicon oxide film or a silicon nitride film. A step of forming a second interlayer insulating film made of a film on the entire surface, and a step of forming a spacer insulating film covering the second interlayer insulating film and having a predetermined film thickness and made of a PSG film or a BPSG film. , Selectively removing the spacer insulating film in the region for forming the element dedicated to characteristic measurement,
A step of leaving the spacer insulating film in the memory cell array formation planned region; and a step of penetrating the spacer insulating film, the second interlayer insulating film and the first interlayer insulating film to form the N-type source / drain region. A step of forming a node contact hole reaching the other and forming a contact hole penetrating the second interlayer insulating film and the first interlayer insulating film and reaching at least the N-type diffusion layer, and a conductor film on the entire surface. And patterning this conductor film to form a storage node electrode made of a first conductor film pattern connected to the other of the N-type source / drain regions through the node contact hole. At least 1
A step of forming a second conductor film pattern connected to the N-type diffusion layer through the contact hole, and a step of selectively removing the remaining spacer insulating film by isotropic etching. Forming a capacitance insulating film, and further forming a cell plate electrode.

Preferably, the upper surface of the second interlayer insulating film is flattened by the chemical mechanical polishing method. More preferably, the upper surface of the second interlayer insulating film is made of a silicon oxide film, the conductor film is made of a polycrystalline silicon film, and the capacitive insulating film is formed by vapor phase growth of a silicon nitride film and this nitriding. When the surface of the silicon film is thermally oxidized, the silicon nitride film is formed on the entire surface after forming the first and second conductor film patterns, and the silicon nitride film in the region for forming the element for exclusive use in characteristic measurement is formed. Selectively remove,
Perform thermal oxidation.

Second Method of Manufacturing Semiconductor Memory Device of the Present Invention
In this mode, a field oxide film is formed in an element isolation region on the surface of a P-type silicon substrate, a gate oxide film is formed in an element formation region, and a gate electrode also serving as a word line is formed. An N-type source / drain region is formed in the memory cell array formation planned region, and at least one N-type diffusion layer is formed in the device-dedicated device-dedicated region for characteristic measurement of these device formation regions, and the first interlayer is formed on the entire surface. An insulating film is formed, a bit contact hole reaching one of the N-type source / drain regions is formed in the first interlayer insulating film, and the N-type source / drain is formed through the bit-contact hole. Forming a bit line connected to one of the regions, and covering at least the bit line and the first interlayer insulating film, at least the upper surface of which is a silicon oxide film or a silicon nitride film. A step of forming a second interlayer insulating film made of a film, and forming a first spacer insulating film of a PSG film or a BPSG film that covers the second interlayer insulating film and has a predetermined film thickness. And a step of selectively removing the first spacer insulating film in the characteristic measurement dedicated element formation scheduled region and leaving the first spacer insulating film in the memory cell array formation scheduled region. First above
Forming a node contact hole penetrating the spacer insulating film, the second interlayer insulating film, and the first interlayer insulating film to reach the other of the N-type source / drain regions. A step of forming a contact hole penetrating at least the N-type diffusion layer through the first interlayer insulating film, and a second spacer insulating film formed of a PSG film or a BPSG film by forming a first conductor film on the entire surface. And the second spacer insulating film and the first conductor film are sequentially patterned, and the upper surface is connected to the other of the N-type source / drain regions through the node / contact hole. A first conductor film pattern covered with a second spacer insulating film, and at least one of them is connected to the N-type diffusion layer through the contact hole so that the upper surface of the second spacer insulating film is not exposed. A step of forming a second conductor film pattern covered with the film, a second conductor film is formed on the entire surface, and the second conductor film is etched back to form the first and second conductor films. A step of leaving a conductor film spacer on the side surface of the conductor film pattern, and the second spacer insulating film and the memory cell that cover the upper surfaces of the first and second conductor film patterns by isotropic etching. -Selectively removing the first spacer insulating film remaining in the array formation region to form a storage node electrode composed of the first conductive film pattern and the conductive film spacer. A step of processing into a state in which the conductor film spacers are connected to the side surfaces of these second conductor film spacers;
Forming a capacitive insulating film, and further forming a cell plate electrode.

Preferably, the upper surface of the second interlayer insulating film is flattened by the chemical mechanical polishing method. More preferably, the upper surface of the second interlayer insulating film is made of a silicon oxide film, the first and second conductor films are made of a polycrystalline silicon film, and the formation of the capacitive insulating film is made of a silicon nitride film. When consisting of vapor phase growth and thermal oxidation of the surface of the silicon nitride film, the first and second conductor film patterns are formed to form the conductor film spacer, and then the silicon nitride film is formed on the entire surface. Then, the silicon nitride film in the region for forming the element for exclusive use in characteristic measurement is selectively removed, and thermal oxidation is performed.

[0028]

Next, the present invention will be described with reference to the drawings.

FIG. 1 which is a schematic plan view of a DRAM and DR
2 which is a partially enlarged plan schematic view of AM, FIG. 3 which is a schematic sectional view taken along the line AA of FIG. 1, and BB line, C of FIG.
Referring to FIG. 4 which is a schematic sectional view taken along line C, DD and EE, the DRAM of the first embodiment of the present invention will be described.
Is a conventional DRAM having a COB structure having a TEG relating to a conductive film forming a storage node electrode and having a fin type stacked storage node electrode, which is as follows.

A memory cell array 102 is provided on the P-type silicon substrate 101. The memory cell array 102 includes memory cells 103 arranged in a matrix.
And is driven by peripheral circuits such as the X decoder 104 and the Y decoder 104. Furthermore, a P-type silicon substrate 10
1, TEGs 107A, 107B, 107C and the like are provided [FIG. 1].

The memory cell 103 consists of one MOS transistor and one capacitive element. Memory cell 1
The cell size of 03 is 0.9 μm × 1.8 μm.
In one MOS transistor, the word line 113 provided on the P-type silicon substrate 101 via the gate oxide film 112 having a film thickness of about 10 nm is used as the gate electrode, and the N-type source provided on the surface of the P-type silicon substrate 101. It has drain regions 114A and 114B. The gate length and gate width of this MOS transistor are 0.4 μm,
It is 0.5 μm. The word line 113 is a tungsten layer formed by stacking a tungsten silicide film having a thickness of about 100 nm on an N-type polycrystalline silicon film having a thickness of about 100 nm.
It consists of a polycide film. N-type source / drain region 11
4A and 114B each have an LDD structure, and the depth of their junction is about 0.15 μm. Each MO
The S transistor is isolated by a field oxide film 111 having a film thickness of about 300 nm provided on the surface of the P-type silicon substrate 101. The word line 113 is connected to the X decoder 104.

The MOS transistor is a (first) interlayer insulating film 1 made of a silicon oxide film 115 having a thickness of about 100 nm and a reflowed BPSG film having a thickness of about 300 nm.
16. The silicon oxide film 115 is provided to prevent boron from the interlayer insulating film 116 from diffusing into the N-type source / drain regions 114A and 114B. The bit line 118 provided on the interlayer insulating film 116 is connected to the N-type source / drain region 114A through the bit contact hole 117 penetrating the interlayer insulating film 116 and the silicon oxide film 115. bit·
The design size of the contact hole 117 is 0.4 μm □, but the finished size is about 0.2 μm □. The line width of the bit lines 118 is about 0.4 μm, and these bit lines 118 are made of an N-type polycrystalline silicon film having a film thickness of about 150 nm and a tungsten film having a film thickness of about 100 nm.
It is made of a tungsten polycide film in which a silicide film is laminated. Further, these bit lines 118 are connected to the Y decoder 105 [FIG. 1, FIG. 2 (a), FIG.
4 (a)-(b)].

The interlayer insulating film 116 is covered with a (second) interlayer insulating film 121. The inter-layer insulating film 121 is a reflowed BPSG film having a thickness of about 400 nm and a thickness of 10
It is a film in which a silicon nitride film having a thickness of about 0 nm is laminated.
The memory element provided over the interlayer insulating film 121 has a film thickness of 60.
The storage node electrode 128 (which is the first conductor film pattern) and the capacitor insulating film 13 which are (the pattern of) the N-type polycrystalline silicon film (which is the conductor film) of about 0 nm
1 and a cell plate electrode 132 made of an N-type polycrystalline silicon film having a film thickness of about 200 nm. The size of the storage node electrode 128 (in a plane projection) is 0.4 μm × 1.3 μm, and the distance between the two storage node electrodes 128 is 0.5 μm. Interlayer insulating film 121, interlayer insulating film 116 and silicon oxide film 1
The storage node electrode 128 is connected to the N-type source / drain region 114B through a node contact hole 125A penetrating through 15. The design size of the node contact hole 125A is 0.4 μm □, but the finished size is about 0.2 μm □. The bottom surface of these storage node electrodes 128 and the top surface of the interlayer insulating film 121 (excluding the portion of the node contact hole 125A) do not directly contact each other (due to the fin structure), but are not contacted with each other.
Voids are formed at intervals of about 4 μm. This space is narrower than the space between two adjacent storage node electrodes 128. These voids are filled with the capacitive insulating film 131 and the cell plate electrode 132 [Fig. 1, Fig. 2 (a), Fig. 3, Fig. 4 (a)-
(B)].

The TEG 107A is a TEG for measuring the positional deviation between the node contact hole 125A and the storage node electrode 128, and a plurality of contact holes 125 formed simultaneously with the node contact hole 125A.
B and a plurality of polycrystalline silicon film patterns 129a (which are second conductor film patterns) in the same layer as the storage node electrode 128. The contact hole 125B and the polycrystalline silicon film pattern 129a are arranged with a required interval, respectively. The contact holes 125B are formed in the interlayer insulating film 121, the interlayer insulating film 116, and the silicon oxide film 1.
Although it penetrates 15 and the field oxide film 111 and reaches the surface of the P-type silicon substrate 101, the bottom of the contact hole 125B may be in the field oxide film 111 in some cases. Polycrystalline silicon film pattern 129a
In the portion covering the interlayer insulating film 121, the conventional structure (for example, the polycrystalline silicon film pattern 329 in FIG.
(See the shape of a)), the bottom surface of the polycrystalline silicon film pattern 129a is in direct contact with the top surface of the interlayer insulating film 121, and no void is provided between them. The size of the contact hole 125B is sufficiently larger than the size of the node contact hole 125A, and the design value of the length of the short side of the contact hole 125B matches the width (0.4 μm) of the storage node electrode 128. The long side length is the storage node electrode 128
Is sufficiently longer than the length (1.3 μm). The width of the polycrystalline silicon film pattern 129a is equal to the storage node electrode 12
8 and the length of the polycrystalline silicon film pattern 129a matches the length of the long side of the contact hole 125B [FIG. 1, FIG. 2 (b), FIG. 3].

The TEG 107B is a TEG for measuring the sheet resistance of the polycrystalline silicon film forming the storage node electrode 128.
For example, a polycrystalline silicon film pattern 129ba, 1 of the same layer as 28 having three kinds of widths (which is a second conductor film pattern)
It is composed of 29bb and 129bc. At both ends of the polycrystalline silicon film patterns 129ba, 129bb, 129bc, probe pads made of a polycrystalline silicon film pattern of several tens of μm square are provided. The width of the polycrystalline silicon film pattern 129ba matches the width of the storage node electrode 128. Polycrystalline silicon film 12
The widths of 9bb and 129bc are, for example, twice or four times the width of the storage node electrode 128. The polycrystalline silicon film patterns 129ba, 129bb, 129bc are also different from the conventional structure (for example, refer to the shapes of the polycrystalline silicon film patterns 329ba, 329bb, 329bc in FIG. 15C), and their bottom surfaces are also different from each other. It is in direct contact with the upper surface of the insulating film 121, and no void is provided between them. It is preferable to measure the sheet resistance before forming the capacitive insulating film 131 (immediately after the storage node electrode 128 and the like are formed) [FIG. 1, FIG. 2 (c), FIG. 4 (c)].

The TEG 107C is a TEG for checking a short circuit between the storage node electrodes 128,
N-type diffusion layer 114C formed simultaneously with N-type source / drain regions 114A and 114B and a plurality of contact holes 125 formed simultaneously with node contact holes 125A.
Polycrystalline silicon film pattern 12 (which is the second conductor film pattern) in the same layer as C and the storage node electrode 128
9ca and 129cb. The widths of the polycrystalline silicon film patterns 129ca and 129cb are wider than the width of the storage node electrode 128, and the distance between the polycrystalline silicon film pattern 129ca and the polycrystalline silicon film pattern 129cb is two adjacent storage node electrodes 128. Equal to the interval. The lengths of the polycrystalline silicon film patterns 129ca and 129cb are sufficiently long and 1 m.
It may be set to m. The polycrystalline silicon film patterns 129ca and 129cb also have a conventional structure (for example,
Polycrystalline silicon film pattern 329 in FIG.
(See the shapes of ca and 329cb), their bottom surfaces are also in direct contact with the top surface of the interlayer insulating film 121, and no void is provided between them. The size of the contact hole 125C is equal to the size of the storage node electrode 128. For the purpose of the TEG 107C, it is preferable that the polycrystalline silicon film pattern 129cb is also connected to the N-type diffusion layer through the contact hole. With such a structure, whether the short-circuit check between the N-type diffusion layers or the storage node is performed. It cannot be distinguished whether it is a short circuit check between the electrodes 128. The short circuit check between the storage node electrodes 128 is also performed before the formation of the capacitive insulating film 131 (immediately after the storage node electrodes 128 and the like are formed) [FIG. 1, FIG. 2 (d), FIG. 4].
(D)].

Referring to FIGS. 1 to 4 and FIGS. 5 and 6 which are schematic sectional views of the manufacturing process along the line FF in FIG. 1, the DRAM of the first embodiment is as follows. It is formed.

First, a LOCOS type field oxide film 111 having a film thickness of about 30 nm is formed in an element isolation region on the surface of a P-type silicon substrate 101, and a gate oxide film 112 having a film thickness of about 10 nm is formed in the element formation region by thermal oxidation. Form.
A N-type polycrystalline silicon film having a film thickness of about 100 nm and a tungsten silicide film having a film thickness of about 100 nm are sequentially formed on the entire surface, and then the laminated film is patterned by a known photolithography technique to form a word which also serves as a gate electrode. Form line 113. Phosphorus ion implantation, word line 113
N-type source / drain regions 114A and 114B are formed in the region where the memory cell array 102 is to be formed in the element forming region by forming a silicon oxide film spacer (not shown) on the side surface and implanting arsenic ions. The N-type diffusion layer 1 is formed in the TEG107C formation planned region of the element formation region.
Form 14C. Silane (Si with good step coverage
H ₄ ) and nitrous oxide (N ₂ O) used as source gases 800
Film thickness 1 by low pressure vapor deposition (LPCVD) at about ℃
After a silicon oxide film (HTO film) 115 having a thickness of about 00 nm is formed on the entire surface, an interlayer insulating film 116 is formed by depositing a BPSG film having a thickness of about 300 nm and reflowing. B
The PSG film is deposited by LPCVD or TEO using TEOS, phosphine (PH ₃ ), trimethyl borate (B (OCH ₃ ) ₃ ) and oxygen (O ₂ ) as source gases.
S and tri-methyl phosphite (P (OCH ₃ ) ₃ )
And tri-methyl borate (or tri-ethyl borate (B (OC ₂ H ₅ ) ₃ ) and ozone (O ₃ ) are used as source gases by atmospheric pressure vapor deposition (APCVD). Reflow is 750 ℃ -900 ℃
Is performed in the temperature range of. In addition, instead of the BPSG film, P
An SG film may be used.

Next, tetra fluoro methane (C
Bit contact hole 117 reaching N type source / drain region 114A by sequentially etching interlayer insulating film 116 and silicon oxide film 115 by a known photolithography process such as RIE using F ₄ ) as an etching gas.
To form After that, (not shown) 10 on the entire surface
This HT is formed by forming an HTO film of 0 nm to 150 nm.
Etch back the O film and bit contact hole 117
A silicon oxide film spacer is formed on the side surface of. An N-type polycrystalline silicon film having a film thickness of about 150 nm and a film thickness of 10
After a tungsten silicide film having a thickness of about 0 nm is sequentially formed, this laminated film is patterned by a known photolithography technique to form a bit line 118 on the interlayer insulating film 116. Deposition and reflow of a BPSG film (or PSG film) with a film thickness of about 400 nm and film thickness 10
The interlayer insulating film 121 is formed by depositing a silicon nitride film having a thickness of about 0 nm. The deposition of this silicon nitride film
Chlorine silane (SiH ₂ Cl ₂ ) and ammonia (NH
₃ ) by LPCVD using and as source gases. A silicon oxide film (NSG film) formed by APCVD may be used instead of the silicon nitride film. Further, a spacer insulating film 122 made of a PSG film (so-called BPSG film) having a film thickness of about 400 nm is formed on the entire surface [FIGS. 1 to 4 and 5 (a)].

Next, the area where the memory cell array 102 is to be formed is covered, and at least the TEGs 107A, 107 are formed.
Octafluorocyclobutane (C ₄ F ₈ ) (or trifluoromethane (CHF ₃ )) using a photoresist film (not shown) having an opening in the region where B and 107C are to be formed as a mask. The spacer insulating film 122 is removed by etching by RIE using an etching gas in which carbon monoxide (CO) is added. At this time, the spacer insulating film 122a is left at least in the region where the memory cell array 102 is to be formed. When the upper surface of the interlayer insulating film 121 is formed of an NSG film, buffered hydrofluoric acid (HF: NH ₄ F having a ratio of about 1:30 is preferably used) using the photoresist film as a mask. It is possible to use anisotropic wet etching. Next, in the region where the memory cell array 102 is to be formed (by the same method as that for forming the bit contact hole 117), the spacer insulating film 122a and the interlayer insulating film 12 are formed.
1, the interlayer insulating film 116 and the silicon oxide film 115 are sequentially etched to form a node contact hole 125A reaching the N-type source / drain region 114B.
In the area where 107B is to be formed, the P-type silicon substrate 10 is formed by sequentially etching the interlayer insulating film 121, the interlayer insulating film 116, the silicon oxide film 115, and the field oxide film 111.
1 to form the contact hole 125B, the TEG10
In the region where 7C is to be formed, the interlayer insulating film 121, the interlayer insulating film 116, and the silicon oxide film 115 are sequentially etched to form a contact hole 125C reaching the N-type diffusion layer 114C. Thereafter, similar to the bit contact hole 117, the node contact hole 125A and the contact hole 12 are formed.
Silicon oxide film spacers are formed on the side surfaces of 5B and 125C [FIGS. 1 to 4 and 5 (b)].

Next, silane (or disilane (Si
LPCVD using ₂ H ₆ )) and phosphine as source gases
Thus, an N-type polycrystalline silicon film 127 having a film thickness of about 600 nm is formed on the entire surface. This polycrystalline silicon film 127
Has an impurity concentration of about 1.5 × 10 ²⁰ cm ⁻³ [FIG. 5 (c)]. Next, the polycrystalline silicon film 127 is patterned by RIE using hydrogen bromide (HBr) or the like as an etching gas, and the storage node electrode 12 is formed.
8, polycrystalline silicon film patterns 129a, 129ba,
129bb, 129bc, 129ca, 129cb and the like are formed [FIGS. 1 to 4 and 5 (c)]. Subsequently, the spacer insulating film 122a is removed by, for example, isotropic wet etching with diluted hydrofluoric acid [FIGS. 1 to 4 and 6].
(A)]. Instead of the polycrystalline silicon film 127, i
An N-type amorphous silicon film may be formed by n-situ. In this case, considering the measurement of the sheet resistance of the storage node electrode 128, it is sufficient to pattern this film to form an amorphous silicon film pattern.
Before forming the capacitive insulating film 131, it is preferable to convert into a polycrystalline silicon film pattern. Furthermore, the conductor film forming the storage node electrode 128 and the like is replaced by a polycrystalline silicon film (or an amorphous silicon film),
A refractory metal film such as a tungsten film, a refractory metal silicide film such as a tungsten / silicide film, or a titanium nitride film may be used.

Subsequently, a silicon nitride film having a film thickness of about 7 nm is formed on the entire surface, and pyrogenic oxidation is further performed in a steam atmosphere at about 800 ° C. to 00 ° C. to obtain a silicon oxide film-converted film thickness of about 5 nm (silicon nitride film). A capacitive insulating film 131 (having a structure in which a silicon oxide film is laminated on the film) is formed. Note that the capacitive insulating film 131 is not limited to this composition structure, and a tantalum oxide (Ta ₂ O ₅ ) film may be used, for example. Then, a film having a thickness of 2 is formed by the same method as that for forming the polycrystalline silicon film 127.
An N-type polycrystalline silicon film of about 00 nm is formed on the entire surface, and this film is patterned to form the cell plate electrode 13
2 is formed [FIGS. 1 to 4]. The conductor film forming the cell plate electrode 132 is not limited to the above-mentioned polycrystalline silicon film, but may be formed in-situ with N.
A film having excellent step coverage such as a type amorphous silicon film or a titanium nitride film may be used. However, the capacitance insulating film 13
When 1 is a tantalum oxide film, the storage node electrode 128 is preferably formed of a refractory metal film or a titanium nitride film, and the cell plate electrode 132 is preferably formed of a titanium nitride film. After that, the DRAM according to the present embodiment is completed through further known manufacturing steps.

In the first embodiment described above, the node contact hole 125A (and the contact holes 125B, 125) is formed.
C) and the storage node electrode 128 (which is the first conductor film pattern) and the second (which constitutes the TEG)
Prior to the formation of the polycrystalline silicon film 127 (which is the conductor film) that constitutes the polycrystalline silicon film pattern 129a (which is the conductor film pattern of FIG. 4), the interlayer insulating film 121 (which is the second interlayer insulating film) Of the spacer insulating film 122 formed above, the portion formed in the region where the TEG 107A or the like is to be formed is removed. Therefore, the bottom surface of the polycrystalline silicon film pattern 129a (which is the second conductor film pattern forming the TEG) or the like has a state of being in direct contact with the upper surface of the interlayer insulating film 121. After the formation of the pattern 129a and the like, the occurrence of the loss of the polycrystalline silicon film pattern 129a and the like is suppressed. As a result, TEG107A, 10
The functions of 7B, 107C, etc. can be fully achieved. Further, the occurrence of a short circuit defect between the memory cells due to the polycrystalline silicon piece (conductor film piece) due to the lack of the polycrystalline silicon film pattern 129a or the like is significantly suppressed.

Referring to FIG. 7 which is a schematic sectional view of the manufacturing process of the DRAM, there is an application example of the first embodiment as described below. In this application example, the upper surface of the second interlayer insulating film is made of a silicon oxide film, and the conductor film forming the storage node electrode or the like is made of a polycrystalline silicon film.
Further, it is applied when the formation of the capacitive insulating film comprises vapor phase growth of the silicon nitride film and thermal oxidation of the surface of the silicon nitride film.

First, by the same method as in the first embodiment, up to the bit line is formed, and then the (second) interlayer insulating film 121a whose upper surface is an NSG film is formed. Similar to the first embodiment, a spacer insulating film that covers the interlayer insulating film 121a is formed. At least TEG107
The spacer insulating film in the regions where A, 107B and 107C are to be formed is removed by etching, leaving the spacer insulating film 122a at least in the region where the memory cell array 102 is to be formed.
25B and 125C are formed, and a polycrystalline silicon film (which is a conductor film) is deposited and patterned to form a storage node electrode, a polycrystalline silicon film pattern 129bc, and the like. Similar to the first embodiment, a silicon nitride film 131aa having a film thickness of about 7 nm is formed [FIG. 7 (a)].

Next, the silicon nitride film 131aa in the region where the TEGs 107A, 107B, 107C are to be formed is removed by RIE using an etching gas in which oxygen (O ₂ ) is added to tetrafluoromethane, and the memory cell array 102 is formed. Silicon nitride film 131 in the region where
Let ab remain [FIG. 7 (b)].

Subsequently, the same pyrogenic oxidation as in the first embodiment is performed to form the capacitive insulating film 131a having the same composition structure as in the first embodiment on the memory cell array 10.
It is formed in the area 2 to be formed. By this oxidation, a silicon oxide film 134 having a thickness of 10 nm or more is formed on the surface of the polycrystalline silicon film pattern 129bc or the like [FIG.
(C)].

This application example has the effects of the first embodiment. Further, in this application example, since the surface of the polycrystalline silicon film pattern forming the TEG is covered with the silicon oxide film thicker than the capacitive insulating film when etching the cell plate electrode, the etching gas is selected and the etching is performed. There is an advantage that the degree of freedom with respect to time control and the like is increased.

FIG. 8 which is a schematic plan view of the DRAM, FIG. 9A which is a schematic plan view of the memory cell, and FIG. 9A.
9 (b), (c) and (d) which are schematic cross-sectional views taken along line GG, BB and CC of FIG.
The DRAM of the second embodiment of the present invention is different from that of the first embodiment in the shape of the storage node electrodes and the like and the shape of the first and second interlayer insulating films, and is as follows. There is.

As in the first embodiment, the P-type silicon substrate 201 has memory cells 20 arranged in rows and columns.
3, a memory cell array 202, peripheral circuits such as an X decoder 204 and a Y decoder 204, and a TEG 20.
7A, 207B, 207C, etc. are provided. TE
G207A, 207B, and 207C are between the TEG for measuring the positional deviation between the node contact hole 225A and the storage node electrode 228, the TEG for measuring the sheet resistance of the storage node electrode 228, and the storage node electrode 228, respectively. FIG. 8 is a TEG for measuring the short circuit of [FIG. 8].

The cell size of the memory cell 203 is 0.9 μm × 1.8 μm (as in the first embodiment). In one MOS transistor, the word line 213 provided on the P-type silicon substrate 201 via the gate oxide film 212 having a film thickness of about 10 nm is used as the gate electrode, and the N-type source provided on the surface of the P-type silicon substrate 201. It has drain regions 214A and 214B. The gate length and gate width of this MOS transistor are each 0.4μ.
m, 0.5 μm. The word line 213 also has a film thickness of 100 n
It is composed of a tungsten polycide film in which a tungsten silicide film having a film thickness of about 100 nm is laminated on an N-type polycrystalline silicon film having a film thickness of about m. The junction depth of the N-type source / drain regions 214A and 214B is about 0.15 μm. Each MOS transistor is isolated by a field oxide film 211 having a film thickness of about 300 nm provided on the surface of the P-type silicon substrate 201.

The MOS transistor is covered with a silicon oxide film 215 having a film thickness of about 100 nm and a (first) interlayer insulating film 216 planarized by chemical mechanical polishing (CMP). Interlayer insulating film 216 and silicon oxide film 2
Through the bit contact hole 217 penetrating 15
The bit line 218 provided on the interlayer insulating film 216 is N
It is connected to the mold source / drain region 214A. The finished size of the bit contact hole 217 is 0.
It is about 2 μm □. Bit line 218 has a line width of 0.4μ
and the bit line 218 has a film thickness of 150 n.
It is composed of a tungsten polycide film in which a tungsten silicide film having a film thickness of about 100 nm is laminated on an N-type polycrystalline silicon film having a film thickness of about m. [FIG. 8, FIG. 9 (a), FIG.
(C) to (d)].

The interlayer insulating film 216 is covered with a (second) interlayer insulating film 221. The interlayer insulating film 221 has a film thickness of about 600 nm and a reflowed BPSG film (or PSG film) flattened by CMP to have a film thickness of 10 nm thereon.
It is a film in which a silicon nitride film (or NSG film) of about 0 nm is laminated. The memory element provided on the interlayer insulating film 221 is made of an N-type polycrystalline silicon film (which is a first conductor film) having a film thickness of about 600 nm (a first conductor film pattern) which is a polycrystalline film. Silicon film pattern 227a
And a storage node electrode 228 composed of a polycrystalline silicon film spacer 238 (formed of a second conductor film) provided on these side surfaces, a capacitive insulating film 231, and an N-type polycrystalline film having a thickness of about 100 nm. It is composed of a cell plate electrode 232 made of a silicon film. The polycrystalline silicon film spacer 238 has a width of about 100 nm and a height of about 900 nm. Storage node electrode 2
The size of 28 (in the plane projection) is 0.6 μm × 1.5.
μm, and the distance between the two storage node electrodes 228 is 0.3 μm. A node penetrating the interlayer insulating film 221, the interlayer insulating film 216, and the silicon oxide film 215.
The storage node electrode 228 is connected to the N-type source / drain region 214B through the contact hole 225A. The finished size of the node contact hole 225A is also about 0.2 μm □. These storage
The bottom surface of the node electrode 228 and the top surface of the interlayer insulating film 221 do not directly contact each other (due to the fin structure) and have a thickness of 0.2 μm.
Voids are formed at regular intervals. This space is narrower than the space between two adjacent storage node electrodes 228. These voids are formed by the capacitive insulating film 231.
And the cell plate electrode 232 [FIGS. 8 and 9 (a) to (d)].

In this embodiment, the distance between the storage node electrodes 228 is narrower than that in the first embodiment, so that the presence or absence of a short circuit between the storage node electrodes 228 becomes important. Therefore, referring to FIGS. 10 and 11 which are schematic cross-sectional views of the manufacturing process along the line HH of FIG.
The manufacturing method of the present embodiment will be described while focusing on the formation of 7C.

First, a field oxide film 211 of LOCOS type having a film thickness of about 300 nm is formed in an element isolation region on the surface of a P-type silicon substrate 201, and a gate oxide film 212 having a film thickness of about 10 nm is formed by thermal oxidation in the element formation region. Form. After an N-type polycrystalline silicon film having a film thickness of about 100 nm and a tungsten silicide film having a film thickness of about 100 nm are sequentially formed on the entire surface, this laminated film is patterned to form a word line 313 which also serves as a gate electrode. N-type source / drain regions 214A and 214B are formed in the region where the memory cell array 202 is to be formed in the element forming region, and N is formed in the region where the TEG207C is to be formed in the element forming region.
The type diffusion layer 214C is formed. A silicon oxide film (HTO film) 215 having a film thickness of about 100 nm is formed on the entire surface. After that, a BPSG film or PSG with a film thickness of about 600 nm
Interlayer insulation film 21 by film deposition, reflow and CMP
6 is formed. The gate electrode 213 is the field oxide film 2
The film thickness of the interlayer insulating film 216 is the thinnest in the upper part of 11 and is about 250 nm. N-type source / drain region 21
The film thickness of the interlayer insulating film 216 is thickest at about 600 nm in the portions where 4A and 214B are present. The interlayer insulating film 2
The constituent materials and forming steps of 16 are not limited to this, and a BPSG film or a PSG film may be deposited and reflowed, and then an NSG film may be deposited and CMP may be performed. CMP only may be used.

Then, a bit contact hole 217 reaching the N-type source / drain region 214A is formed by the same method as in the first embodiment, and a film thickness of 150 nm is formed on the entire surface.
After forming an N-type polycrystalline silicon film having a thickness of about 100 nm and a tungsten silicide film having a thickness of about 100 nm in this order, the laminated film is patterned to form a bit line 218 on the interlayer insulating film 216. The BPSG film (or PSG film) with a film thickness of about 600 nm is deposited, reflow and CMP are performed, and the silicon nitride film (or NSG film) with a film thickness of about 100 nm is deposited, etc.
To form The interlayer insulating film 21 at the bit line 218 portion
The film thickness of No. 1 is about 400 nm, and the film thickness of other portions is about 650 nm. The interlayer insulating film 211 is not limited to these constituent materials and forming process, either.
For example, after forming an HTO film of about 100 nm, 500
It is also possible to form an NSG film having a thickness of about nm and perform CMP to further form a silicon nitride film or an NSG film having a thickness of about 100 nm. Next, PS with a film thickness of about 200 nm is formed on the entire surface.
A first spacer insulating film 222 made of a G film (or a BPSG film) is formed [FIGS. 9 and 10 (a)].

Next, the area where the memory cell array 202 is to be formed is covered, and at least the TEGs 207A and 207 are formed.
The (first) spacer insulating film 222 is removed by etching using a photoresist film (not shown) having an opening in the region where B and 207C are to be formed as a mask. At this time, the spacer insulating film 222a is left at least in the region where the memory cell array 202 is to be formed. Next, a node contact hole 125A reaching the N-type source / drain region 114B, a contact hole 225C reaching the N-type diffusion layer 214C, etc. are formed [FIG. 8, FIG. 9, FIG. 10].
(B)].

Then, an N-type polycrystalline silicon film 227 (which is a first conductor film) having a film thickness of about 600 nm is formed on the entire surface by the same method as in the first embodiment. Further, a PSG film (or BPSG) having a film thickness of about 300 nm is used.
A second spacer insulating film 230 made of a film is formed on the entire surface [FIG. 10 (c)].

The spacer insulating film 2 is formed by anisotropic etching.
30, the polycrystalline silicon film 227 is sequentially patterned to form a polycrystalline silicon film pattern 227a (first conductor film pattern), polycrystalline silicon film patterns 229ca and 229cb (second conductor film pattern).
Etc. are formed. A spacer insulating film 230a is left on the upper surfaces of the polycrystalline silicon film pattern 227a and the polycrystalline silicon film patterns 229ca and 229cb. Subsequently, an N-type polycrystalline silicon film 237 (which is a second conductor film) having a film thickness of about 100 nm is formed on the entire surface by the same method as that for forming the polycrystalline silicon film 227 [FIG. ]. The polycrystalline silicon film 237 is etched back by the same RIE as that used for patterning the polycrystalline silicon film 227 to form a polycrystalline silicon film spacer 238 [FIG. 11 (b)].

Subsequently, the spacer insulating films 222a, 222a and 222a are formed by isotropic wet etching using, for example, dilute hydrofluoric acid.
Remove 30a. As a result, the storage node electrode 228 including the polycrystalline silicon film pattern 227a and the polycrystalline silicon film spacer 238 is formed, and at the same time, the polycrystalline silicon film pattern 229ca which is the second conductor film pattern forming the TEG 207C or the like is formed. , 229
The polycrystalline silicon film spacer 238 is also connected to the side surface of cb or the like [FIG. 8, FIG. 9, FIG.
(C)]. In this embodiment, as in the first embodiment, instead of the polycrystalline silicon films 227 and 237, in-
An N-type amorphous silicon film may be formed in situ.
Also in this case, considering the measurement of the sheet resistance of the storage node electrode 228, it is sufficient to pattern this film to form an amorphous silicon film pattern. Conversion to a crystalline silicon film pattern is preferable. Furthermore, as the conductor film forming the storage node electrode 228 and the like and the polysilicon film spacer 238 which is the conductor film spacer, a polysilicon film (or an amorphous silicon film) is used.
Instead of the above, a refractory metal film such as a tungsten film, a refractory metal silicide film such as a tungsten silicide film, or a titanium nitride film may be used.

Then, a silicon nitride film having a film thickness of about 7 nm is formed on the entire surface, and pyrogenic oxidation is performed to obtain a silicon oxide film-equivalent film thickness of about 5 nm (of a structure in which a silicon oxide film is laminated on a silicon nitride film). ) Capacitance insulating film 231
To form As in the first embodiment, the capacitance insulating film 231 is not limited to this composition structure, and a tantalum oxide film may be used, for example. Then, an N-type polycrystalline silicon film having a film thickness of about 100 nm is formed on the entire surface by the same method as that for forming the polycrystalline silicon film 227, and this film is patterned to form a cell plate electrode 232. FIG. 9].
The conductor film forming the cell plate electrode 232 is not limited to the above-mentioned polycrystalline silicon film.
A film excellent in step coverage such as an N-type amorphous silicon film or a titanium nitride film may be used in-situ. Then, after further known manufacturing steps, the DR according to the present embodiment
AM is completed.

The second embodiment also has the effects of the first embodiment. The details are as follows. Formation of node contact hole 225A (and contact hole 225C, etc.) and polycrystalline silicon film pattern 227a (which is the first conductor film pattern that constitutes the storage node electrode) and second conductor (which constitutes the TEG) Prior to the formation of the polycrystalline silicon film 227 (which is the first conductor film) that constitutes the polycrystalline silicon film patterns 229ca and 229cb (which are the film patterns), interlayer insulation (which is the second interlayer insulation film) Of the (first) spacer insulating film 222 formed on the film 221,
The portion formed in the formation planned region such as TEG207C is removed. Therefore, the polycrystalline silicon film pattern 2 (which is the second conductor film pattern forming the TEG)
The bottom surfaces of 29ca, 229cb, etc. are formed so as to be in direct contact with the top surface of the interlayer insulating film 221, and these polycrystalline silicon film patterns 229ca, 22c are formed.
After the formation of 9cb and the like, the occurrence of the loss of these polycrystalline silicon film patterns 229ca, 229cb and the like is suppressed. As a result, the functions of the TEG 207C and the like can be fully achieved. Further, the occurrence of a short circuit defect between the memory cells due to the polycrystalline silicon piece (conductive film piece) due to the lack of the polycrystalline silicon film pattern which is the second conductive film pattern is significantly suppressed.

Further, in this embodiment, a capacitance element having a larger capacitance value than that of the first embodiment can be obtained. Further, since the upper surfaces of the interlayer insulating films 221 and 216 are flattened, the formation of the node contact holes 225A and the like becomes easier than the formation of the node contact holes of the first embodiment.

The flattening of the upper surface of the interlayer insulating film of the second embodiment can be applied to the first embodiment. Furthermore, a storage node electrode having a polycrystalline silicon film spacer can also be applied to the first embodiment.

[0065]

As described above, according to the present invention, prior to the formation of the storage node electrode having the fin structure, the spacer insulating film made of the PSG film or the like formed on the upper surface of the interlayer insulating film is not formed in the region where the TEG is to be formed. By removing and leaving it only in the region where the memory cell array is to be formed, a conductor film is formed and patterned to form the first conductor film pattern and TEG included in the storage node electrode. When the constituent second conductor film pattern is formed, the bottom surface of the second conductor film pattern comes into direct contact with the upper surface of the interlayer insulating film. Therefore, when the remaining spacer insulating film is removed by isotropic etching, it is possible to prevent the second conductive film pattern from being chipped and generating conductive film pieces.

As a result, according to the present invention, the storage
It has a TEG relating to the conductor film that constitutes the node electrode,
In a DRAM having a COB structure, a fin structure, and a stacked type storage node electrode, a D having a structure in which a TEG functions sufficiently and a short circuit between memory cells is less likely to occur.
The RAM and the manufacturing method thereof are obtained.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a first embodiment of the present invention.

FIG. 2 is a partially enlarged schematic plan view of the first embodiment.

FIG. 3 is a schematic sectional view of the first embodiment, and is a schematic sectional view taken along the line AA in FIG.

FIG. 4 is a schematic sectional view of the first embodiment, and is a schematic sectional view taken along line BB, CC line, DD line and EE line of FIG. 2;

5 is a schematic cross-sectional view of the manufacturing process of the first embodiment, which is a schematic cross-sectional view taken along the line FF of FIG.

FIG. 6 is a schematic cross-sectional view of the manufacturing process of the first embodiment, and is a schematic cross-sectional view taken along the line FF of FIG.

FIG. 7 is a schematic sectional view of a manufacturing process for explaining the first application example.

FIG. 8 is a schematic plan view of the second embodiment of the present invention.

FIG. 9 is a schematic plan view and a schematic cross-sectional view of the memory cell of the second embodiment.

10 is a schematic cross-sectional view of the manufacturing process of the second embodiment, which is a schematic cross-sectional view taken along the line HH of FIG.

11 is a schematic cross-sectional view of the manufacturing process of the second embodiment, which is a schematic cross-sectional view taken along the line HH of FIG.

FIG. 12 is a schematic plan view of a conventional DRAM.

FIG. 13 is a partially enlarged plan schematic view of the conventional DRAM.

14 is a schematic cross-sectional view of the conventional DRAM, which is a schematic cross-sectional view taken along the line AA of FIG.

15 is a schematic cross-sectional view of the conventional DRAM, which is a schematic cross-sectional view taken along the line BB, CC, DD and EE in FIG.

16 is a schematic sectional view in the manufacturing process of the conventional DRAM, which is a schematic sectional view taken along the line FF in FIG.

FIG. 17 is a schematic cross-sectional view in the manufacturing process of the conventional DRAM, which is a schematic cross-sectional view taken along the line FF in FIG.

[Explanation of symbols]

101, 201, 301 P-type silicon substrate 102, 202, 302 Memory cell array 103, 203, 303 Memory cell 104, 204, 304 X decoder 105, 205, 305 Y decoder 107A-107C, 207A-207C, 307A ~
307C TEG 111, 211, 311 Field oxide film 112, 212, 312 Gate oxide film 113, 213, 313 Word line 114A, 114B, 214A, 214B, 314A,
314B N-type source / drain region 114C, 214C, 314C N-type diffusion layer 115, 134, 215, 315 Silicon oxide film 116, 121, 121a, 216, 221, 316
321 Interlayer insulating film 117, 217, 317 Bit contact hole 118, 218, 318 Bit line 122, 122a, 222, 222a, 230, 230
a, 322, 323b, 323c Spacer insulating film 125A, 225A, 325A Node contact hole 125B, 125C, 225B, 225C, 325B,
325C contact hole 127,227,237,327,332a-332c
Polycrystalline silicon film 128, 228, 328 Storage node electrode 129a, 129ba, 129bb, 129bc, 12
9ca, 129cb, 227a, 229ca, 229c
b, 329a, 329ba, 329bb, 329bc,
329ca, 329cb Polycrystalline silicon film pattern 131, 131a, 231, 331 Capacitance insulating film 131aa, 131ab Silicon nitride film 238 Polycrystalline silicon film spacer 339 Disappearing part

Claims (9)

[Claims] 1. A MOS transistor comprising a gate electrode provided on a P-type silicon substrate via a gate oxide film and also serving as a word line, and an N-type source / drain region provided on the surface of the P-type silicon substrate. And one stacked-type capacitive element including a storage node electrode including the first conductor film pattern, a capacitive insulating film, and a cell plate electrode, and one memory cell is formed. Is a semiconductor memory device in which a characteristic measurement-dedicated element including a second conductor film pattern in the same layer as a conductor film forming the second conductor film pattern is provided on the P-type silicon substrate. A first interlayer insulating film covering a surface of the transistor and having a node contact hole reaching one of the N-type source / drain regions; A bit line connected to one of the N-type source / drain regions through the node / contact hole is provided on the film, and a second interlayer insulating film having at least an upper surface made of a silicon oxide film or a silicon nitride film. The bit line and the first interlayer insulating film are covered with the storage node electrode through the node contact hole penetrating the second and first interlayer insulating films, and the N-type source is formed. Two adjacent storages connected to the other of the drain regions and between the bottom surface of the storage node electrode and the top surface of the second interlayer insulating film;
A semiconductor memory device having a void portion that is narrower than a distance between the node electrodes, and the second conductor film pattern is provided in direct contact with an upper surface of the second interlayer insulating film. . 2. The semiconductor memory device according to claim 1, wherein a conductor film spacer is provided on each side surface of the first and second conductor film patterns. 3. At least one of the second conductor film patterns is provided on the surface of the P-type silicon substrate through a contact hole provided through the second and first interlayer insulating films. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is connected to the N-type diffusion layer. 4. A field oxide film is formed in an element isolation region on the surface of a P-type silicon substrate, a gate oxide film is formed in an element formation region, and a gate electrode also serving as a word line is formed. N in the memory cell array formation planned area
Type source / drain regions are formed, at least one N-type diffusion layer is formed in a region for element-dedicated characteristic measurement in the element formation region, and a first interlayer insulating film is formed on the entire surface to form the N-type source / drain region. Forming a bit contact hole reaching one of the drain regions in the first interlayer insulating film and forming a bit line connected to one of the N-type source / drain regions through the bit contact hole; Covering the bit line and the first interlayer insulating film, and forming a second interlayer insulating film having at least an upper surface made of a silicon oxide film or a silicon nitride film on the entire surface, and covering the second interlayer insulating film. , Having a predetermined film thickness, PS
A step of forming a spacer insulating film made of a G film or a BPSG film; and a step of selectively removing the spacer insulating film in the characteristic measurement dedicated element formation planned region, and forming the spacer insulating film in the memory cell array formation planned region. And forming a node contact hole penetrating the spacer insulating film, the second interlayer insulating film and the first interlayer insulating film to reach the other of the N-type source / drain regions, and Forming a contact hole penetrating the interlayer insulating film and the first interlayer insulating film of at least the N-type diffusion layer; forming a conductor film on the entire surface; patterning the conductor film;・ N-type source through the contact hole
A second conductor film pattern, which forms a storage node electrode made of a first conductor film pattern connected to the other of the drain regions and at least one of which is connected to the N-type diffusion layer through the contact hole. And a step of selectively removing the remaining spacer insulating film by isotropic etching, a step of forming a capacitive insulating film, and a step of forming a cell plate electrode. Manufacturing method of semiconductor memory device. 5. The method of manufacturing a semiconductor memory device according to claim 4, wherein an upper surface of the second interlayer insulating film is planarized by a chemical mechanical polishing method. 6. The upper surface of the second interlayer insulating film is made of a silicon oxide film, the conductor film is made of a polycrystalline silicon film, and the capacitive insulating film is formed by vapor phase growth of a silicon nitride film and When the surface of the silicon nitride film is thermally oxidized, the silicon nitride film is formed on the entire surface after the first and second conductor film patterns are formed, and the silicon nitride film in the region for forming the element dedicated to characteristic measurement is formed. 6. The method of manufacturing a semiconductor memory device according to claim 4, wherein the film is selectively removed and thermal oxidation is performed. 7. A field oxide film is formed in an element isolation region on the surface of a P-type silicon substrate, a gate oxide film is formed in an element formation region, and a gate electrode which also serves as a word line is formed. N in the memory cell array formation planned area
Type source / drain regions are formed, at least one N-type diffusion layer is formed in a region for element-dedicated characteristic measurement in the element formation region, and a first interlayer insulating film is formed on the entire surface to form the N-type source / drain region. Forming a bit contact hole reaching one of the drain regions in the first interlayer insulating film and forming a bit line connected to one of the N-type source / drain regions through the bit contact hole; Covering the bit line and the first interlayer insulating film, and forming a second interlayer insulating film having at least an upper surface made of a silicon oxide film or a silicon nitride film on the entire surface, and covering the second interlayer insulating film. , Having a predetermined film thickness, PS
A step of forming a first spacer insulating film made of a G film or a BPSG film, and a step of selectively removing the first spacer insulating film in the region for forming a device dedicated to characteristic measurement to form the memory cell array Leaving the first spacer insulating film in the region, and penetrating the first spacer insulating film, the second interlayer insulating film, and the first interlayer insulating film to the other of the N-type source / drain regions. Forming a reaching node contact hole and forming a contact hole penetrating the second interlayer insulating film and the first interlayer insulating film and reaching at least the N-type diffusion layer; and a first conductor on the entire surface. Forming a film, PSG film or BP
A step of forming a second spacer insulating film made of an SG film, patterning the second spacer insulating film and the first conductor film in order, and then the N-type source / drain through the node / contact hole. A first conductor film pattern that is connected to the other of the regions and has an upper surface covered with the second spacer insulating film; and at least one is connected to the N-type diffusion layer through the contact hole and the upper surface is Forming a second conductor film pattern covered with a second spacer insulating film; forming a second conductor film on the entire surface; and etching back the second conductor film to form a second conductor film. A step of leaving a conductor film spacer on the side surfaces of the first and second conductor film patterns; and a second spacer insulating film that covers the upper surfaces of the first and second conductor film patterns by isotropic etching. And the memory cell The first spacer insulating film left in the area where the ray is to be formed is selectively removed to form a storage node electrode composed of the first conductor film pattern and the conductor film spacer, and 2. A semiconductor comprising: a step of processing the second conductive film spacer on a side surface of the conductive film spacer; and a step of forming a capacitive insulating film and further forming a cell plate electrode. Storage device manufacturing method. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein an upper surface of the second interlayer insulating film is planarized by a chemical mechanical polishing method. 9. The upper surface of the second interlayer insulating film is made of a silicon oxide film, the first and second conductor films are made of a polycrystalline silicon film, and the capacitor insulating film is formed of a silicon nitride film. Of vapor phase growth and thermal oxidation of the surface of the silicon nitride film, after forming the first and second conductor film patterns and forming the conductor film spacer,
The silicon nitride film is formed on the entire surface, and the silicon nitride film in the region for forming the characteristic-dedicated element is selectively removed.
9. The method of manufacturing a semiconductor memory device according to claim 7, wherein thermal oxidation is performed.