TWI735860B - Method of manufacturing memory device - Google Patents

Abstract

A method of manufacturing a memory device includes following steps. A first dielectric layer is formed on the substrate between bit-line structures. First trenches are formed in the first dielectric layer. A second dielectric layer is formed to fill in the first trenches. A portion of the first dielectric layer is removed, so that a top surface of the first dielectric layer is lower than a top surface of the second dielectric layer. A first mask layer is formed to cover the top surfaces of the first and second dielectric layers. A first etching process is performed to form second trenches in the first dielectric layer. A third dielectric layer is formed to fill the second trenches. The first dielectric layer is removed to form contact openings between the second and third dielectric layers. A conductive material is formed to fill in the contact openings.

Description

Manufacturing method of memory element

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a memory device.

Dynamic random access memory is a type of volatile memory, which is composed of multiple memory cells. In detail, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other by a word line and a bit line. In order to increase the integration of dynamic random access memory to speed up the operation speed of components, and to meet consumer demand for miniaturized electronic devices, buried word line dynamic random access memory (buried word memory) has been developed in recent years. line DRAM) to meet the above-mentioned needs.

With the advancement of technology, all kinds of electronic products are developing towards the trend of light, thin and short. However, under this trend, the critical size of DRAM is gradually shrinking, which leads to many challenges in the manufacturing process of DRAM.

The present invention provides a method for manufacturing a memory element, which can accurately control the critical size of a capacitor contact window, thereby improving the reliability of the memory element.

The present invention provides a method for manufacturing a memory element, the steps of which are as follows. A plurality of isolation structures are formed in the substrate to separate the substrate into a plurality of active regions. A plurality of character line groups are formed in the substrate, and the character line groups extend along the Y direction and pass through the isolation structure and the active area. A plurality of bit line structures are formed on the substrate, and the bit line structures extend along the X direction and cross the word line group. A first dielectric layer is formed on the substrate between the bit line structures. A plurality of first trenches are formed in the first dielectric layer, which respectively correspond to the word line group. Fill the second dielectric layer into the first trench. A part of the first dielectric layer is removed so that the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer. A first mask layer is formed to cover the top surface of the first dielectric layer and the top surface of the second dielectric layer. Using the first mask layer as a mask, a first etching process is performed to form a plurality of second trenches in the first dielectric layer. Fill the second trench with the third dielectric layer. The first dielectric layer is removed to form a plurality of contact openings between the second dielectric layer and the third dielectric layer. Fill the conductive material into the contact window opening.

Based on the above, the present invention first forms the first dielectric layer, and then forms the second dielectric layer and the third dielectric layer in the first dielectric layer. Then, the first dielectric layer is removed to form a plurality of contact openings. Then, a conductive material is filled into the contact window opening to form a plurality of capacitor contact windows. In other words, the present invention uses the damascene method to form the capacitor contact window, which can simplify the manufacturing method of the capacitor contact window and accurately control the critical size of the capacitor contact window.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIG. 1 is a schematic top view of a memory device according to an embodiment of the invention. The memory elements described in the following embodiments are described using dynamic random access memory (DRAM) as an example, but the invention is not limited thereto.

1, this embodiment provides a memory device including: a substrate 100, a plurality of isolation structures 101, a plurality of active areas AA, a plurality of bit line structures 102, a plurality of word line groups 202, and a plurality of capacitor contact windows CC1, CC2. For the sake of clarity of the drawing, FIG. 1 only shows the above-mentioned components, and other components can be seen in the sectional views of subsequent FIGS. 2A-2L and 3A-3L.

As shown in FIG. 1, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first regions R1 and the second regions R2 are alternately arranged along the X direction. The isolation structure 101 is disposed in the substrate 100 to define the substrate 100 to define multiple active areas AA. In other words, there is an isolation structure 101 between two adjacent active areas AA. In one embodiment, only one memory cell is formed on one active area AA, and each memory cell is separated by the isolation structure 101 to effectively reduce the interference problem between the memory cells. In detail, the active area AA is configured in a strip shape and arranged in an array. In this embodiment, the active area AA is arranged into three active area columns (active area columns) AC1 to AC3, and two adjacent active area columns are in a mirror configuration. For example, the long side direction of the active area row AC3 is non-orthogonal to the X direction and has an included angle θ, and the long side direction of the active area row AC2 is non-orthogonal to the X direction and has an included angle (180°-θ). In one embodiment, the included angle θ may be between 20 degrees and 22 degrees. However, the present invention is not limited to this. In other embodiments, two adjacent active area rows may also have the same configuration.

The bit line structure 102 is located on the substrate 100 and traverses the first region R1 and the second region R2. The bit line structures 102 extend along the X direction and are arranged with each other along the Y direction. The character line group 202 is located in the substrate 100 of the first region R1. The character line groups 202 extend along the Y direction and are arranged with each other along the X direction. Each character line group 202 has two buried character lines 202a, 202b. In one embodiment, the X direction and the Y direction are substantially perpendicular to each other.

In this embodiment, each active area AA has a long side L1 and a short side L2, and the long side L1 traverses the corresponding character line group 202 (that is, two embedded character lines 202a, 202b), and There is a bit line contact window BC at the overlap of each active area AA and the corresponding bit line structure 102. Therefore, when each bit line structure 102 traverses the corresponding word line group 202, the bit line contact window BC can be used to electrically connect the corresponding doped region (not shown). The doped region is located between the two buried word lines 202a, 202b.

The capacitor contact windows CC1 and CC2 are located on the substrate 100 between the bit line structures 102. In detail, the capacitor contact windows CC1 and CC2 are respectively disposed on the two ends of the long side L1 of the active area AA, and they can be electrically connected to the active area AA and subsequent capacitors (not shown). In addition, although the capacitor contact windows CC1 and CC2 are shown as rectangles in FIG. 1, the actual contact windows formed will be slightly circular, and the size of the contact windows can be designed according to the requirements of the manufacturing process.

2A to 2L are schematic cross-sectional views of the manufacturing process of the memory device along the line A-A' in FIG. 1. 3A to 3L are schematic cross-sectional views of the manufacturing process of the memory device along the line B-B' in FIG. 1.

Please refer to FIG. 1, FIG. 2A and FIG. 3A at the same time. The present embodiment provides a method for manufacturing a memory device. The steps are as follows. First, an initial structure is provided, which includes a substrate 100, a plurality of isolation structures 101, a plurality of bit line structures 102, and a plurality of word line groups 202. In one embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator, SOI) on an insulating layer. In this embodiment, the substrate 100 is a silicon substrate.

As shown in FIGS. 1 and 3A, the isolation structure 101 is disposed in the substrate 100 to separate the substrate 100 into a plurality of active areas AA. In an embodiment, the isolation structure 101 includes a dielectric material, and the dielectric material may be silicon oxide. In another embodiment, the isolation structure 101 may be, for example, a shallow trench isolation structure (STI).

As shown in FIGS. 1 and 2A, a plurality of character line groups 202 are arranged in the substrate 100 of the first region R1. In detail, each character line group 202 includes two buried character lines 202a and 202b. Each buried word line 202a includes a gate electrode 204a and a gate dielectric layer 206a. The gate dielectric layer 206a surrounds the gate electrode 204a to electrically isolate the gate electrode 204a from the substrate 100. In an embodiment, the material of the gate electrode 204a includes a conductive material, the conductive material may be, for example, a metal material, a barrier metal material, or a combination thereof, and the formation method thereof may be chemical vapor deposition (CVD) or physical vapor deposition. Deposition method (PVD). The material of the gate dielectric layer 206a may be, for example, silicon oxide, and its formation method may be a chemical vapor deposition method, a thermal oxidation method, or an in situ steam generation (ISSG) method. Similarly, the other buried word line 202b also includes a gate electrode 204b and a gate dielectric layer 206b. The gate dielectric layer 206b surrounds the gate electrode 204b to electrically isolate the gate electrode 204b from the substrate 100. In addition, the initial structure further includes a silicon nitride layer 208. In detail, the silicon nitride layer 208 is disposed on the buried word lines 202 a and 202 b and extends to cover the top surface of the substrate 100 and the isolation structure 101. In an embodiment, the formation method of the silicon nitride layer 208 may be a chemical vapor deposition method.

Referring back to FIGS. 1 and 3A, a plurality of bit line structures 102 are formed on the substrate 100. In the cross section of FIG. 3A, the bit line structure 102 includes a silicon oxide layer 104, a silicon nitride layer 106, a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The first spacer 114 covers the sidewalls of the silicon nitride layer 106, the sidewalls of the barrier layer 108, the sidewalls of the bit line 110, and the sidewalls of the cap layer 112. The second spacer 116 covers the sidewalls of the first spacer 114, the sidewalls of the silicon oxide layer 104 and the top surface of the cap layer 112. On the other hand, in the cross section along the active area AA, the bit line structure 102 includes a bit line contact window (not shown), a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The bit line structure 102 can be electrically connected to the active area AA (that is, the source/drain doped area) through a bit line contact window (not shown).

In one embodiment, the material of the bit line contact window (not shown) may be polysilicon or silicon germanium. The material of the barrier layer 108 includes a barrier metal material, which may be TiN, for example. The material of the bit line 110 may be a metal material, which may be W, for example. The material of the cap layer 112 may be silicon nitride. In addition, a metal silicide layer (not shown) may also be included between the bit line contact window (not shown) and the bit line 110, which may be TiSi, CoSi, NiSi, or a combination thereof, for example.

It should be noted that the first spacer 114 and the second spacer 116 may be in the form of strips extending along the X direction, which can protect the sidewalls of the bit line structure 102 to electrically isolate the bit line structure 102 from subsequent ones. The formed conductor material 136 (as shown in Figure 3J). In addition, the material of the first spacer 114 may be silicon nitride, and the material of the second spacer 116 may be silicon oxide. The method of forming the first spacer 114 and the second spacer 116 is similar to the conventional method of forming the spacer, and will not be described in detail here. In one embodiment, since the second spacer 116 is silicon oxide, compared to the conventional silicon nitride, the second spacer 116 of this embodiment can effectively reduce the distance between adjacent bit line structures 102. The parasitic capacitance, and then improve the performance of the memory. However, the present invention is not limited to this, and the material of the second spacer 116 may be other low dielectric constant materials (ie, dielectric materials with a dielectric constant lower than 4).

2A and 3A at the same time, a first dielectric layer 118 is formed on the initial structure (or the substrate 100). The first dielectric layer 118 fills the space between the bit line structure 102 and extends to cover the top surface of the bit line structure 102. In an embodiment, the material of the first dielectric layer 118 may be spin-on dielectric (SOD).

As shown in FIGS. 2A and 3A, a silicon oxide layer 120, a carbon layer 122, and a silicon oxynitride layer 124 are sequentially formed on the first dielectric layer 118. In one embodiment, the composite layer of the silicon oxide layer 120, the carbon layer 122, and the silicon oxynitride layer 124 can be regarded as the hard mask layer HM. In another embodiment, the material of the silicon oxide layer 120 may be, for example, tetraethoxysilane (TEOS).

As shown in FIGS. 2A and 3A, a photoresist pattern 126 is formed on the silicon oxynitride layer 124 (or the hard mask layer HM). The photoresist pattern 126 has a plurality of openings 12. The opening 12 may be a strip-shaped opening, which extends along the Y direction and exposes a part of the surface of the silicon oxynitride layer 124. On the other hand, the opening 12 is only located on the substrate 100 in the first region R1 and corresponds to the character line group 202.

2B and 3B at the same time, using the photoresist pattern 126 as a mask, remove a portion of the hard mask layer HM and a portion of the first dielectric layer 118, so that the remaining silicon oxide layer 120 and the first dielectric layer 118a A plurality of first trenches 14 are formed in the middle. The first trench 14 extends along the Y direction and exposes the top surface of the silicon nitride layer 208 in the first region R1. That is, the first trench 14 separates two adjacent first dielectric layers 118a, so that the first dielectric layer 118a is located on the substrate 100 in the second region R2.

2B-2C and 3B-3C at the same time, after removing the photoresist pattern 126, the silicon oxynitride layer 124 and the carbon layer 122, a dielectric material 128 is formed on the silicon oxide layer 120. The dielectric material 128 is filled in the first trench 14 and covers the top surface 120t of the silicon oxide layer 120. In an embodiment, the dielectric material 128 may be a nitride, such as silicon nitride.

Referring to FIGS. 2C-2D and 3C-3D at the same time, a first etch-back process is performed on the dielectric material 128 to remove part of the dielectric material 128 to expose the top surface 120t of the silicon oxide layer 120. In this case, the top surface 128t of the second dielectric layer 128a filled in the first trench 14 and the top surface 120t of the silicon oxide layer 120 are substantially coplanar. In an alternative embodiment, the first dielectric layer 118a and the silicon oxide layer 120 thereon can be regarded as an entire first dielectric layer.

Please refer to FIGS. 2D-2E and 3D-3E at the same time to remove the silicon oxide layer 120. As shown in FIG. 2E, the top surface 118t of the first dielectric layer 118a is lower than the top surface 128t of the second dielectric layer 128a. In one embodiment, there is a height difference H between the top surface 118t of the first dielectric layer 118a and the top surface 128t of the second dielectric layer 128a, and the height difference H may be between 55 nm and 65 nm. In an alternative embodiment, part of the first dielectric layer 118a is also removed.

2F and 3F at the same time, a first mask layer 130 is formed on the substrate 100. In an embodiment, the material of the first mask layer 130 includes a dielectric material, which can be, for example, oxide, nitride, oxynitride, or a combination thereof, which can be formed by atomic layer deposition (ALD) or similar methods . In this embodiment, the first mask layer 130 may be Ultra-Low Temperature Oxide (ULTO). As shown in FIG. 2F, the first mask layer 130 conformally covers the top surface 118t of the first dielectric layer 118a and the top surface 128t of the second dielectric layer 128a to form an uneven surface 130t. In some embodiments, the first mask layer 130 may be, for example, a continuous concave-convex structure having the same thickness. The first mask layer 130 on the first dielectric layer 118a is a concave portion; and the first mask layer 130 on the second dielectric layer 128a is a convex portion. In an alternative embodiment, the top surface 130t of the first mask layer 130 has a plurality of first notches 16, which respectively correspond to the isolation structure 101 in the second region R2 (or the top surface 118t of the first dielectric layer 118a) .

As shown in FIG. 2F and FIG. 3F, a second mask layer 132 is formed on the first mask layer 130. In an embodiment, the material of the second mask layer 132 includes a dielectric material, which may be, for example, oxide, nitride, oxynitride, or a combination thereof, which may be formed by chemical vapor deposition or similar methods. In this embodiment, the second mask layer 132 may be plasma-enhanced silicon nitride (PESIN). Specifically, as shown in FIG. 2F, the second mask layer 132 is filled in the first recess 16, so that the top surface 132 t of the second mask layer 132 forms the second recess 18. The second mask layer 132 (or the second mask layer 132 in the first recess 16) located on the first dielectric layer 118a has a first thickness T1, and the second mask layer 132 located on the second dielectric layer 128a The mask layer 132 has a second thickness T2. In an embodiment, the second thickness T2 is greater than the first thickness T1. In an alternative embodiment, the second mask layer 132 is a non-conformal layer, and therefore, an overhang is formed on the top of the second recess 18. In this case, as shown in FIG. 2F, the cross-sectional profile of the second notch 18 is a shape with a narrow top and a wide bottom. That is, the bottom width W2 of the second notch 18 is greater than the top width W1 of the second notch 18. In this embodiment, the second mask layer 132 helps to control the width of the third dielectric layer 134a to be subsequently formed (as shown in FIG. 2H). It will be explained in detail in the subsequent paragraphs and will not be detailed here.

2F-2G and 3F-3G at the same time, the second mask layer 132 and the first mask layer 130 are used as masks to perform a full-scale etching process (which can be regarded as the first etching process). A plurality of second trenches 24 are formed in the dielectric layer 118a. Specifically, the second trench 24 runs through the second mask layer 132a, the first mask layer 130a, and the first dielectric layer 118b along the second recess 18 downward to expose the nitrogen in the second region R2. The silicon layer 208. In the process of forming the second trench 24, part of the second mask layer 132 is removed, so that the thickness of the second mask layer 132 a is smaller than the thickness of the second mask layer 132. In this embodiment, the second trench 24 is formed by using the second mask layer 132 and the first mask layer 130 as an etching mask, and can be aligned in the second region R2 without an additional mask. The isolation structure 101. Therefore, the second trench 24 can be regarded as a self-align trench. In this case, this embodiment can reduce the number of manufacturing steps and the use of photomasks, thereby reducing manufacturing costs.

In one embodiment, the above-mentioned comprehensive etching process has high etching selectivity for the second mask layer 132 and the first mask layer 130. In other words, the etching rate for the first mask layer 130 in this comprehensive etching process is greater than the etching rate for the second mask layer 132. In addition, since the first thickness T1 of the second mask layer 132 is smaller than the second thickness T2, the thinner second mask layer 132 located in the first recess 16 is quickly removed during the full-scale etching process. It is removed, thereby exposing the first mask layer 130 below. On the other hand, the thicker second mask layer 132 on the second dielectric layer 128a can be used as an etching mask to prevent the first mask layer 130 from being over-etched.

In addition, in one embodiment, the above-mentioned comprehensive etching process has high etching selectivity for the second mask layer 132 and the first dielectric layer 118a. That is to say, the etching rate for the first dielectric layer 118a of this comprehensive etching process is greater than the etching rate for the second mask layer 132. In this case, the second mask layer 132 can be used as an etching mask to form the second trench 24 in the first dielectric layer 118a.

It is worth noting that if the full-scale etching process is directly performed without forming the second mask layer 132, the full-scale etching process will over-etch the first mask layer 130 and widen the width of the second trench 24. Make it larger than the width of the first recess 16. In this case, the width of the third dielectric layer 134a (as shown in FIG. 2H) subsequently filled in the second trench 24 will increase, thereby reducing the capacitor contact windows CC1 and CC2 (as shown in FIG. 2L) to be subsequently formed. ) Width. That is to say, the contact area between the active area AA and the capacitor contact windows CC1, CC2 will decrease, which will cause the impedance between the active area AA and the capacitor contact windows CC1, CC2 to increase, thereby leading to the operating speed and performance of the memory device. reduce. On the other hand, if the width of the second trench 24 is too large, it is not conducive to reducing the critical size of the memory device.

As shown in FIG. 2G, after forming the second trench 24, a dielectric material 134 is formed on the substrate 100. The dielectric material 134 is filled in the second trench 24 and extends to cover the top surface of the second mask layer 132a. In an embodiment, the dielectric material 134 may be, for example, an oxide, a nitride, an oxynitride, or a combination thereof, and it may be formed by ALD, CVD or similar methods. In this embodiment, the dielectric material 134 may be nitride, such as silicon nitride.

2G-2H and 3G-3H at the same time, perform a second etch-back process to remove part of the dielectric material 134, the second mask layer 132a, the first mask layer 130a, and a part of the second dielectric layer 128a, To expose the top surface 118t of the first dielectric layer 118b. In this case, the dielectric material 134 filled in the second trench 24 can be regarded as a third dielectric layer 134a, which separates two adjacent first dielectric layers 118b. In another embodiment, as shown in FIG. 3H, part of the second spacer 116 is also removed to expose the top surface 102t of the bit line structure 102.

2H-2I and 3H-3I at the same time, an etching process (which can be regarded as a second etching process) is performed, and the first dielectric layer 118b is removed, so that the second dielectric layer 128b and the third dielectric layer 134a A plurality of contact window openings 26 are formed therebetween. In one embodiment, the etching process includes a dry etching process, a wet etching process, or a combination thereof. For example, only the dry etching process can be performed. On the other hand, it is also possible to perform a dry etching process first, and then perform a wet etching process to avoid damage to the top surface of the substrate 100. In this embodiment, the etching rate for the first dielectric layer 118b in the etching process is greater than the etching rate for the second dielectric layer 128b and the etching rate for the third dielectric layer 134a. That is, during the etching process, the first dielectric layer 118b is completely removed, but the second dielectric layer 128b and the third dielectric layer 134a are not removed or slightly removed. In addition, although the contact opening 26 shown in FIG. 2I and FIG. 3I exposes the top surface of the silicon nitride layer 208, the present invention is not limited to this. In other embodiments, the above-mentioned etching process can also remove part of the silicon nitride layer 208 to expose the substrate 100 in the second region R2. In an alternative embodiment, after the etching process is performed, an additional etching process may also be performed to remove a part of the silicon nitride layer 208 to expose the substrate 100 in the second region R2.

2J and 3J at the same time, the conductive material 136 is filled into the contact opening 26. In one embodiment, the conductive material 136 may be, for example, polysilicon, and its formation method may be CVD first, and then chemical mechanical polishing (CMP).

Referring to FIGS. 2J-2K and 3J-3K at the same time, part of the conductive material 136 is removed to form a plurality of openings 28 on the conductive material 136a. As shown in FIG. 2K, the opening 28 is located between the second dielectric layer 128b and the third dielectric layer 134a. As shown in FIG. 3K, the opening 28 is located between the bit line structures 102.

As shown in FIGS. 2L and 3L, a metal silicide layer 138 and a metal layer 140 are respectively formed on the conductive material 136a. In an embodiment, the metal silicide layer 138 may be TiSi, CoSi, NiSi, or a combination thereof, for example. In an embodiment, the metal layer 140 may be W, for example. As shown in FIG. 2L, the composite structure of the conductive material 136a, the metal silicide layer 138, and the metal layer 140 can be regarded as the capacitor contact window CC1 or CC2. The capacitor contact windows CC1 and CC2 are respectively disposed at both ends of the active area AA to electrically connect the active area AA and the capacitor 144 formed subsequently.

In one embodiment, as shown in FIG. 2L, the capacitor contact windows CC1 and CC2 not only cover the surface of the active area AA, but also cover the top surface of the partially embedded character line 202a. Specifically, this embodiment uses a damascene method to form the capacitor contact windows CC1 and CC2. Therefore, the capacitor contact windows CC1 and CC2 may have a rectangular structure. In other words, the sidewalls of the capacitor contact windows CC1 and CC2 are substantially perpendicular to the top surface of the substrate 100. In addition, the capacitor contact windows CC1 and CC2 are formed by filling the conductive material 136 into the second trench 24. In this case, compared with the step of patterning the conductive material, the manufacturing method of this embodiment can accurately control the width or critical size of the capacitor contact windows CC1 and CC2, thereby improving the reliability of the memory device.

In addition, in this case, the third dielectric layer 134a respectively corresponds to the isolation structure 101 in the substrate 100 of the second region R2 to electrically isolate the two adjacent capacitor contact windows CC1 and CC2.

2L and 3L at the same time, a dielectric layer 142 is formed on the substrate 100. Next, a plurality of capacitor openings 40 are formed in the dielectric layer 142, and a plurality of capacitors 144 are formed in the capacitor openings 40, respectively. The capacitor 144 is electrically connected to the active area AA through the capacitor contact windows CC1 and CC2, respectively. Specifically, the capacitor 144 includes a lower electrode 144a, an upper electrode 144c, and a dielectric layer 144b. The dielectric layer 144b is located between the lower electrode 144a and the upper electrode 144c. The bottom electrode 144a is electrically connected to the capacitor contact windows CC1 and CC2, respectively. In an embodiment, the material of the dielectric layer 142 may be silicon oxide, for example. The material of the lower electrode 144a and the upper electrode 144c is, for example, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper, or metal silicide. The dielectric layer 144b may include a high dielectric constant material layer (ie, a dielectric material with a dielectric constant higher than 4), the material of which is, for example, oxides of the following elements, such as hafnium, zirconium, aluminum, titanium, lanthanum, and yttrium , Gamma or tantalum, or aluminum nitride, or any combination of the above.

It is worth noting that since the materials of the second dielectric layer 128b and the third dielectric layer 134a are both silicon nitride, when the capacitor opening 40 is formed in the dielectric layer 142, the second dielectric layer 128b and the third dielectric layer 134a The dielectric layer 134a can be used as an etch stop layer. The etch stop layer can avoid excessive etching when forming the capacitor opening 40, which may cause a short circuit problem caused by the electrical connection of two adjacent capacitor contact windows CC1 and CC2. On the other hand, even if there is an overlap shift or misalignment during the formation of the capacitor opening 40, the second dielectric layer 128b and the third dielectric layer 134a made of silicon nitride are not the same. The over-etching formed by the capacitor opening 40 can be prevented, so as to prevent the short circuit problem of two adjacent capacitor contact windows CC1 and CC2. Therefore, the capacitor contact windows CC1 and CC2 of this embodiment can maintain a columnar structure without sharp corners at the bottom of the capacitor contact windows CC1 and CC2.

In summary, in the present invention, the first dielectric layer is formed first, and then the second dielectric layer and the third dielectric layer are formed in the first dielectric layer. Afterwards, the first dielectric layer is removed to form a plurality of contact window openings. Then, a conductive material is filled into the contact window opening to form a plurality of capacitor contact windows. That is to say, the present invention uses the damascene method to form the capacitor contact window, which can simplify the manufacturing method of the capacitor contact window and accurately control the critical size of the capacitor contact window, thereby improving the reliability of the memory element. In addition, in the present invention, the material of the dielectric layer next to the capacitor contact window is all silicon nitride, which can avoid the problem of short circuit of two adjacent capacitor contact windows caused by excessive etching.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

12: opening 14: The first ditch 16: first notch 18: second notch 24: The second ditch 26, 28: contact window opening 40: Capacitor opening 100: base 101: Isolation structure 102: bit line structure 102t: the top surface of the bit line structure 104: silicon oxide layer 106: silicon nitride layer 108: barrier layer 110: bit line 112: roof layer 114: first gap 116: second spacer 118, 118a, 118b: first dielectric layer 118t: the top surface of the first dielectric layer 120: silicon oxide layer 120t: The top surface of the silicon oxide layer 122: Carbon layer 124: Silicon oxynitride layer 126: photoresist pattern 128: Dielectric material 128a, 128b: second dielectric layer 128t: the top surface of the second dielectric layer 130, 130a: the first mask layer 130t: the top surface of the first mask layer 132, 132a: second mask layer 132t: The top surface of the second mask layer 134, 134a: third dielectric layer 136, 136a: Conductor material 138: metal silicide layer 140: Metal layer 142: Dielectric layer 144: Capacitor 144a: lower electrode 144b: Dielectric layer 144c: upper electrode 202: character line group 202a, 202b: buried character line 204a, 204b: gate 206a, 206b: gate dielectric layer 208: silicon nitride layer AA: active area AC1, AC2, AC3: active area line BC: bit line contact window CC1, CC2: capacitor contact window H: height difference HM: Hard mask layer L1: Long side L2: Short side R1: Zone 1 R2: Zone 2 T1: first thickness T2: second thickness W1: The top width of the second notch W2: the bottom width of the second notch θ: included angle

FIG. 1 is a schematic top view of a memory device according to an embodiment of the invention. 2A to 2L are schematic cross-sectional views of the manufacturing process of the memory device along the line A-A' in FIG. 1. 3A to 3L are schematic cross-sectional views of the manufacturing process of the memory device along the line B-B' in FIG. 1.

40: Capacitor opening

100: base

101: Isolation structure

128b: second dielectric layer

134a: third dielectric layer

136a: Conductor material

138: metal silicide layer

140: Metal layer

142: Dielectric layer

144: Capacitor

144a: lower electrode

144b: Dielectric layer

144c: upper electrode

202: character line group

202a, 202b: buried character line

204a, 204b: gate

206a, 206b: gate dielectric layer

208: silicon nitride layer

AA: active area

CC1, CC2: capacitor contact window

R1: Zone 1

R2: Zone 2

Claims (13)

A method for manufacturing a memory element includes: Forming a plurality of isolation structures in the substrate to separate the substrate into a plurality of active regions; Forming a plurality of character line groups in the substrate, the character line groups extending along the Y direction and passing through the isolation structure and the active area; Forming a plurality of bit line structures on the substrate, the bit line structures extending along the X direction and across the character line group; Forming a first dielectric layer on the substrate between the bit line structures; Forming a plurality of first trenches in the first dielectric layer, which respectively correspond to the character line group; Filling a second dielectric layer into the first trench; Removing part of the first dielectric layer so that the top surface of the first dielectric layer is lower than the top surface of the second dielectric layer; Forming a first mask layer to cover the top surface of the first dielectric layer and the top surface of the second dielectric layer; Using the first mask layer as a mask, performing a first etching process to form a plurality of second trenches in the first dielectric layer; Filling a third dielectric layer into the second trench; Removing the first dielectric layer to form a plurality of contact openings between the second dielectric layer and the third dielectric layer; and Fill the conductive material into the contact window opening. According to the manufacturing method of the memory element described in the first item of the scope of patent application, the top surface of the first mask layer has a plurality of first notches corresponding to the isolation structure. The method for manufacturing a memory element as described in item 2 of the scope of the patent application further includes forming a second mask layer on the first mask layer, wherein the second mask layer is filled in the first recess , So that a plurality of second notches are formed on the top surface of the second mask layer. According to the manufacturing method of the memory element described in the scope of patent application 3, the width of the bottom of each of the second recesses is greater than the width of the top. The method for manufacturing a memory device as described in the scope of patent application 3, wherein the second mask layer located on the first dielectric layer has a first thickness, and all areas located on the second dielectric layer have a first thickness. The second mask layer has a second thickness, and the second thickness is greater than the first thickness. According to the manufacturing method of the memory device according to the third item of the patent application, the first mask layer includes ultra-low temperature oxide, atomic layer oxide or a combination thereof, and the second mask layer includes nitride. According to the manufacturing method of the memory device according to the third item of the scope of patent application, the etching rate of the first mask layer in the first etching process is greater than the etching rate of the second mask layer. According to the manufacturing method of the memory device described in the scope of patent application 3, the etching rate of the first dielectric layer in the first etching process is greater than the etching rate of the second mask layer. According to the method of manufacturing a memory device according to claim 3, wherein the step of removing the first dielectric layer to form the contact window opening includes performing a second etching process, which includes a dry etching process, Wet etching process or a combination thereof. According to the manufacturing method of the memory element described in the scope of patent application, the etching rate of the first dielectric layer by the second etching process is greater than that of the second dielectric layer and the third dielectric layer. The etching rate of the layer. The method for manufacturing a memory element according to the first item of the patent application, wherein the material of the first dielectric layer includes a spin-on dielectric material, the second dielectric layer includes a nitride, and the third dielectric layer The electrical layer includes nitride. According to the manufacturing method of the memory element described in the first item of the scope of patent application, after filling the conductive material into the contact window opening, the method further includes: Etch back the conductor material; Forming a metal silicide layer on the conductive material; and A metal layer is formed on the metal silicide layer. The method of manufacturing a memory element as described in the first item of the patent application further includes forming a plurality of capacitors on the conductor material, wherein one of the capacitors includes: a lower electrode, an upper electrode, and an upper electrode arranged on the upper electrode. The dielectric layer between the electrode and the lower electrode.

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