TWI825725B - Method of manufacturing memory device having active area in strip - Google Patents

Abstract

The present application provides a memory device and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area over or in the semiconductor substrate and including a recess surrounding the active area; a first dielectric layer disposed over the active area of the semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; and an isolation member disposed within the recess and entirely surrounding the active area.

Description

Preparation method of memory element with strip-shaped active area

This application claims priority to U.S. Patent Application Nos. 17/685,520 and 17/686,106 (that is, the priority date is "March 3, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a memory device and a manufacturing method thereof. In particular, it relates to a memory element having a strip-shaped active area (AA) and a method for manufacturing the memory element.

Non-volatile memory elements retain data even when power is removed. One type of non-volatile memory device is a one-time programmable (OTP) memory device. Using OTP memory components, users can only program the OTP memory components once, and the data stored in the OTP memory components cannot be modified. Signals are transmitted to metal interconnects provided on a semiconductive substrate.

However, the wiring of such metal interconnects poses an obstacle to increasing the wiring density of memory devices. Such wiring may cause a narrow process window and may cause misalignment or leakage between memory cells in the memory device, thereby limiting the reduction of the minimum feature size. Therefore, it is expected to develop improvements that can resolve related manufacturing challenges. .

The above description of "prior art" is only to provide background technology and does not acknowledge the above The "prior art" description in this article discloses the subject matter of the present disclosure and does not constitute the prior art of the present disclosure, and any description of the "prior art" above shall not be regarded as any part of this case.

One aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes the steps of: providing a semiconductor substrate, including an active region disposed on or in the semiconductor substrate, a first dielectric layer on the semiconductor substrate, and a second dielectric layer on the first dielectric layer. A dielectric layer and a patterned photoresist layer on the second dielectric layer; removing the semiconductor substrate, the first dielectric layer and the second dielectric layer exposed through the patterned photoresist layer a first portion of the layer to form a trench. Remove the patterned photoresist layer; set an isolation component in the trench; set a sacrificial pillar on the second dielectric layer; set a first spacer around the sacrificial pillar; remove the sacrificial pillar; A second spacer is provided around the first spacer; and a second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer is removed.

In some embodiments, the preparation method further includes removing the first gap after removing the first dielectric layer and the second portion of the second dielectric layer exposed through the second spacer. sub and the second gap sub.

In some embodiments, the sacrificial pillar is removed after the first spacer is disposed and before the second spacer is disposed.

In some embodiments, the preparation method further includes removing a third portion of the semiconductor substrate exposed through the second spacer, the first dielectric layer, and the second dielectric layer.

In some embodiments, the sacrificial pillar includes nitride.

In some embodiments, a cross section of the sacrificial post is circular.

In some embodiments, the first spacer and the second spacer include a phase Same dielectric material.

In some embodiments, removing the first dielectric layer and the second portion of the second dielectric layer exposed through the second spacer includes removing the second portion of the second dielectric layer that appears in a top view. a fourth portion of the first dielectric layer and the second dielectric layer within the spacer, and remove the first dielectric layer appearing outside the second spacer from the top view; and a fifth portion of the second dielectric layer.

In some embodiments, removing the fourth portion of the first dielectric layer and the second dielectric layer that appear within the second spacer from the top view occurs after moving from the top view. The removal is performed before or after the fifth portion of the first dielectric layer and the second dielectric layer appearing outside the second spacer.

In some embodiments, removing the first dielectric layer and the fourth portion of the second dielectric layer appearing within the second spacer from the top view and removing the fourth portion of the second dielectric layer from the top view The first dielectric layer outside the second spacer and the fifth portion of the second dielectric layer are executed simultaneously.

In some embodiments, the arrangement of the second spacer includes forming an opening surrounded by the first spacer and the second spacer.

In some embodiments, the second portions of the first dielectric layer and the second dielectric layer exposed through the second spacer are at least partially disposed within the opening from the top view.

In some embodiments, the second spacer includes a first annular member in contact with an outer surface of the first spacer, and includes a second annular member in contact with an inner surface of the first spacer. .

In some embodiments, the first dielectric layer includes oxide.

In some embodiments, the second dielectric layer includes nitride.

In some embodiments, the isolation component includes an oxide.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes the steps of: providing a semiconductor substrate, including an active region disposed on or in the semiconductor substrate; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; forming a nitride film extending through the semiconductor substrate. A trench of the oxide film and the nitride film; forming a first hollow spacer on the nitride film; forming a second hollow spacer around the first hollow spacer; forming a groove surrounded by the first hollow spacer a third hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second hollow spacer and the third hollow spacer.

In some embodiments, the second hollow spacer surrounds the first hollow spacer and the third hollow spacer.

In some embodiments, the manufacturing technology of the oxide film includes oxidizing the semiconductor substrate.

In some embodiments, the manufacturing technology of the nitride film includes chemical vapor deposition (CVD).

In some embodiments, the trench is filled with an isolation material.

In some embodiments, the preparation method further includes disposing a photoresist material on the nitride film, and patterning the photoresist material to form a patterned photoresist layer.

In some embodiments, forming the trench includes removing the oxide film and the nitride film exposed through the patterned photoresist layer.

In some embodiments, the preparation method further includes forming a sacrificial pillar on the nitride film before forming the first hollow spacer.

In some embodiments, the first hollow spacer surrounds the sacrificial post.

In some embodiments, the preparation method further includes removing the sacrificial pillar after forming the first hollow spacer.

In some embodiments, the formation of the second hollow spacer and the formation of the third hollow spacer are performed separately or simultaneously.

In some embodiments, the second hollow spacer and the third hollow spacer include a same dielectric material.

In some embodiments, the preparation method further includes removing a portion of the semiconductor substrate exposed through the nitride film to form a hole, and filling the hole with an isolation component.

Another aspect of the present disclosure provides a memory device. The memory device includes a semiconductor substrate, an active region is defined on or in the semiconductor substrate, and includes a groove surrounding the active region; a first dielectric layer disposed on the active region of the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; and an isolation component disposed in the groove and completely surrounding the active area.

In some embodiments, a top surface of the second dielectric layer and a top surface of the isolation component are substantially coplanar.

In some embodiments, a top surface of the first dielectric layer is substantially lower than a top surface of the isolation component.

In some embodiments, the first dielectric layer and the isolation feature include a same material.

In some embodiments, the semiconductor substrate includes silicon.

In some embodiments, the first dielectric layer and the isolation component are integral.

In short, since the active region of the semiconductor substrate is formed by It is defined by placing a plurality of annular spacers and removing a predetermined portion of the semiconductor substrate exposed through the annular spacers, and the size of the active region may be kept minimal or not reduced during the removal. Therefore, the subsequent process window on the active area is not further reduced. Therefore, misalignment or leakage between memory cells in the memory device can be prevented or minimized, and the overall performance of the memory device can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100:Memory components

101:Semiconductor substrate

101a:Array area

101b: Active area

101c: Groove

102: First dielectric layer

102a:Top surface

103: Second dielectric layer

103a:Top surface

104:Isolation components

104a:Top surface

105:Patterned photoresist layer

105a: Photoresist material

106:Ditch

107:Isolation materials

108:Sacrificial Pillar

109:First gap

109a:Outer surface

109b:Inner surface

110: The second gap

110a: First ring component

110b: Second ring component

111:Open your mouth

112:hole

AA:line

BB:line

CC: line

DD:line

EE: line

FF: line

GG: line

HH: line

S200: Preparation method

S201: Steps

S202: Step

S203: Step

S204: Step

S205: Step

S206: Step

S207: Step

S208: Step

S209: Step

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a cross-sectional side view illustrating a memory device according to some embodiments of the present disclosure.

FIG. 2 is a cross-sectional top view illustrating the memory device of FIG. 1 .

FIG. 3 is a flow chart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure.

4 to 27 are cross-sectional views illustrating intermediate stages of manufacturing memory devices according to some embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. To simplify the present disclosure, the components and arrangements are described below specific examples. Of course, these are just examples and are not meant to be limiting. For example, in the following description, the formation of the first feature on the second feature may include an embodiment in which the first and second features are in direct contact, or may include an embodiment in which additional features are formed between the first and second features. For example, the first and second features may not be in direct contact.

Additionally, reference numbers and/or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and/or arrangements discussed.

In addition, spatially relative terms, such as "below", "below", "below", "above", "above", etc., for convenience of description, may be used here to describe one element or feature and another as shown in the figure ( some) elements or characteristics. Spatially relative terms are intended to encompass various orientations of elements in use or operation, as well as the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a cross-sectional side view illustrating a memory device 100 according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional top view illustrating the memory device 100 in FIG. 1 . Figure 1 is a cross-sectional side view along line AA in Figure 2. In some embodiments, memory element 100 as shown in Figure 1 may be part of an element. In some embodiments, the memory device 100 includes a plurality of unit cells arranged along rows and columns.

In some embodiments, memory device 100 includes semiconductor substrate 101 . In some embodiments, semiconductor substrate 101 is semiconductive in nature. In some embodiments, semiconductor substrate 101 is a semiconductor wafer (eg, silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, silicon-on-insulator wafer). In some embodiments, semiconductor substrate 101 is a silicon substrate.

In some embodiments, semiconductor substrate 101 is defined to have a peripheral area (not shown) and array area 101a. In some embodiments, array area 101a is at least partially surrounded by a surrounding area. In some embodiments, the peripheral region is adjacent to the periphery of the semiconductor substrate 101 and the array region 101a is adjacent to the central region of the semiconductor substrate 101 . In some embodiments, the array area 101a may be used for the preparation of electronic components, such as capacitors, transistors, or similar components. In some embodiments, a boundary is provided between the peripheral area and the array area 101a.

In some embodiments, the semiconductor substrate 101 includes a groove 101c extending into the semiconductor substrate and surrounding the active region 101b. In some embodiments, the semiconductor substrate 101 includes an active region 101b disposed on or within the semiconductor substrate 101 . In some embodiments, active region 101 b is a doped region in semiconductor substrate 101 . In some embodiments, active region 101 b extends horizontally on or below the top surface of semiconductor substrate 101 . In some embodiments, the dimensions of the top cross-section of each active region 101b may be the same or different from each other.

In some embodiments, each active region 101b includes the same type of dopant. In some embodiments, each active region 101b includes a different dopant type than is included in other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, active region 101b includes N-type dopants.

In some embodiments, the first dielectric layer 102 is disposed on the semiconductor substrate 101 . In some embodiments, the first dielectric layer 102 is disposed on the active region 101b of the semiconductor substrate 101. In some embodiments, the first dielectric layer 102 includes a dielectric material such as oxide, silicon dioxide (SiO2), or similar materials. In some embodiments, first dielectric layer 102 is an oxide film. In some embodiments, the first dielectric layer 102 may serve as a gate dielectric or part of a gate dielectric subsequently formed on the active region 101 b of the semiconductor substrate 101 .

In some embodiments, the second dielectric layer 103 is disposed on the first dielectric layer 102 and the semiconductor substrate 101 . In some embodiments, the second dielectric layer 103 is disposed on the semiconductor on the active area 101b of the body substrate 101. In some embodiments, second dielectric layer 103 includes nitride, silicon nitride, or similar materials. In some embodiments, the second dielectric layer 103 is a nitride film. In some embodiments, the second dielectric layer 103 can be used as a mask layer to protect the semiconductor substrate 101 . In some embodiments, as shown in FIG. 2 , the active region 101b covered by the first dielectric layer 102 and the second dielectric layer 103 is in a strip shape, a strip shape, a rectangular shape or a polygon shape.

In some embodiments, memory device 100 includes an isolation feature 104 surrounding active region 101 b of semiconductor substrate 101 . In some embodiments, active regions 101b are surrounded by isolation features 104 such that active regions 101b are separated and electrically isolated from each other by isolation features 104. In some embodiments, active areas 101b are arranged along row or column directions. In some embodiments, active area 101b is completely surrounded by isolation component 104.

In some embodiments, the isolation component 104 surrounds the first dielectric layer 102 and the second dielectric layer 103 disposed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the isolation feature 104 is at least partially disposed within the recess 101 c of the semiconductor substrate 101 . In some embodiments, isolation feature 104 completely surrounds active region 101 b of semiconductor substrate 101 .

In some embodiments, the top surface 103a of the second dielectric layer 103 and the top surface 104a of the isolation component 104 are substantially coplanar. In some embodiments, the top surface 102a of the first dielectric layer 102 is substantially lower than the top surface 104a of the isolation feature 104. In some embodiments, the depth of isolation feature 104 is substantially greater than or equal to the depth of active region 101b. In some embodiments, isolation feature 104 is a shallow trench isolation (STI), or is a portion of an STI. In some embodiments, isolation features 104 define the boundaries of active region 101b.

In some embodiments, the manufacturing technology of the isolation component 104 includes insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. or combinations thereof. In some embodiments, first dielectric layer 102 and isolation feature 104 include the same material. in some In this embodiment, the first dielectric layer 102 and the isolation component 104 are integrated.

3 is a flowchart illustrating the method S200 of manufacturing the memory device 100 according to some embodiments of the present disclosure. FIGS. 4 to 27 are cross-sectional views illustrating the intermediate stages of manufacturing the memory device 100 according to some embodiments of the present disclosure.

The stages shown in Figures 4 to 27 are also schematically illustrated in the flow chart of Figure 3 . In the following discussion, the preparation stages shown in FIGS. 4 to 27 are discussed with reference to the process steps shown in FIG. 3 . The preparation method S200 includes some operations, and the description and explanation should not be regarded as limiting the order of operations. Method S200 includes several steps (S201, S202, S203, S204, S205, S206, S207, S208 and S209).

Referring to FIGS. 4 to 8 , according to step S201 in FIG. 3 , a semiconductor substrate 101 , a first dielectric layer 102 on the semiconductor substrate, and a second dielectric layer on the first dielectric layer are provided. 103, and a patterned photoresist layer 105 on the second dielectric layer.

In some embodiments as shown in FIG. 4 , a semiconductor substrate 101 is provided including an active region 101 b disposed thereon or in it. In some embodiments, semiconductor substrate 101 includes semiconductive material. In some embodiments, semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 is defined to have a peripheral region (not shown) and an array region 101a at least partially surrounded by the peripheral region. In some embodiments, the array region 101a is adjacent to the central region of the semiconductor substrate 101.

In some embodiments, active region 101 b is a doped region in semiconductor substrate 101 . In some embodiments, active region 101 b extends horizontally on or below the top surface of semiconductor substrate 101 . In some embodiments, each active region 101b includes the same type of dopant. In some embodiments, each active region 101b includes a different dopant type than is included in other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the manufacturing technology of the active region 101b includes an ion implantation process or an ion doping process.

In some embodiments as shown in FIG. 5 , a first dielectric layer 102 is formed on the semiconductor substrate 101 . In some embodiments, the first dielectric layer 102 is formed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the manufacturing technique of the first dielectric layer 102 includes oxidizing the semiconductor substrate 101 or a portion of the semiconductor substrate 101 , deposition, or any other suitable process. In some embodiments, first dielectric layer 102 includes a dielectric material such as oxide, silicon dioxide (SiO2), or similar materials. In some embodiments, first dielectric layer 102 is an oxide film.

In some embodiments, as shown in FIG. 6 , a second dielectric layer 103 is formed on the first dielectric layer 102 . In some embodiments, the second dielectric layer 103 is disposed on the active region 101b of the semiconductor substrate 101. In some embodiments, second dielectric layer 103 includes nitride, silicon nitride, or the like. In some embodiments, the second dielectric layer 103 is a nitride film. In some embodiments, the manufacturing technology of the second dielectric layer 103 includes chemical vapor deposition (CVD), spin coating, or any other suitable process.

In some embodiments as shown in FIGS. 7 and 8 , the patterned photoresist layer 105 is formed on the second dielectric layer 103 . In some embodiments, the manufacturing technology of the patterned photoresist layer 105 includes disposing the photoresist material 105a on the second dielectric layer 103, as shown in Figure 7, and patterning the photoresist material 105a as shown in Figure 8. change. The patterning technique of the photoresist material 105a includes etching or any other suitable process to remove part of the photoresist material 105a. As shown in FIG. 8 , the second dielectric layer 103 is at least partially exposed through the patterned photoresist layer 105 .

Referring to FIGS. 9 and 10 , according to step S202 in FIG. 3 , the semiconductor substrate 101 , the first dielectric layer 102 and the second dielectric layer 103 exposed through the patterned photoresist layer 105 are removed. the first part to form trench 106. FIG. 10 is a top view of FIG. 9 . FIG. 9 is a cross-sectional side view along line BB in FIG. 10 . The trench 106 extends through the first dielectric layer 102 and the second dielectric layer 103 . In some embodiments, the removal technique of the first portion of the semiconductor substrate 101 , the first dielectric layer 102 and the second dielectric layer 103 exposed through the patterned photoresist layer 105 includes etching or any other suitable process. In some embodiments, after trenches 106 are formed as shown in Figure 9, a stripe pattern is formed as shown in the top view of Figure 10.

Referring to FIGS. 11 and 12 , the patterned photoresist layer 105 is removed according to step S203 in FIG. 3 . FIG. 12 is a top view of FIG. 11 . FIG. 11 is a cross-sectional side view taken along line CC in FIG. 12 . In some embodiments, the removal technique of the patterned photoresist layer 105 includes etching, stripping, or any other suitable process. As shown in FIG. 12 , after the patterned photoresist layer 105 is removed, the second dielectric layer 103 is exposed.

Referring to FIGS. 13 to 15 , according to step S204 in FIG. 3 , the isolation component 104 is disposed in the trench 106 . FIG. 15 is a top view of FIG. 14 . FIG. 14 is a cross-sectional side view along line DD in FIG. 15 . In some embodiments, the manufacturing technology of the isolation component 104 includes disposing an isolation material 107 on the semiconductor substrate 101 and the second dielectric layer 103, as shown in FIG. 13, and then removing part of the isolation material 107 to form the isolation component 104. As shown in Figure 14. In some embodiments, trench 106 is filled with isolation material 107 . In some embodiments, the removal technique of portions of isolation material 107 includes planarization, etching, or any other suitable process. In some embodiments, the isolation component 104 surrounds the first dielectric layer 102 and the second dielectric layer 103 disposed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, isolation component 104 includes oxide.

Referring to FIGS. 16 and 17 , according to step S205 in FIG. 3 , a sacrificial pillar 108 is provided on the second dielectric layer 103 . Figure 17 is a top view of Figure 16. Figure 16 is a cross-sectional side view along line EE in Figure 17. The fabrication technology of the sacrificial pillar 108 includes deposition or any other suitable process. In some embodiments, sacrificial pillar 108 is in contact with isolation feature 104 and second dielectric layer 103 . In some embodiments, sacrificial post 108 includes nitride. In some embodiments, sacrificial post 108 is circular in cross-section.

Referring to FIGS. 18 and 19 , according to step S206 in FIG. 3 , the first spacer 109 surrounding the sacrificial pillar 108 is set. Figure 19 is a top view of Figure 18. FIG. 18 is a cross-sectional side view along line FF in FIG. 19. FIG. The first spacer 109 is formed on the isolation component 104 and the second dielectric layer 103 . In some embodiments, sacrificial pillar 108 is surrounded by first spacers 109 . In some embodiments, first spacer 109 contacts the entire outer surface of sacrificial post 108 . In some embodiments, first spacer 109 is hollow. In some embodiments, sacrificial pillars 108 are formed on the second dielectric layer 103 before the first spacers 109 are formed. In some embodiments, the first spacer 109 includes a dielectric material such as an oxide, a nitride, an oxynitride, or the like.

Referring to FIGS. 20 and 21 , according to step S207 in FIG. 3 , the sacrificial pillar 108 is removed. Figure 21 is a top view of Figure 20. Fig. 20 is a cross-sectional side view along line GG in Fig. 21. In some embodiments, the removal technique of sacrificial pillar 108 includes etching or any other suitable process. In some embodiments, the sacrificial pillars 108 are removed after the first spacers 109 are formed.

Referring to FIGS. 22 and 23 , according to step S208 in FIG. 3 , the second spacer 110 surrounding the first spacer 109 is set. Figure 23 is a top view of Figure 22. Figure 22 is a cross-sectional side view along line HH in Figure 23. In some embodiments, the manufacturing technology of the second spacer 110 includes deposition or any other suitable process. In some embodiments, the sacrificial pillar 108 is removed before the second spacer 110 is provided. In some embodiments, the first spacer 109 and the second spacer 110 include the same dielectric material. In some embodiments, the first spacer 109 and the second spacer 110 include dielectric materials, such as oxide, nitride, oxynitride or similar materials.

In some embodiments, the second spacer 110 is disposed by forming a The outer surface 109a of a spacer 109 contacts the first annular component 110a and forms a second annular component 110b that contacts the inner surface 109b of the first spacer 109. In some embodiments, the first annular component 110a is a second hollow spacer, and the second annular component 110b is a third hollow spacer. In some embodiments, the first annular member 110 a surrounds the first spacer 109 and the second annular member 110 b is surrounded by the first spacer 109 . The first annular component 110a surrounds the first spacer 109 and the second annular component 110b. In some embodiments, the formation of the first annular component 110a and the second annular component 110b are performed separately or simultaneously.

In some embodiments, the arrangement of the second spacer 110 includes forming an opening 111 surrounded by the first spacer 109 and the second spacer 110 . After the second spacer 110 is disposed, at least a portion of the second dielectric layer 103 is exposed through the second spacer 110 and is disposed in the opening 111 from a top view as shown in FIG. 23 .

Referring to FIGS. 24 and 25 , according to step S209 in FIG. 3 , the second portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 are removed. 24 is a top view illustrating that the portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 and surrounded by the second annular member 110b are removed from the top view, and FIG. 25 is a top view, illustrating that the portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 and outside the first annular component 110a are removed from the top view.

In some embodiments, removing the second portion of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 includes removing the second portion of the first dielectric layer 102 and the second portion of the second dielectric layer 103 from the top view as shown in FIG. 24 Parts of the first dielectric layer 102 and the second dielectric layer 103 within the spacer 110, and the first dielectric layer 102 and the outside of the second spacer 110 are removed from the top view as shown in FIG. 25 part of the second dielectric layer 103 .

In some embodiments, the second gap is removed from the top view as shown in Figure 24 The portions of the first dielectric layer 102 and the second dielectric layer 103 within the spacer 110 are removed from the top view of the first dielectric layer 102 and the second spacer outside the second spacer as shown in FIG. 25 . The second portion of dielectric layer 103 is performed before or after. In some embodiments, portions of the first dielectric layer 102 and the second dielectric layer 103 within the second spacer 110 are removed from the top view as shown in FIG. 24 , and are removed from the top view as shown in FIG. 25 In the top view, the portions of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer are removed simultaneously.

In some embodiments, the process is performed as shown in FIG. 24 before or after removing the portions of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer in the top view as shown in FIG. 25 . After removing the portions of the first dielectric layer 102 and the second dielectric layer 103 in the second spacer 110 from the top view, at least a portion of the semiconductor substrate 101 passes through the second dielectric as shown in FIG. 25 . The electrical layer 103 is exposed.

In some embodiments, after removing the second portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacers 110, as shown in FIGS. 26 and 27, the A spacer 109 and a second spacer 110 . Figure 27 is a top view of Figure 26. In some embodiments, the removal technique of the first spacer 109 and the second spacer 110 includes etching, stripping, or any other suitable process. In some embodiments, removing the first spacer 109 and removing the second spacer 110 are performed separately or simultaneously. In some embodiments, removing the first spacer 109 is performed before or after removing the second spacer 110 .

In some embodiments, as shown in FIG. 25 , the portion of the semiconductor substrate 101 exposed through the second dielectric layer 103 is removed, and then the isolation component 104 is also disposed in the hole 112 , as shown in FIG. 27 . In some embodiments, isolation component 104 fills hole 112 . In some embodiments, removing the portion of the semiconductor substrate 101 exposed through the second dielectric layer 103 is performed before or after removing the first spacer 109 and removing the second spacer 110 . In some embodiments, The memory device 100 shown in FIGS. 1 and 2 is formed in FIGS. 26 and 27 .

In some embodiments, the second dielectric layer 103 is removed after the holes 112 are filled with the isolation features 104 . In some embodiments, after the second dielectric layer 103 is removed, the isolation feature 104 and the first dielectric layer 102 are planarized. In some embodiments, implantation of dopants is performed on active region 101b after planarization.

One aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes the steps of: providing a semiconductor substrate, including an active region disposed on or in the semiconductor substrate, a first dielectric layer on the semiconductor substrate, and a second dielectric layer on the first dielectric layer. A dielectric layer and a patterned photoresist layer on the second dielectric layer; removing the semiconductor substrate, the first dielectric layer and the second dielectric layer exposed through the patterned photoresist layer a first portion of the layer to form a trench. Remove the patterned photoresist layer; set an isolation component in the trench; set a sacrificial pillar on the second dielectric layer; set a first spacer around the sacrificial pillar; remove the sacrificial pillar; A second spacer is provided around the first spacer; and a second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer is removed.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The preparation method includes the steps of: providing a semiconductor substrate, including an active region disposed on or in the semiconductor substrate; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; forming a nitride film extending through the semiconductor substrate. A trench of the oxide film and the nitride film; forming a first hollow spacer on the nitride film; forming a second hollow spacer around the first hollow spacer; forming a groove surrounded by the first hollow spacer a third hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second hollow spacer and the third hollow spacer.

Another aspect of the present disclosure provides a memory device. The memory device includes a semiconductor substrate, an active region is defined on or in the semiconductor substrate, and includes an active region surrounding the semiconductor substrate. a groove in the active region; a first dielectric layer disposed on the active region of the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; and a second dielectric layer disposed on the recess An isolation component within the tank and completely surrounding the active area.

In summary, since the active region of the semiconductor substrate is defined by disposing a number of annular spacers on the semiconductor substrate and removing a predetermined portion of the semiconductor substrate exposed through the annular spacers, the size of the active region can be kept minimal or No reduction. Therefore, the subsequent process window on the active area is not further reduced. Therefore, misalignment or leakage between memory cells in the memory device can be prevented or minimized, and the overall performance of the memory device can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

100:Memory components

101:Semiconductor substrate

101a:Array area

101b: Active area

101c: Groove

102: First dielectric layer

102a:Top surface

103: Second dielectric layer

103a:Top surface

104:Isolation components

104a:Top surface

Claims (13)

A method for manufacturing a memory element, including: providing a semiconductor substrate, including an active region disposed on or in the semiconductor substrate; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; Form a trench extending through the oxide film and the nitride film; form a first hollow spacer on the nitride film; form a second hollow spacer around the first hollow spacer; form the first hollow spacer a third hollow spacer surrounded by hollow spacers; and removing portions of the oxide film and the nitride film exposed through the second hollow spacer and the third hollow spacer. The preparation method as claimed in claim 1, wherein the second hollow spacer surrounds the first hollow spacer and the third hollow spacer. The preparation method as claimed in claim 1, wherein the manufacturing technology of the oxide film includes oxidizing the semiconductor substrate. The preparation method as claimed in claim 1, wherein the manufacturing technology of the nitride film includes chemical vapor deposition (CVD). The preparation method of claim 1, wherein the trench is filled with an isolation material. The preparation method of claim 1 further includes disposing a photoresist material on the nitride film, and patterning the photoresist material to form a patterned photoresist layer. The preparation method of claim 6, wherein forming the trench includes removing the oxide film and the nitride film exposed through the patterned photoresist layer. The preparation method of claim 1 further includes forming a sacrificial pillar on the nitride film before forming the first hollow spacer. The preparation method as claimed in claim 8, wherein the first hollow spacer surrounds the sacrificial pillar. The preparation method of claim 8 further includes removing the sacrificial pillar after forming the first hollow spacer. The preparation method as claimed in claim 1, wherein the formation of the second hollow spacer and the formation of the third hollow spacer are performed separately or simultaneously. The preparation method of claim 1, wherein the second hollow spacer and the third hollow spacer include a same dielectric material. The preparation method of claim 1 further includes removing the semiconductor exposed through the nitride film. portion of the body base to form a hole and fill the hole with an isolation member.