KR20010008436A - Method for manufacturing hybrid semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a hybrid semiconductor device is provided to minimize damage to a peripheral circuit portion in a subsequent etching process for an interlayer dielectric, by forming a dummy pattern functioning as a guide ring on an interface between the peripheral circuit portion and a logic circuit portion. CONSTITUTION: A contact pad(49) is formed in a cell portion on a semiconductor substrate(41) having an isolation layer(43) and a word line(45). A wet-etch stop layer(51) is formed on the entire surface. The first interlayer dielectric(55), a bit line(57) and the second interlayer dielectric(59) are formed on the entire surface. A capacitor contact plug(61) is connected to the contact pad on the semiconductor substrate and a capacitor contact plug is formed on the wet-etch stop layer, wherein the capacitor contact plug formed on the wet-etch stop layer is located on an interface between a peripheral circuit portion and a logic circuit portion and used as a guard ring. A capacitor is formed only on the contact plug connected to the contact pad. After the first and second interlayer dielectrics in the logic circuit portion are etched and the wet-etch stop layer is dry-etched in a subsequent process, a silicide layer is formed in the logic circuit portion.

Description

Manufacturing method of composite semiconductor device

The present invention relates to a method for manufacturing a composite semiconductor device. More specifically, in logic, low surface resistance and contact resistance are required for high speed operation, and for this, a composite semiconductor using a silicide forming process without deterioration of device characteristics is required. It relates to a method of manufacturing a device.

The silicide process is generated by the reaction of silicon with a material such as Ti, Co, Ni, and has a low resistance.

Therefore, the silicide process must also be used in the MML process of manufacturing DRAM and logic as one chip. However, the silicide reactant has a problem that resistance increases again due to the aggregation of crystals when the temperature of the subsequent thermal process is high.

Therefore, in the MML process, a method of forming a capacitor of the DRAM first and then etching only the logic side to form silicide is used to suppress the change of the silicide characteristics by the subsequent thermal process. For reference, the capacitor formation process of DRAM requires a high temperature of 780 degrees or more.

In order to form silicide in the source / drain regions of logic after forming the capacitor of the DRAM, the oxide layer layer that has been stacked must be opened during the process up to the capacitor formation process. A wet etch is used because a thick oxide layer of 10000 kPa or more is laminated.

However, since the etching amount cannot be controlled by wet etching, the nitride layer or the polysilicon layer which has better etching selectivity than the oxide layer after the word line forming process is already disposed below the oxide layer so that the etching stop layer barrier during the wet etching of the oxide layer is performed. I use it.

The etch stop layer is etched through a dry method after wet etching of the oxide layer to open a place where the silicide is finally formed.

However, in the wet etching process, when the oxide film near the interface is etched by the lateral diffusion of the etchant, sufficient margin is given, which may cause many problems.

In the MML ball, a capacitor of a DRAM is first formed, and then a silicide is formed by etching only the logic side, thereby suppressing the change of the silicide characteristic by a subsequent thermal process.

However, after the capacitor of the DRAM is formed, an oxide layer having a thickness of about 10000 GPa or more is laminated. In order to remove this layer, a wet etching method having an excellent etching rate is used. Since it cannot be precisely controlled and etched, an oxide film and a nitride film or polysilicon having excellent etching selectivity are deposited after the transistor is formed and used as an etch stop layer. The etch stop layer is removed by dry etching again to open the contact surface where the silicide is finally formed.

As the device becomes more and more fine, recently, a method of forming a contact pad and forming a poly 2,3 contact thereon is mainly used rather than forming a poly 2,3 contact directly on a silicon semiconductor substrate.

1A to 1E are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the prior art, and are divided into a cell part, a peripheral circuit part, and a logic part.

First, as shown in FIGS. 1A to 1B, an isolation layer 13 is formed on a semiconductor substrate 11, and a gate electrode is formed in a stacked structure of a gate oxide film 15, a gate electrode conductor 17, and a mask insulating film. .

The first oxide film is deposited on the entire surface, and the first oxide film is anisotropically etched to form the first oxide film spacer.

A photoresist pattern is formed to expose the source / drain junction regions of the peripheral circuit portion and the logic portion, and the source / drain junction region is formed by implanting impurities into the peripheral circuit portion and the logic portion.

Then, the photoresist pattern is removed, and a second oxide film is formed on the entire surface at a constant thickness.

The second oxide film of the cell portion is anisotropically etched to form a spacer having a first oxide film and a second oxide film stacked structure.

Then, a contact pad 19 connected to the source / drain junction region of the cell portion is formed using a self-aligned contact process, and a polysilicon film is formed.

Then, the wet etch stop layer 21 is formed in the logic unit as shown in FIG. 1C. In this case, the wet etching barrier layer 21 is formed of a nitride film because it is difficult to control the etching amount during the wet etch process of removing the oxide layer of the logic unit.

Next, as shown in FIG. 1D, the first interlayer insulating film 23 is formed in the cell portion, and the second interlayer insulating film 25 is formed over the entire surface, and then the bit line 27 connected to the semiconductor substrate of the cell portion and the peripheral circuit portion. To form.

Then, the third interlayer insulating film 29 and the fourth interlayer insulating film 31 for flattening the upper portion are formed on the entire surface, and the capacitor 33 is formed in the cell portion of the semiconductor substrate. In this case, the capacitor 33 is connected to the capacitor contact pad 19 and is formed in a stacked structure of a storage electrode, a dielectric film, and a plate electrode.

Next, as shown in FIG. 1E, after etching various oxide layers of the logic part by a wet method using the wet etch stop layer 21 to form silicide only in the logic part, the etch stop layer 21 is dry etched. After opening the region to be formed and depositing a material such as Ti, Co, Ni and the like to form the silicide 35.

In wet etching, the oxide layer is also etched toward the DRAM region by the side diffusion of the etching solution, which causes a lot of problems when the design is not sufficient to give a margin.

This side etching phenomenon causes the following problems.

First, as the oxide film of the portion where the silicide should not be formed is removed by the side etching phenomenon, the silicon layer on the semiconductor substrate side reacts with the particles sputtered to expose and form the silicide, Ti, Co, Ni, and the like to form silicide.

Therefore, the silicide layer may be formed in a portion where the silicide should not be formed, such as DRAM. This may cause the source / drain junction depth to be increased to increase device isolation characteristics and transistor leakage current.

More specifically, the device isolation layer is removed from the interface between the silicide region and the region where the silicide is not formed due to the side diffusion by the wet etching process when the logic unit is opened, thereby forming silicide in an unwanted region. As a result, electrical short circuits and leakage currents can be caused.

Second, if there is a polysilicon line on the field oxide layer formed for device isolation at the interface between the part where silicide should not be formed and the logic requiring silicide, such as DRAM, the oxide layer under polysilicon is etched away. The line can fall off.

This is a major cause of contamination in subsequent processes, resulting in catastrophic phenomena such that the fallen polysilicon is adsorbed in an arbitrary area, resulting in an electrical short.

Third, the photo-resist (PR) itself may fall off by side etching. Since the length of the oxide film under the photoresist is etched is about 5 ㎛ large, it may cause the photoresist to partially collapse.

As a countermeasure to partially solve this problem, a method of widening the field oxide layer, which is an isolation layer, by 5 μm or more at the boundary between the DRAM where silicide is not formed and the logic region where silicide is formed is used. Unresolved, it only results in loss of area.

The present invention was created to solve the above problems, and an object of the present invention is to form a barrier between an oxide film, which is an interlayer insulating film, and polysilicon having a high etching selectivity between a logic region and a peripheral circuit part of a composite semiconductor device. The present invention provides a method for manufacturing a composite semiconductor device capable of improving the characteristics of the device by etching the insulating film by a wet method.

1A to 1E are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to an embodiment of the present invention.

-Explanation of symbols for the main parts of the drawings-

11,41: semiconductor substrate 13,43: device isolation film

15,45: word line, polysilicon layer 17,47: insulating film spacer

19,49: contact pad 21,51: wet etch stop layer

23,55: First interlayer insulating film 25,59: Second interlayer insulating film

27, 57: bit line 29: third interlayer insulating film

31: fourth interlayer insulating film 33,63: capacitor

35, 67 silicide 53: first photosensitive film pattern

61: capacitor contact plug 65: second photosensitive film pattern

100: non-silicide region, region where no silicide is formed

200: silicide region, logic section

According to an aspect of the present invention, a contact pad is formed in a cell portion of an upper portion of a semiconductor substrate on which a device isolation layer and a word line are formed, a wet etch stop layer is formed on an entire surface, and a first surface is formed on an entire surface. Forming a first interlayer insulating film, a bit line, and a second interlayer insulating film, and forming a capacitor contact plug connected to a contact pad on a semiconductor substrate and a capacitor contact plug formed on a wet etch stop layer, on the wet etch stop layer. The formed capacitor contact plug is formed at a boundary between a peripheral circuit portion and a logic portion to use as a guard ring, forming a capacitor only on an upper portion of the contact plug connected to the contact pad, and wetting the first and second interlayer insulating layers of the logic portion. Etching and dry etching the wet etch stop layer in a subsequent process, and then forming silicide in the logic portion. It characterized by comprising.

On the other hand, the principle of the present invention for achieving the above object is a nitride film or polysilicon used as a wet etch stop layer when removing the oxide side of the logic side on the device isolation layer of the logic side of the silicide is formed and the DRAM interface is not formed silicide By not removing the film, the phenomenon that the device isolation film is removed from the interface by side etching is prevented first. In addition, a polysilicon layer used for forming a capacitor in the DRAM is formed on the upper portion of the DRAM during the DRAM process to fundamentally prevent the etching solution from penetrating into the region where the silicide should not be formed.

As a result, it is possible to eliminate the phenomenon in which the device isolation film at the interface or the silicide is formed at a region where silicide is not to be formed near the interface, thereby preventing electrical short circuits and leakage. In addition, the polysilicon layer formed on the device isolation layer or the gate oxide layer, that is, the word line, may be prevented from falling off, and the photosensitive layer may be prevented from falling off or collapsing. In addition, the present invention may also be applied to fabricating MML products using DRAMs, for example, trench capacitors, which do not use poly 3 layers or poly 4 layers. In addition, placing a dummy polysilicon line (dummy poly 1 line) on the boundary wall between the silicide region and the region where the silicide should not be formed is more effective to solve the problem, which is a diffusion path of the etching solution using the high thickness of the polysilicon line Because it can increase.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2A to 2F are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to an embodiment of the present invention, wherein a logic portion, which is a region 200 in which silicide is formed, and a cell portion, which is a non-silicide region 100, in which a silicide is not formed, are shown. And a peripheral circuit portion is shown.

First, as shown in FIG. 2A, an isolation layer 43 is formed on a semiconductor substrate 41, and a gate electrode is formed in a stacked structure of a gate oxide film, a gate electrode conductor 45, and a mask insulating film.

The first oxide film is deposited on the entire surface, and the first oxide film 47 is anisotropically etched from the peripheral circuit portion and the logic portion to form the first oxide film spacer 47.

A photoresist pattern is formed to expose the source / drain junction regions of the peripheral circuit portion and the logic portion, and impurities are implanted into the peripheral circuit portion and the logic portion to form the source / drain junction region.

Then, the photoresist pattern is removed, and a second oxide film is formed on the entire surface at a constant thickness.

The second oxide film of the cell portion is anisotropically etched to form a spacer having a first oxide film and a second oxide film stacked structure.

Then, a contact pad 49 connected to the source / drain junction region of the cell portion is formed using a self-aligned contact process, but a polysilicon film is formed.

The wet etch stop layer 51 is formed in the logic unit. At this time, the wet etching barrier layer 51 is formed of a nitride film because it is difficult to control the etching amount during the wet etch process of removing the oxide layer of the logic unit.

In this case, the wet etch stop layer 51 forms a first photoresist pattern 53 exposing the cell portion and the peripheral circuit portion, that is, the non-silicide region 100, and etches the etch stop layer 51 by using the mask as a mask. The wet etch stop layer 51 is left only in the logic part which is the region 200.

Next, as shown in FIG. 2B, a first interlayer insulating layer 55 is formed over the entire surface, and a bit line 57 connected to a bit line contact pad is formed among the contact pads 49.

As shown in FIG. 2C, the second interlayer insulating layer 59 is formed on the entire surface, and the capacitor contact plugs 61 are disposed on the capacitor contact pads 49 and the wet etch stop layer 51 between the peripheral circuit portion and the logic portion boundary. ).

In this case, the capacitor contact plug 61 formed on the wet etch stop layer 51 serves as a guard-ring for suppressing side etching during the wet etching process of the oxide film, which is an interlayer insulating film.

Next, as shown in FIG. 2D, a capacitor 63 connected to the contact plug 61 connected to the contact pad 49 of the cell portion is formed.

As shown in FIG. 2E, a second photoresist pattern 65 exposing the silicide formation region 200 is formed on the cell portion and the peripheral circuit portion, which are the non-silicide regions 100.

Then, the first and second interlayer insulating films 55 and 59 of the logic part, which are the silicide formation region 200, are etched using the second photoresist pattern 65 as a mask.

In this case, the capacitor contact plug 61 is used as a side etch barrier for preventing etching of the interlayer insulating films 55 and 59 of the peripheral circuit portion.

Subsequently, as illustrated in FIG. 2F, the second photoresist layer pattern 65 is removed, and the silicide 67 is formed on the semiconductor substrate of the logic unit and the silicide formation region 200.

As described above, the method of manufacturing the composite semiconductor device according to the embodiment of the present invention can completely prevent the etching solution from penetrating into the an-silicide region by using an oxide film, which is an interlayer insulating film, and a material having a high selective etching ratio. As a result, three conventional problems, namely, a device isolation film at an interface is removed during a wet etching process, and silicides are formed in a subsequent process to prevent electrical short-circuits and leakage, and a word of polysilicon near the interface is prevented. It can also prevent the line from falling off or the photoresist falling off.

Another embodiment of the present invention is to form a contact plug on the wet etch stop layer during the bit line contact process.

Another embodiment of the present invention is to form a dummy word line, that is, a polysilicon line on the interface between the peripheral circuit portion and the logic portion, thereby increasing the side diffusion path to minimize the etching of the peripheral circuit portion. At this time, the polysilicon line serves as a kind of guard ring.

In addition, a capacitor may be formed on the contact plug on the interface between the peripheral circuit portion and the logic portion.

The wet etch stop layer may be formed of a nitride film or polysilicon having a high etching selectivity difference from the first and second interlayer insulating films formed of an oxide film series.

As described above, the present invention provides a side etch guard structure using a nitride layer or a poly layer, which is used as a wet etch stop layer when the oxide layer is removed, and a poly 3 contact and a poly 3 layer, which are used to form a capacitor in a DRAM. By forming a C, it essentially blocks the etch solution from penetrating into the non-silicide region and minimizes the loss of DRAM and logic boundary area without further processing, and electrical short-circuit and leakage currents that can occur due to silicide of the non-silicide region Since the malfunction due to the generation can be prevented, there is an advantage that the cost can be reduced and the yield can be improved.

In addition, it is possible to prevent the polysilicon lines formed on the oxide film from falling off, and furthermore, since the oxide film of the photoresist film is removed by side etching to prevent the photoresist film from falling off or collapse, the process stability and other equipments. There is an advantage that can prevent the contamination of.

Claims (6)

Forming a contact pad on an upper portion of the semiconductor substrate on which the device isolation layer and the word line are formed; Forming a wet etch stop layer over the entire surface, Forming a first interlayer insulating film, a bit line, and a second interlayer insulating film on the entire surface; A capacitor contact plug connected to the contact pad on the semiconductor substrate and a capacitor contact plug formed on the wet etch stop layer are formed, and the capacitor contact plug formed on the wet etch stop layer is formed at a boundary between the peripheral circuit part and the logic part. And using it as a guard ring, Forming a capacitor only on an upper portion of the contact plug connected to the contact pad; Etching the first and second interlayer dielectric layers of the logic unit by a wet method, and dry etching the wet etch stop layer by a subsequent process, and then forming silicide in the logic unit Method for manufacturing a composite semiconductor device comprising the. The method of claim 1, wherein the contact plug on the wet etch stop layer is formed during a bit line contact process. The method of claim 1, wherein a word line dummy pattern, which is a polysilicon layer, is formed at a boundary between a peripheral circuit portion and a logic portion instead of the contact plug on the wet etch stop layer. The method of claim 1, wherein a capacitor is formed on the contact plug on an interface between the peripheral circuit portion and the logic portion. The method of claim 1, wherein the wet etch stop layer is A method for manufacturing a composite semiconductor device, characterized in that it is formed of a nitride film or polysilicon. The method of claim 1, wherein the first and second interlayer insulating films are formed. A method for manufacturing a composite semiconductor device, characterized in that formed of an oxide-based insulating material.