KR20040001128A - Method for forming the DRAM memory cell - Google Patents
Method for forming the DRAM memory cell Download PDFInfo
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- KR20040001128A KR20040001128A KR1020020036228A KR20020036228A KR20040001128A KR 20040001128 A KR20040001128 A KR 20040001128A KR 1020020036228 A KR1020020036228 A KR 1020020036228A KR 20020036228 A KR20020036228 A KR 20020036228A KR 20040001128 A KR20040001128 A KR 20040001128A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
Description
본 발명은 디램 메모리 셀의 제조방법에 관한 것으로, 보다 상세하게는 평탄 커패시터 플레이트와 워드라인을 하나로 통합하여 평판 구조의 디램 셀 면적을 줄일 수 있어 반도체소자의 제조 수율을 향상 시킬 수 있도록 하는 디램 메모리 셀의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a DRAM memory cell, and more particularly, a DRAM memory, which integrates a flat capacitor plate and a word line into one to reduce the area of a DRAM cell having a flat plate structure, thereby improving a manufacturing yield of a semiconductor device. It relates to a method for producing a cell.
일반적으로 MOS(Metal-Oxide-Semiconductor, 이하 MOS 이라 칭함)형 DRAM(Dynamic Random Access Memory, 이하 DRAM 이라 칭함)은 하나의 MOS 트랜지스터 및 하나의 커패시터로 이루어진 메모리 셀(Memory Cell)을 갖는다.In general, a MOS (Metal-Oxide-Semiconductor) type DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) has a memory cell consisting of one MOS transistor and one capacitor.
최근 반도체 집적회로 공정 기술이 발달함에 따라 반도체 기판 상에 제조되는 소자의 최소 선폭 길이는 더욱 미세화되고, 단위 면적당 집적도는 증가하고 있다. 한편, 메모리 셀의 집적도가 증가함에 따라서 전하 저장용 셀 커패시터가 점유 할 수 있는 공간은 더욱 좁아지게 되므로, 단위 면적당 정전 용량이 증대된 셀 커패시터의 개발이 필수적이다.With the recent development of semiconductor integrated circuit processing technology, the minimum line width length of devices fabricated on a semiconductor substrate is further miniaturized, and the degree of integration per unit area is increasing. On the other hand, as the density of memory cells increases, the space that can be occupied by the cell capacitor for charge storage becomes narrower. Therefore, it is essential to develop a cell capacitor with increased capacitance per unit area.
도 1은 종래 기술에 따른 디램 메모리 셀의 제조방법에 의해 제조된 디램 메모리 셀의 구조를 나타낸 단면도이다.1 is a cross-sectional view illustrating a structure of a DRAM memory cell manufactured by a DRAM memory cell manufacturing method according to the related art.
도 1에 도시된 바와 같이, 비트라인 콘택(5)을 중심으로 얇은 게이트산화막(3)을 기반으로 구성된 워드라인(7)이 양쪽에 형성되고, 이 워드라인(7)에 인접하여 모스 커패시터(8)가 형성된다.As shown in FIG. 1, word lines 7 formed on the basis of the bit line contacts 5 based on the thin gate oxide film 3 are formed on both sides thereof, and adjacent to the word lines 7, a MOS capacitor ( 8) is formed.
또한, 상기 워드라인(7)과 모스 커패시터(8) 사이는 게이트 스페이서(11)로 격리되어 있고, 그 격리된 부분에 셀 정션(12)이 형성되어있다.In addition, the word line 7 and the MOS capacitor 8 are separated by a gate spacer 11, and a cell junction 12 is formed in the isolated portion.
그러나, 상기와 같은 종래의 디램 메모리 셀의 구조는 워드라인(7)과 모스 커패시터(8) 격리를 위해 스페이서(11)를 형성하여야 할 추가 면적이 필요한 문제점이 있었다.However, the conventional DRAM memory cell has a problem in that an additional area for forming the spacer 11 is required to isolate the word line 7 and the MOS capacitor 8.
또한, 상기 워드라인(7)과 모스 커패시터(8) 사이를 격리한 부분에 셀 정션(12)이 형성됨으로써, 디램 동작 시, 셀 정션(12)으로 흐르게 되는 누설전류에 의해 디램 리프레쉬 특성을 악화시키는 문제점이 있었다.In addition, since the cell junction 12 is formed in an area between the word line 7 and the MOS capacitor 8, the DRAM refresh characteristic is deteriorated due to leakage current flowing to the cell junction 12 during the DRAM operation. There was a problem letting.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 기존의 비트라인 콘택을 중심으로 워드라인이 양쪽에 배치되고, 바로 인접하여 모스 커패시터가 배치되어있는 구조에 있어서, 평탄 커패시터 플레이트와 워드라인을 하나로 통합하여 셀면적을 줄이도록 하는 것으로 워드라인 영역의 게이트절연막을 두껍게 형성하여 커패시터 플레이트 중 워드라인을 사용될 부분의 하부 문턱전압을 높여 대기상태일 때 커패시터와 비트라인과의 격리가 가능하도록 하여 기존의 공정 단계에서 간단히 레이아웃의 변경 만으로 평판 구조의 디램 셀 면적을 줄일 수 있도록 하는 디램 메모리 셀의 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is a flat structure in which a word line is disposed on both sides of an existing bit line contact and a MOS capacitor is disposed immediately adjacent to each other. The capacitor plate and the word line are integrated to reduce the cell area. The gate insulating film in the word line area is thickened to increase the lower threshold voltage of the part where the word line is to be used. The present invention provides a method of manufacturing a DRAM memory cell that allows isolation to reduce a DRAM cell area of a flat panel structure by simply changing the layout in an existing process step.
도 1은 종래 기술에 따른 디램 메모리 셀을 설명하기 위해 디램 메모리 셀 어레이를 나타낸 평면도이다.1 is a plan view illustrating a DRAM memory cell array in order to describe a DRAM memory cell according to the related art.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 디램 메모리 셀의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 실리콘 기판 102 : 소자분리막100 silicon substrate 102 device isolation film
104 : 워드라인의 게이트산화막104: gate oxide film of word line
106 : 커패시터의 하부 전극으로 사용되는 게이트산화막106: gate oxide film used as the lower electrode of the capacitor
108 : 커패시터 전극 110 : 스페이서108: capacitor electrode 110: spacer
112 : 소오스/드레인 전극 114 : 실리사이드층112 source / drain electrode 114 silicide layer
116 : 층간절연막 118 : 금속플러그116: interlayer insulating film 118: metal plug
120 : 비트라인120: bit line
상기 목적을 달성하기 위하여, 본 발명은 소자분리막이 형성된 실리콘 기판 상에 듀얼 게이트 산화 마스크를 이용하여 듀얼 게이트 산화막을 형성하는 단계와, 상기 결과물 상에 워드라인과 커패시터 형성을 위한 다결정 실리콘을 증착한 후, 노광 및 식각 공정을 진행하여 커패시터 전극을 형성하는 단계와, 상기 커패시터 전극 측벽에 게이트 스페이서를 형성하고, 소오스/드레인 전극에 이온을 도핑하여 비트라인 정션을 형성하는 단계와, 상기 커패시터 전극 상부에 실리사이드층을 형성한 후, 결과물 전체에 층간절연막을 증착하는 단계와, 상기 층간절연막 상에 비트라인 콘택 형성을 위한 감광막 패턴을 형성한 후, 이를 식각마스크로 식각하여 비트라인 콘택홀을 형성하는 단계와, 상기 비트라인 콘택홀을 금속으로 매립하여 금속플러그를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 디램 메모리 셀의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a dual gate oxide film using a dual gate oxide mask on the silicon substrate on which the device isolation film is formed, and depositing polycrystalline silicon for word line and capacitor formation on the resultant And forming a capacitor electrode by performing an exposure and etching process, forming a gate spacer on the sidewall of the capacitor electrode, and forming a bit line junction by doping ions to a source / drain electrode, and forming an upper portion of the capacitor electrode. Forming a silicide layer on the substrate, depositing an interlayer insulating film on the entire resultant, forming a photoresist pattern for forming a bitline contact on the interlayer insulating film, and then etching the same using an etching mask to form a bitline contact hole And filling the bit line contact hole with metal to form a metal plug. Provides a method of manufacturing a DRAM memory cell, characterized in that it comprises a step.
바람직하게 본발명은 상기 워드라인과 커패시터 전극은 듀얼 게이트 산화막으로 공통으로 사용하며, 상기 듀얼 게이트 산화막은 워드라인에 해당하는 부분의 게이트 산화막이 커패시터 하부전극으로 사용되는 게이트 산화막 보다 10~100배 더 두껍게 형성되는 것을 특징으로 한다.Preferably, the word line and the capacitor electrode are commonly used as the dual gate oxide layer, and the dual gate oxide layer is 10 to 100 times more than the gate oxide layer where the gate oxide layer corresponding to the word line is used as the capacitor lower electrode. It is characterized by being formed thick.
바람직하게 본발명은 데이터를 읽거나 쓸 때 커패시터 하부전극으로 사용되는 게이트 산화막에 인가되는 전압은 워드라인에 해당하는 부분의 게이트 산화막의 문턱전압보다 더 크게 인가하며, 데이터를 유지하고 있을 때 커패시터 하부전극으로 사용되는 게이트 산화막에 인가되는 전압은 워드라인에 해당하는 부분의 문턱전압보다 더 낮게 인가해 주는 것을 특징으로 한다.Preferably, the present invention applies the voltage applied to the gate oxide film used as the capacitor lower electrode when reading or writing data to be greater than the threshold voltage of the gate oxide film of the portion corresponding to the word line. The voltage applied to the gate oxide used as the electrode is characterized in that the lower than the threshold voltage of the portion corresponding to the word line.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 디램 메모리 셀의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 실리콘기판(100) 내에 소자간 격리를 위한 소자분리막(102)을 형성하고, 실리콘기판(100) 상부에 듀얼 게이트 산화 마스크(미도시함)를 사용하여 워드라인이 형성될 부분만 두껍게 워드라인의 게이트산화막(104)을 형성한 후, 커패시터의 하부 전극으로 사용되는 게이트 산화막(106)은 얇게 형성한다.As shown in FIG. 2A, the device isolation layer 102 is formed in the silicon substrate 100 to isolate the devices, and a word line is formed by using a dual gate oxide mask (not shown) on the silicon substrate 100. After the gate oxide film 104 of the word line is formed thick only in the portion to be formed, the gate oxide film 106 used as the lower electrode of the capacitor is formed thin.
이때, 워드라인과 커패시터 전극은 공통으로 사용하며, 상기 듀얼 게이트 산화막은 워드라인에 해당하는 부분의 게이트 산화막(104)이 커패시터 하부전극으로 사용되는 게이트 산화막(106) 보다 10~100배 더 두껍게 형성한다. 즉, 동작 전압이 커패시터에 인가되었을 경우 두껍게 형성된 워드라인의 게이트산화막(104) 부분의 게이트 문턱전압은 동작 전압보다 높게 형성시켜 동작 전압 이하에서도 커패시터 하부전극의 전하가 빠져나가지 못하도록 구성된다.In this case, the word line and the capacitor electrode are commonly used, and the dual gate oxide layer is formed to be 10 to 100 times thicker than the gate oxide layer 106 used as the capacitor lower electrode. do. That is, when the operating voltage is applied to the capacitor, the gate threshold voltage of the gate oxide film 104 of the thick word line is formed higher than the operating voltage so that the charge of the lower electrode of the capacitor does not escape even below the operating voltage.
그리고, 데이터를 읽거나 쓸 때 커패시터 하부전극으로 사용되는 게이트 산화막(106)에 인가되는 전압은 워드라인에 해당하는 부분의 게이트 산화막(104)의 문턱전압보다 더 크게 인가하여 워드라인에 해당하는 부분의 게이트 산화막(104)이턴온(Turn On)되게 한다.When the data is read or written, the voltage applied to the gate oxide film 106 used as the capacitor lower electrode is greater than the threshold voltage of the gate oxide film 104 corresponding to the word line to correspond to the word line. The gate oxide film 104 is turned on.
이어서, 도 2b에 도시된 바와 같이, 상기 결과물 상에 워드라인과 커패시터 형성을 위한 다결정 실리콘을 증착한 후, 노광 및 식각 공정을 진행하여 커패시터 전극(108)을 형성한다. 이때, 상기 커패시터 전극(108) 끝부분은 워드라인에 해당하는 부분의 게이트 산화막(104)의 끝부분과 일치되도록 형성한다.Subsequently, as illustrated in FIG. 2B, polycrystalline silicon for forming a word line and a capacitor is deposited on the resultant, and then an exposure and etching process is performed to form the capacitor electrode 108. At this time, the end of the capacitor electrode 108 is formed to match the end of the gate oxide film 104 of the portion corresponding to the word line.
그 후, 상기 결과물 상에 절연물을 증착한 후, 이방성 건식 식각 공정을 진행하여 커패시터 전극 측벽에 스페이서(110)를 형성한다.Thereafter, after depositing an insulating material on the resultant, an anisotropic dry etching process is performed to form spacers 110 on the sidewalls of the capacitor electrodes.
그리고, 도 2c에 도시된 바와 같이, 상기 실리콘기판(100) 내에 이온을 주입 임플란트 공정을 실시하여 소오스/드레인 전극(112)을 형성한 후, 상기 커패시터 전극(108) 상부에 커패시터 전극(108)의 저항을 낮추기 위해 실리사이드층(114)을 형성한다.As shown in FIG. 2C, after implanting ions into the silicon substrate 100 to form a source / drain electrode 112, the capacitor electrode 108 is disposed on the capacitor electrode 108. In order to lower the resistance of the silicide layer 114 is formed.
이어서, 상기 결과물 전체에 후속 공정에 의해 형성될 비트라인과 커패시터 전극 간의 절연을 위해 층간절연막(116)을 증착하고, 그 층간절연막(116) 상에 비트라인 콘택 형성을 위한 감광막 패턴(미도시함)을 형성한 후, 이를 식각마스크로 식각하여 비트라인 콘택홀(미도시함)을 형성한다.Subsequently, an interlayer insulating film 116 is deposited on the entire resultant to insulate between the bit line and the capacitor electrode to be formed by a subsequent process, and a photoresist pattern (not shown) for forming a bit line contact on the interlayer insulating film 116. ), And then etched with an etching mask to form a bit line contact hole (not shown).
그 후, 상기 비트라인 콘택홀(미도시함)을 금속으로 매립하여 금속플러그(118)를 형성한 후, 결과물 전체에 금속을 증착하여 비트라인(120)을 형성한다.Thereafter, the bit line contact hole (not shown) is filled with metal to form a metal plug 118, and then metal is deposited on the entire resultant to form the bit line 120.
따라서, 상기한 바와 같이, 본 발명에 따른 디램 메모리 셀의 제조방법을 이용하게 되면 평탄 커패시터 플레이트와 워드라인이 하나로 통합되어 기존의 공정 단계에서 간단히 레이아웃의 변경만으로 평판 구조의 디램 셀 면적을 줄일 수 있어 반도체소자의 제조 수율을 향상시킬 수 있을 뿐만 아니라 워드라인 영역의 게이트절연막을 두껍게 형성하여 커패시터 플레이트 중 워드라인을 사용될 부분의 하부 문턱전압을 높여 대기상태일 때 커패시터와 비트라인과의 격리가 가능하도록 하여 디램 동작 시, 셀 정션으로 흐르게 되는 누설전류를 방지하여 디램 리프레쉬 특성을 향상시킬 수 있다.Therefore, as described above, when the DRAM memory cell manufacturing method according to the present invention is used, the flat capacitor plate and the word line are integrated into one, thereby reducing the DRAM cell area of the flat panel structure by simply changing the layout in an existing process step. In addition, it is possible to improve the manufacturing yield of semiconductor devices and to form a thick gate insulating film in the word line region to increase the lower threshold voltage of the portion where the word line is to be used in the capacitor plate, so that the capacitor and the bit line can be isolated in the standby state. By preventing the leakage current flowing to the cell junction during DRAM operation, the DRAM refresh characteristic can be improved.
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