KR100849188B1 - Method for manufacturing semiconductor device with recess gate - Google Patents

Abstract

A method for manufacturing a semiconductor device having a recess gate is provided to improve the refresh characteristic and yield of a device by reducing a height of a horn which is generated at an interface of an isolation layer and a recess. A hard mask pattern for a recess is formed on a semiconductor substrate(31). The semiconductor substrate is first-etched by using the hard mask pattern as an etch barrier to form a first recess(37a). The first-etching process is performed by using a mixed plasma made of a primary etch gas to which H2 gas is added, so that a sidewall of the first recess has a vertical profile and a passivation layer is formed on the sidewall of the first recess through a plasma reaction. The semiconductor substrate under the first recess is second-etched by using the passivation layer as an etch barrier to form a second recess(37b) having a bowing profile substantially. The primary etch gas is Cl2/N2 gas.

Description

A method of manufacturing a semiconductor device having a recess gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESS GATE}

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to the prior art.

2 shows a profile of a recess pattern according to the prior art;

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with an embodiment of the present invention.

4 illustrates a profile of a first recess pattern and a passivation film on sidewalls thereof according to an embodiment of the present invention.

Figure 5 is a view for comparing the recess pattern according to the embodiment of the present invention with the recess pattern according to the prior art.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: hard mask oxide film 34: hard mask amorphous carbon film

35 antireflection film 36 photoresist pattern

37: recess 38: passivation film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device having a recess gate.

In recent years, as semiconductor devices have become highly integrated, as the cell transistor channel length decreases and the ion implantation doping concentration of the substrate increases, junction leakage increases due to an increase in electric field. In the conventional planar transistor structure, it is difficult to secure the refresh characteristics of the device.

In order to solve this problem, by forming a gate on a recess formed by etching a predetermined portion of the active region of the semiconductor substrate, the refresh characteristics of the device can be improved by increasing the cell transistor channel length and decreasing the ion implantation doping concentration. A three-dimensional recess gate process has been introduced.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to the prior art.

As shown in FIG. 1A, an isolation layer 12 is formed on the semiconductor substrate 11 to define an active region. The device isolation layer 12 may be formed by, for example, a shallow trench isolation (STI) process.

Subsequently, a hard mask oxide film 13 and a hard mask amorphous carbon film 14 are sequentially formed on the semiconductor substrate 11. The hard mask oxide layer 13 and the hard mask amorphous carbon layer 14 serve as an etching barrier during an etching process for forming subsequent recesses.

Next, a photoresist pattern 16 is formed on the hard mask amorphous carbon film 14 to expose a region where the recess is to be formed. An antireflection film 15 may be interposed below the photoresist pattern 16 to prevent reflection during the exposure process.

As shown in FIG. 1B, the hard mask amorphous carbon film 14 is etched using the photoresist pattern 16 as an etching mask.

As shown in FIG. 1C, the hard mask oxide layer 13 and the semiconductor substrate 11 are sequentially etched using the etched hard mask amorphous carbon film 14 as an etch barrier to form a recess 17.

Subsequently, although not shown in the specification, after the hard mask amorphous carbon film 14 and the etched hard mask oxide film 13 are removed in a subsequent process, the gate oxide film is formed on the entire surface of the substrate 11 including the recess 17. (Not shown) and forming a gate pattern (not shown) on the gate oxide film, part of which is embedded in the recess 17 and the other protruding over the surface of the substrate 11. The set gate process is terminated.

However, as the trend of ultra-high integration of semiconductor devices has recently been further increased, the pattern size has been further reduced. Therefore, when the conventional technology is applied, a bottom-shaped profile (V-Shape) has a profile when etching to form a recess. A recess is formed, whereby a horn of a point shape is generated at the boundary between the device isolation layer and the recess. The reason for the occurrence of the horn is that when the device isolation film is formed by the STI process, the STI angle is 90 ° or less for the insulating gap gap-fill in the trench for device isolation. This is because the size of the recess has a sharp profile due to the decrease in size, and thus the degree of residual of Si is large between the device isolation layer and the recess.

2 is a view showing a profile of a recess pattern according to the prior art.

Referring to Figure 2 it can be seen that the recess pattern has a pointed profile (see upper figure). In addition, when looking at the boundary between the device isolation layer and the recess, it can be seen that a sharp horn (see A) has occurred. Since the recess pattern has a sharp profile, the residual Si is large and the height of the horn is very high. It can be seen (see the lower figure).

These horns cause deterioration of the characteristics of the gate oxide film, and thus become concentration points of stress, resulting in leakage currents, thereby degrading the refresh characteristics of the device and lowering the yield in manufacturing the device. Generates. Therefore, there is a need for a technique capable of reducing the height of the horns.

The present invention has been proposed to solve the above problems of the prior art, by forming a recess having a dual profile of the upper and lower profiles are different through two-step etching during the etching for forming the recess. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a recess gate capable of reducing the height of the horn generated at the boundary between the device isolation layer and the recess.

A method of manufacturing a semiconductor device having a recess gate of the present invention for achieving the above object comprises the steps of: forming a hard mask pattern for a recess on an upper surface of a semiconductor substrate; The first substrate is formed by first etching the semiconductor substrate using the hard mask pattern as an etching barrier, and performing the first etching using a mixed plasma in which H ₂ gas is added to the stock corner gas. Forming a passivation film by a plasma reaction on the sidewall of the first recess while the recess sidewall has a vertical profile; And second etching the substrate under the first recess using the passivation layer as an etch barrier to form a second recess having a substantially bowing profile.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

As shown in FIG. 3A, an isolation layer 32 is formed on the semiconductor substrate 31. The device isolation layer 32 may be formed by an STI process.

Subsequently, the hard mask oxide film 33 and the hard mask amorphous carbon film 34 are sequentially formed on the semiconductor substrate 31 on which the device isolation film 32 is formed. The hard mask oxide layer 33 and the hard mask amorphous carbon layer 34 serve as an etching barrier during an etching process for forming subsequent recesses.

Next, a photoresist pattern 36 is formed on the hard mask amorphous carbon film 34 to expose the region to be recessed. An antireflection film 35 may be interposed below the photoresist pattern 36 to prevent reflection during the exposure process.

As shown in FIG. 3B, the hard mask amorphous carbon film 34 is etched using the photoresist pattern 36 as an etching mask. Here, the hard mask amorphous carbon layer 34 is etched using the hard mask oxide layer 33 as an etch stop layer, and is etched using a plasma source of Capacitively Coupled Plasma (CCP) or Magnetically Enhanced Reactive Ion Etching (MERIE) type. N ₂ / O ₂ plasma is used as the gas.

Subsequently, the semiconductor substrate 31 is exposed by etching the hard mask oxide layer 33 using the photoresist pattern 36 and the etched hard mask amorphous carbon layer 34 as an etch barrier. Here, the etching of the hard mask oxide film 33 is performed on the gas of CF _X / CHF _X. O ₂ It can be carried out using a mixed plasma with added gas.

As shown in FIG. 3C, the photoresist pattern 36 and the anti-reflection film 35 are removed.

Subsequently, the etched hard mask amorphous carbon film 34 is removed. Here, the removal of the hard mask amorphous carbon film 34 may be performed using an O ₂ plasma having a flow rate of 200 to 1000 sccm, and is preferably performed by applying only source power without applying bias power.

As shown in FIG. 3D, the semiconductor substrate 31 having the etched hard mask oxide layer 33 as an etch barrier is first etched to form a first recess 37a having a substantially vertical profile. do. It is preferable that the depth of the first recess 37a be 1000 to 1300 mm 3.

Here, the primary etching for forming the first recess 37a is performed using a mixed plasma in which H ₂ gas is added to the gas of Cl ₂ / N ₂ , which is a major etching gas. The flow rate of H ₂ gas to be added is preferred search is 30 ~ 100sccm. When the primary etching is performed using a mixed plasma in which H ₂ gas is added to the gas of Cl ₂ / N ₂ , the portion of the semiconductor substrate 11, that is, the sidewall of the first recess 37a that is simultaneously exposed as the etching proceeds The passivation film 38 by a plasma reaction is formed in FIG. 4 (refer FIG. 4). The passivation film 38 protects the exposed substrate during the first etching process, thereby helping to form the first recess 37a in a vertical profile, and in the subsequent process of forming the second recess 37b. Acts as an etch barrier.

This primary etching is performed using a TCP (Transformer Coupled Plasma) / ICP (Inductively Coupled Plasma) type plasma source, and the etching conditions are 5 to 20 mtorr pressure, 700 to 1500 W source power and 200 to 500 V bias. It is preferable to apply power. In addition, the primary etching is performed on Cl ₂ / N ₂ described above. It may also be performed by adding a gas such as CF _{x Hy-} based gas, for example CHF ₃ , CH ₂ F ₂ , to the mixed plasma to which H ₂ is added.

Although not shown in the drawings of this specification, 0 ₂ / N ₂ for the result after the passivation film 38 is formed. An oxide film (not shown) may be further formed on the passivation film 38 by plasma oxidation treatment using gas. This is because the etching margin of the passivation film 38 which acts as an etching barrier may be insufficient in the subsequent process of forming the second recess 37b. It is preferable that the thickness in which the passivation film 38 and the oxide film are laminated is 20-30 kPa.

As shown in Fig. 3E, when the hard mask oxide film 33 and at least the passivation film 38 (an additional oxide film by plasma oxidation is formed on the passivation film 38), the passivation film 38 and the oxide film are etch barriers. The second recess 37b is formed by second etching the semiconductor substrate 31 under the first recess 37a as an etching barrier. The second recess 37b may be formed to a depth of about 200 to about 500 mm 3.

At this time, the secondary etching is performed to have a weak isotropic etching characteristic, so that the second recess 37b has a bowing profile whose side is slightly inwardly curved, and consequently, the second recess 37b. Has a width that is extended by several tens to several tens of nm than the width of the first recess 37a.

This secondary etching is carried out using a plasma source of the TCP / ICP type, using an etching gas containing chlorine gas, bromine gas and florine gas, but the etching conditions 10 It is preferable to apply a pressure of ˜30 mtorr, a source power of 500 to 1000 W, and a bias power of 100 to 500 V. In particular, when using HBr / Cl ₂ / SF ₆ / O ₂ gas as an etching gas, it is preferable that the flow rate ratio is 9: 3: 13: 1.

The secondary etching process proceeds with the primary etching process and In-Situ.

The first recess 37a and the second recess 37b formed through the process of FIGS. 3D and 3E make the recess 37 having a dual profile having different upper and lower recess profiles. do. Since the recess 37 having such a dual profile has a profile of about a few tens to several tens of nm wide in the lower portion of the recess 37, the height of the horn is significantly reduced ( See the right figure of FIG. 5). That is, the height of the horn can be minimized even when the STI angle is less than 90 °. When the gate pattern is formed on the recess 37, leakage current is suppressed and the refresh characteristics of the device can be improved, so that the yield can be improved and the cost can be reduced during device manufacturing.

After the process of forming the second recess 37b, the hard mask oxide layer 33 and at least the passivation layer 38 are formed as etch barriers to the second recess 37b in order to further widen the lower portion of the recess 37. By performing isotropic etching (hereinafter, referred to as tertiary etching), the side of the second recess 37b may be further widened, thereby further reducing the height of the horn. As a result of the tertiary etching, the side surface of the second recess 37b may be widened, for example, by about 10 to 15 nm, and thus the profile of the second recess 37b having a boeing profile may be modified to be close to a spherical shape.

At this time, the third etching is performed using a plasma source of TCP / ICP type, using an etching gas in which a small amount of SF ₆ / O ₂ gas is mixed with a large amount of HBr / Cl ₂ gas, but the etching conditions of 20 ~ 100mtorr It is preferable to apply a pressure, a source power of 500-1500 W and a bias power of 50 W or less. At this time, SF ₆ NF _X Alternatively, CF _X gas may be used.

Subsequently, although not shown in the present specification, after the hard mask oxide layer 33 etched in a subsequent process is removed, a gate oxide layer (not shown) is formed on the entire surface of the substrate 31 including the recess 37. A semiconductor device having a recess gate according to an exemplary embodiment of the present invention by forming a gate pattern (not shown) partially embedded in the recess 37 and protruding over the surface of the substrate 31 on the gate oxide layer. The manufacturing method of is terminated.

Although the primary, secondary or tertiary etching according to the embodiment of the present invention described above is performed in a high-density etching equipment using a plasma source of the TCP / ICP type, another embodiment may exist. For example, primary etching, secondary etching, or tertiary etching may be performed in an ICP type etching apparatus equipped with a Faraday Shield, or may include MDS (Microwave Down Stream), ECR (Electron Cyclotron Resonance), It may be performed in any one of the etching equipment using the plasma type of the helical type.

4 illustrates a profile of a first recess pattern and a passivation film on sidewalls thereof according to an embodiment of the present invention.

Referring to FIG. 4, when the H ₂ gas is added to the Cl ₂ / N ₂ gas to etch the semiconductor substrate, a passivation film is formed on the sidewall of the recess by a plasma reaction at the same time as the recess is formed.

5 is a diagram for comparing a recess pattern according to the related art with a recess pattern according to an exemplary embodiment of the present invention.

Referring to the left side of FIG. 5, it can be seen that the recess pattern according to the related art has a pointed profile at the bottom, and thus, the horns of the point shape are very high at the boundary between the device isolation layer and the recess. On the other hand, referring to the right side of FIG. 5, since the recess pattern according to the exemplary embodiment of the present invention has a dual profile having a wider width at the bottom than the top, the height of the horns occurring at the boundary between the device isolation layer and the recess is increased. It can be seen that it is significantly lower.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the method of manufacturing a semiconductor device having a recess gate according to the present invention, a recess having a dual profile having different upper and lower profiles is formed through two-step etching during etching for forming a recess. As a result, the height of the horn generated at the boundary between the device isolation layer and the recess can be reduced to improve the refresh characteristics of the device and the yield in manufacturing the device.

Claims (20)

Forming a hard mask pattern for a recess on the semiconductor substrate; The first substrate is formed by first etching the semiconductor substrate using the hard mask pattern as an etching barrier, and performing the first etching using a mixed plasma in which H ₂ gas is added to the stock corner gas. Forming a passivation film by a plasma reaction on the sidewall of the first recess while the recess sidewall has a vertical profile; And Second etching the substrate under the first recess using the passivation layer as an etching barrier to form a second recess having a substantially bowing profile Method for manufacturing a semiconductor device comprising a. The method of claim 1, The stock angle gas is Cl ₂ / N ₂ gas Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first recess and the passivation film forming step, Is performed by further adding a CF _x H _y- based gas to the mixed plasma. Method of manufacturing a semiconductor device. The method of claim 3, The CF _x H _y -based gas is CHF ₃ or CH ₂ F ₂ Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first recess and the passivation film forming step, Using a plasma source of TCP / ICP type, Is performed by applying a pressure of 5-20 mtorr, a source power of 700-1500 W and a bias power of 200-500 V Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The depth of the first recess is 1000 ~ 1300Å Method of manufacturing a semiconductor device. The method according to claim 1 or 2, After the first recess formation and passivation film forming step, Forming an oxide film by plasma oxidation on the passivation film; The second recess forming step may include The passivation film and the oxide film by the plasma oxidation process are performed using an etching barrier. Method of manufacturing a semiconductor device. The method of claim 7, wherein The plasma oxidation treatment is performed using a gas of O ₂ / N ₂ Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The second recess forming step may include Using a mixed plasma containing chlorine gas, bromine gas and florin gas Method of manufacturing a semiconductor device. The method of claim 9, The mixed plasma is HBr / Cl ₂ / SF ₆ / O ₂ gas Method of manufacturing a semiconductor device. The method of claim 9, The second recess forming step may include Using a plasma source of TCP / ICP type, It is performed by applying pressure of 10 ~ 30mtorr, source power of 500 ~ 1000W and bias power of 100 ~ 500V Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The depth of the second recess is 200 ~ 500Å Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first etching and the second etching is performed in situ Method of manufacturing a semiconductor device. The method according to claim 1 or 2, After the second recess forming step, Performing isotropic etching the passivation layer as an etch barrier to extend the side surface of the second recess. Method of manufacturing a semiconductor device further comprising. The method of claim 14, The isotropic etching is, HBr / Cl ₂ to Is performed using a mixed plasma with SF ₆ / O ₂ gas Method of manufacturing a semiconductor device. The method of claim 15, The isotropic etching is, Using a plasma source of TCP / ICP type, Is performed by applying a pressure of 20 to 100 mtorr, a source power of 500 to 1500 W, and a bias power of 50 W or less. Method of manufacturing a semiconductor device. The method of claim 15, The SF ₆ gas can be replaced with NF _X or CF _X gas Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The hard mask pattern is made of an oxide film Method of manufacturing a semiconductor device. The method of claim 18, The hard mask pattern forming step, Forming a hard mask oxide film and a hard mask amorphous carbon film on the semiconductor substrate; Forming a photoresist pattern on the hardmask amorphous carbon film to expose a region to be recessed; Etching the hard mask amorphous carbon layer using the photoresist pattern as an etching mask; Etching the hard mask oxide layer using the etched hard mask amorphous carbon layer as an etching barrier to expose the semiconductor substrate; And Removing the etched hard mask amorphous carbon film. Method of manufacturing a semiconductor device. The method of claim 19, Removing the etched hard mask amorphous carbon film, Using O ₂ plasma, Performed by applying only source power without bias power Method of manufacturing a semiconductor device.

Images