KR20080087442A - Method for forming recess gate of semiconductor device - Google Patents

Method for forming recess gate of semiconductor device Download PDF

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Publication number
KR20080087442A
KR20080087442A KR1020070029688A KR20070029688A KR20080087442A KR 20080087442 A KR20080087442 A KR 20080087442A KR 1020070029688 A KR1020070029688 A KR 1020070029688A KR 20070029688 A KR20070029688 A KR 20070029688A KR 20080087442 A KR20080087442 A KR 20080087442A
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KR
South Korea
Prior art keywords
groove
horn
gate
etching
film
Prior art date
Application number
KR1020070029688A
Other languages
Korean (ko)
Inventor
박정훈
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070029688A priority Critical patent/KR20080087442A/en
Publication of KR20080087442A publication Critical patent/KR20080087442A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A method for forming a recess gate of a semiconductor device is provided to prevent the decrease of a channel length due to a horn by removing the horn generated in forming a recess gate before a gate dielectric is formed. A sidewall oxide layer(102) and a linear nitride layer(104) are formed sequentially on a surface of a trench. A semiconductor substrate(100) has an isolation layer(108) that defines an active region. A dielectric(106) is formed on the linear nitride layer to gap-fill the trench. A gate mask is formed on the semiconductor substrate, The hard mask exposes a gate forming region in the active region. The gate forming region of the exposed active region is etched to form a groove(A). A horn(H) is generated at an edge of a lower surface of the groove. The sidewall oxide layer part is firstly recessed to expose the horn part. The horn at the edge on the groove lower surface is removed to secondly recess the sidewall oxide layer part adjacent to the edge of the groove lower surface. A gate dielectric(120) is formed on a surface of the groove.

Description

Method for forming recess gate of semiconductor device

1A to 1F are cross-sectional views illustrating processes of forming a recess gate of a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 102 sidewall oxide film

104: linear nitride film 106: insulating film

 T: trench 108: device isolation film

110: buffer oxide film 112: nitride film

114: amorphous carbon film 116: antireflection film

118: hard mask film 120: gate insulating film

122: gate conductive film 124: gate hard mask film

126: gate H: horn

 A: Home

The present invention relates to a method of forming a recess gate of a semiconductor device, and more particularly, to a method of forming a recess gate capable of preventing a decrease in refresh and an increase in cell resistance which may be caused by a horn.

As the integration of semiconductor devices proceeds, there is a considerable difficulty due to the reduction of the threshold voltage and the refresh due to the problem of decreasing the length and width of the channel, and various studies have been conducted to secure their characteristics.

As one example, a recessed gate for recessing a channel region to form a groove in order to improve refresh characteristics while securing a channel length of a semiconductor device, and then forming a gate on the recess. Forming method was introduced.

The recess gate is a structure in which an effective channel length is increased as compared to a conventional planar gate, and thus, short channel characteristics can be reduced to improve device characteristics.

Hereinafter, the recess gate forming method currently being performed will be briefly described.

First, a recess mask for exposing a gate forming region is formed on a semiconductor substrate on which a device isolation film defining an active region is formed. Thereafter, the recess mask is used as an etch mask to etch exposed portions of the substrate to form grooves, and then the recess mask is removed. Next, a gate insulating film, a gate conductive film, and a gate hard mask film are sequentially formed on the grooves, and then, they are etched to form recess gates on the grooves.

However, when the recess gate is formed in the same manner as described above, since the interface between the device isolation film and the semiconductor substrate has a negative inclination from the position of the semiconductor substrate in the channel width direction, when the substrate is etched to form the groove, The phenomenon remains without being fully etched. That is, when the profile of the bottom surface is viewed in the channel width direction, a horn is formed that is not flat but is curved at both ends. As a result, a short channel effect is generated in which the channel length is reduced and the threshold voltage Vt is drastically reduced.

In addition, conventionally, when the doping impurities of the channel are excessively injected to reduce the short channel effect in the horn state, the threshold voltage target position is increased to increase the defects and traps of the device. This results in side effects such as reduced refresh and increased cell resistance.

The present invention provides a method of forming a recess gate of a semiconductor device that removes a horn generated during substrate etching.

In addition, the present invention provides a method of forming a recess gate of a semiconductor device capable of preventing a decrease in refresh characteristics due to horns and an increase in cell resistance.

A method of forming a recess gate of a semiconductor device according to the present invention includes a device isolation film defining an active region in which a sidewall oxide film and a linear nitride film are sequentially formed on a trench surface, and an insulating film is formed to fill a trench on the linear nitride film. Forming a hard mask on the semiconductor substrate, the hard mask exposing the gate forming region in the active region; Etching a gate forming region of the exposed active region to form a horn-induced groove in a bottom edge thereof; Firstly recessing the sidewall oxide layer so that the horn portion is exposed; Removing the horn at the bottom edge of the groove to secondary recess the sidewall oxide portion adjacent the bottom edge of the groove; And forming a gate insulating film on the groove surface.

The hard mask is formed of a laminated film of a pad oxide film and a pad nitride film.

The pad nitride layer of the hard mask is removed after first recessing the sidewall oxide layer to expose the horn portion and before removing the horn of the bottom edge of the groove.

The hard mask further forms an amorphous carbon film and a silicon nitride oxide film on the pad nitride film so that the etching barrier property is improved.

The etching of the gate forming region of the exposed active region is performed by TCP using a combination gas of Cl2, HBr and SF6.

The etching of the gate forming region of the exposed active region is performed by adding N2 or H2 gas to protect sidewalls of the semiconductor substrate.

The step of first recessing the sidewall oxide layer so that the horn portion is exposed is performed using HF or BOE solution.

And performing anisotropic or isotropic etching using a combination gas of CxHyFz and O2 to obtain a narrow trapezoidal shape at the top of the groove bottom edge prior to the step of primarily recessing the sidewall oxide layer so that the horn portion is exposed. .

The etching of the bottom of the groove is performed by a combination of anisotropic etching giving a chuck vice and isotropic etching without applying a bias, under conditions in which the horn portion is preferentially etched.

Secondly recessing the sidewall oxide layer portion adjacent to the groove bottom edge is performed using HF or BOE solution.

The gate insulating film is formed using a process combining dry, wet and radical oxidation.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention removes the horn generated during the etching of the substrate during the formation of the recess gate before forming the gate insulating film, or makes the horn have a negative profile.

In this way, since the present invention can prevent the reduction in the channel length due to the horn as compared with the related art, the refresh characteristics and the cell resistance characteristics due to the increase in the threshold voltage margin Vt Margin can be improved.

1A to 1F are cross-sectional views illustrating processes of forming a recess gate of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a buffer oxide film 110, a nitride film 112, and an amorphous film are formed to form a recess mask on a semiconductor substrate 100 on which a device isolation film 108 defining an active region is formed according to a known STI process. The carbon film 114 and the antireflection film 116 made of silicon nitride oxide film are sequentially formed.

In this case, the device isolation layer 108 includes a sidewall oxide layer 102 and a linear nitride layer 104 formed on the surface of the trench T in order, and the insulating layer 106 to fill the trench T on the linear nitride layer 104. It is made of a formed structure.

Referring to FIG. 1B, the antireflection film 116, the amorphous carbon film 114, the nitride film 112, and the buffer oxide film may be formed using a mask pattern (not shown) exposing a gate formation region on the antireflection film 116. Etch 110) sequentially. Thereafter, the semiconductor substrate 100 is etched using the etched nitride film 112 as an etch mask to form the groove A. In this case, the anti-reflection film 116 and the amorphous carbon film 114 are etched and removed together during the etching of the nitride film 112, the buffer oxide film 110, and the semiconductor substrate 100.

The etching of the substrate 100 for forming the groove A may be performed by using a TCP (Transfomer Coupled Plasma) etching using a combination gas of Cl 2, HBr, and SF 6, and N2 for protecting sidewalls of the semiconductor substrate 100. Or by adding H2 gas. The TCP etching refers to an etching process having two radio frequency (RF) powers to obtain a high density plasma.

Meanwhile, when etching the substrate 100 for forming the groove A, an interface between the device isolation layer 108 and the semiconductor substrate 100 has a negative inclination in the semiconductor substrate 100 position in the channel width direction. Therefore, the semiconductor substrate 100 may be left without being completely etched. Accordingly, a horn H of the shape in which both ends are not flat at the edges of the bottom surface of the groove A in the channel width direction may be bent upward. ) Is generated.

Referring to FIG. 1C, a portion of the sidewall oxide layer 102 of the device isolation layer 108 exposed by the groove A is removed by wet etching using an HF or BOE solution, and subsequently, the horn portion H is exposed. As such, the sidewall oxide layer 102 of the portion where the horn H is generated is similarly first recessed by wet etching using HF or BOE solution. Then, the nitride film 112 used as the hard mask film 118 is removed by wet cleaning using a H 3 PO 4 solution.

Meanwhile, after the portion of the sidewall oxide film 102 exposed by the groove A is removed, and before the sidewall oxide film 102 of the portion where the horn H is generated is first recessed, the groove A is removed. ) It is preferable to perform anisotropic or isotropic etching using a combination gas of CxHyFz and O2 to obtain a trapezoidal shape with a narrow upper surface at the bottom edge.

Referring to FIG. 1D, the bottom surface of the groove A including the horn H is oxidized using N 2 and O 2 plasma. Then, an oxide film (not shown) formed on the surface of the groove A as a result of the oxidation is etched using CF4 gas, and subsequently, TCP etching is performed on the substrate resultant, so that the horn of the bottom edge of the groove A is formed. H) is removed, thereby flattening the bottom surface of the groove (A).

Here, the TCP etching is performed using a combination gas of Cl 2, HBr, and SF 6, and particularly, a condition in which the horn (H) portion is preferentially etched by combining anisotropic etching giving chuck bias and isotropic etching without applying bias. It is preferable to form a narrow trapezoidal profile by performing the process.

Referring to FIG. 1E, a portion of the sidewall oxide layer 102 adjacent to the bottom edge of the planarized groove A is secondary recessed by wet etching using HF or BOE solution. Here, the present invention can further increase the effective channel length because the bottom edge of the groove A is secondarily recessed, so that the short channel characteristics can be further reduced to further improve the device characteristics.

Referring to FIG. 1F, after the gate insulating layer 120 is formed on the surface of the groove A, the gate conductive layer 122 is formed to fill the groove A on the gate insulating layer 120. In this case, the gate insulating layer 120 is formed using a combination of dry, wet, and radical oxidation in order to maximize the amount of oxidation in the <110> and <111> directions of the horn portion H. . After that, the gate hard mask layer 124 is formed on the gate conductive layer 122, and the gate hard mask layer 124, the gate conductive layer 122, and the gate insulating layer 120 are sequentially etched to form a gate. 126 is formed.

Here, since the edge portion of the bottom surface of the groove A is sufficiently exposed, and the oxidation rate is fast because it is close to the (110) or (111) surface, the bottom surface of the groove A is generally flat or the edge portion. It may have a profile of curved shape. Therefore, according to the present invention, the horn H generated during the etching of the substrate is removed before the gate insulating film is formed, or the subsequent process is performed in such a manner that the edge of the groove A has a curved profile. The decrease in refresh caused by the horn H and the increase in cell resistance can be prevented.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention eliminates the horn generated during the formation of the recess gate before forming the gate insulating layer, or makes the horn have a negative profile, thereby reducing the channel length caused by the horn compared to the conventional art. Since it can prevent, the refresh characteristic and the cell resistance characteristic by the increase of a threshold voltage margin (Vt Margin) can be improved.

Furthermore, defects and traps of the device can be reduced.

Claims (12)

A gate forming region in the active region is formed on a semiconductor substrate having a device isolation film defining an active region in which a sidewall oxide film and a linear nitride film are sequentially formed on the trench surface, and an insulating film is formed to fill a trench on the linear nitride film. Forming a hard mask exposing the hard mask; Etching a gate forming region of the exposed active region to form a horn-induced groove in a bottom edge thereof; Firstly recessing the sidewall oxide layer so that the horn portion is exposed; Removing the horn at the bottom edge of the groove to secondary recess the sidewall oxide portion adjacent the bottom edge of the groove; And Forming a gate insulating film on the groove surface; Recess gate forming method of a semiconductor device comprising a. The method of claim 1, And the hard mask is formed of a laminated film of a pad oxide film and a pad nitride film. The method of claim 2, The pad nitride layer of the hard mask may be removed after first recessing the sidewall oxide layer so that the horn portion is exposed and before removing the horn at the bottom edge of the groove. A method of forming a set gate. The method of claim 2, The hard mask may be formed by forming an amorphous carbon film and a silicon nitride oxide film on the pad nitride layer so that the etching barrier property is improved. The method of claim 1, And etching the gate forming region of the exposed active region by TCP using a combination gas of Cl 2, HBr, and SF 6. The method of claim 5, wherein And etching the gate forming region of the exposed active region by adding N2 or H2 gas to protect sidewalls of the semiconductor substrate. The method of claim 1, Recessing the sidewall oxide film portion primarily so that the horn portion is exposed, the recess gate forming method of the semiconductor device, characterized in that performed using HF or BOE solution. The method of claim 1, And performing anisotropic or isotropic etching using a combination gas of CxHyFz and O2 to obtain a narrow trapezoidal shape at the top of the groove bottom edge prior to the step of primarily recessing the sidewall oxide layer so that the horn portion is exposed. A method of forming a recess gate in a semiconductor device, characterized in that the. The method of claim 1, Removing the horn may include oxidizing a bottom of a groove including the horn portion using N2 and O2 plasma; Etching the oxide film formed on the groove surface as a result of the oxidation using CF4 gas; And etching the bottom surface of the groove using a TCP method using a combination gas of Cl 2, HBr, and SF 6. The method of claim 9, The etching of the bottom of the groove is performed by a combination of anisotropic etching giving chuck bias and isotropic etching without applying bias, so that the horn portion is preferentially etched. method. The method of claim 1, And secondly recessing the sidewall oxide layer portion adjacent the bottom edge of the groove using HF or BOE solution. The method of claim 1, And the gate insulating film is formed using a combination of dry, wet, and radical oxidation.
KR1020070029688A 2007-03-27 2007-03-27 Method for forming recess gate of semiconductor device KR20080087442A (en)

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