KR100825028B1 - Method of manufacturing a semiconductor device having a recess gate - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device having a recess gate for preventing a leakage current and a decrease in yield caused by the point when forming the recess pattern, the present invention is to form a recess mask pattern on a substrate step; Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form sidewall protective layers on sidewalls of the first recess pattern; Etching a substrate of a bottom portion of the first recess pattern to form a second recess pattern; Widening the width of the second recess pattern; Forming a gate electrode having a gate insulating layer interposed therebetween in the first and second recess patterns.

Description

Method of manufacturing a semiconductor device having a recess gate {METHOD FOR FOBRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE}

1 is a cross-sectional view for explaining a recess pattern of a semiconductor device according to the prior art;

2 is a TEM photograph showing a recess pattern of a semiconductor device according to the prior art;

Figure 3 is a TEM photograph showing the cause of the formation (Horn),

4A to 4F are cross-sectional views illustrating a method of manufacturing a recess pattern of a semiconductor device in accordance with an embodiment of the present invention;

5a and 5b is a TEM photograph showing an oxide film according to a preferred embodiment of the present invention,

6A and 6B are TEM photographs for comparing the present invention with the prior art.

* Explanation of symbols for the main parts of the drawings

401 semiconductor substrate 402 device isolation film

403: sacrificial oxide film 404: amorphous carbon

405: antireflection film 406: photosensitive film pattern

407: first recess pattern 408: sidewall protective film

409: second recess pattern 410: gate insulating film

411 polysilicon electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a recess pattern of a semiconductor device.

As the semiconductor devices become highly integrated, the conventional planar gate wiring forming method for forming a gate over a flat active region becomes smaller as the gate channel length and the ion implantation doping concentration increase. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

In order to secure refresh characteristics of a semiconductor device, a technique of forming a recess gate structure, which is a 3D gate structure that increases a channel length by recessing a region under a gate pattern, has been proposed.

1 is a cross-sectional view illustrating a recess pattern of a semiconductor device according to the prior art.

As shown in FIG. 1, an isolation layer 102 is formed on the semiconductor substrate 101, and an oxide film 103 and an amorphous carbon 104 are formed on the semiconductor substrate 101 to open the recess formation region. The open semiconductor substrate 101 is etched to form a recess pattern 105.

As described above, a portion of the semiconductor substrate 101 is selectively etched to form the recess pattern 105, thereby increasing the channel length and reducing the implant doping concentration, thereby improving the refresh characteristics of the device.

However, the size in which the recess pattern 105 can be formed is reduced in the process of the semiconductor device being ultra-fine patterned, and the recess pattern 105 is formed with a profile of a “Ｖ” type to form the recess pattern 105. There is a problem in that a sharp point (Horn, '100' of FIG. 2) occurs between the adjacent device isolation layer 102 (see FIG. 2).

Particularly, the sharp point forms a slope profile without etching vertically for the gap fill characteristic of the insulating film when forming the device isolation layer 102 together with the “Ｖ” type profile of the recess pattern 105. There is a problem that is further worsened by (see Fig. 3).

As described above, there is a problem in that the characteristics of subsequent gate oxides are degraded due to horns, and as stress concentration points, they act as a leakage source, thereby reducing the yield of devices. It is difficult to produce DRAM due to problems such as (Yield Drop).

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a semiconductor device having a recess gate for preventing a leakage current and a decrease in yield, which are generated due to a peak in forming a recess pattern. There is this.

A method of manufacturing a semiconductor device having a recess gate according to the present invention includes forming a recess mask pattern on a substrate; Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form sidewall protective layers on sidewalls of the first recess pattern; Etching a substrate of a bottom portion of the first recess pattern to form a second recess pattern; Widening the width of the second recess pattern; And forming a gate electrode having a gate insulating layer interposed therebetween in the first and second recess patterns.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

4A to 4F are cross-sectional views illustrating a method of manufacturing a recess pattern of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, an isolation layer 402 is formed on the substrate 401. Here, the substrate 401 may be a semiconductor substrate on which a DRAM process is performed. In addition, the device isolation layer 402 proceeds through a shallow trench isolation (STI) process, which forms trenches in the substrate 401 and fills trenches to secure gap-fill characteristics of the insulating layer in the process of filling the insulating layer. It can be formed in a slope profile (not a vertical profile).

Subsequently, the sacrificial oxide film 403 and the amorphous carbon 404 are formed on the substrate 401 including the device isolation film 402. Here, the sacrificial oxide film 403 serves as a hard mask when the subsequent recess pattern is formed, and the amorphous carbon 404 serves as a hard mask for etching the sacrificial oxide film 403.

Subsequently, a bottom anti reflection coating (BARC) is formed on the amorphous carbon 404. Here, the anti-reflection film 405 serves to prevent reflection when forming the subsequent photoresist pattern.

Subsequently, a photosensitive film pattern 406 is formed on the antireflection film 405. Here, the photoresist pattern 406 may be formed by coating a photoresist on the antireflection film 405 and patterning the recess formation region to be opened by exposure and development.

As shown in FIG. 4B, the anti-reflection film 405, the amorphous carbon 404, and the sacrificial oxide film 403 are etched using the photoresist pattern 406.

Here, the amorphous carbon 404 is etched to a point where the sacrificial oxide film 403 is opened using a plasma using a mixed gas of N ₂ and O ₂ in a MERIE (Magnetically Enhanced Reactive Ion beam Etching) type plasma equipment.

Subsequently, the sacrificial oxide film 403 is etched using a plasma formed by adding oxygen gas to a mixed gas of CF gas and CHF gas.

As shown in FIG. 4C, the photoresist pattern 406, the antireflection film 405, and the amorphous carbon 404 are removed. Here, the photoresist pattern 406 and the anti-reflection film 405 may be lost when etching both the amorphous carbon 404 and the sacrificial oxide film 403 of FIG. 4B, or may be removed together when the amorphous carbon 404 is removed.

Here, the amorphous carbon 404 is removed using a plasma formed of oxygen gas, but the oxygen gas may use a flow rate of 200 sccm to 1000 sccm.

Subsequently, the substrate 401 is etched using the sacrificial oxide film 403 as an etch barrier to form a first recess pattern 407 and a plasma oxide layer on the substrate 401 including the first recess pattern 407. 408 is formed. That is, the etching process is performed by injecting a mixed gas of an etching gas for forming the first recess pattern 407 and a gas for forming the plasma oxide layer 408, and simultaneously forming the first recess pattern 407. The plasma oxide layer 408 is formed on the substrate 401 including the one recess pattern 407.

In particular, the etching gas for forming the first recess pattern 407 may use HBr, and the gas for forming the plasma oxide layer 408 may use a mixed gas of O ₂ / N ₂ or O ₂ / CHxFx. have. In addition, CHxFx may use CHF ₃ or CH ₂ F ₂ . Preferably, the mixed gas of O ₂ / N ₂ may form a thicker plasma oxide layer 408.

In order to simultaneously form the first recess pattern 407 and the plasma oxide layer 408, a pressure of 5 mT to 20 mT and a source power of 700 mW to 1500 mW in a high density plasma apparatus of a transformer coupled plasma (TCP) or inductively coupled plasma (ICP), Etching may be performed such that a bottom power of 200 kW to 500 kW is applied to a depth of 200 kW to 500 kW. In addition to the TCP or ICP, it can be carried out in any one of the etching equipment selected from the group of MDS (Microwave Down Stream), ECR (Electron Cyclotron Resonance) and HELICAL.

As described above, when the first recess pattern 407 is formed, the substrate is exposed by etching simultaneously with etching by adding O ₂ / N ₂ or O ₂ / CHxFx, which is a gas for forming the plasma oxide layer 408. Plasma oxidation is performed on the surface of the 401 to form the plasma oxide layer 408 without undergoing a separate plasma oxidation process.

As shown in FIG. 4D, the plasma oxide layer 408 of the bottom of the first recess pattern 407 is etched to leave the plasma oxide layer 408 on the sidewall of the first recess pattern 407, thereby protecting the sidewall protective layer 408A. To form. Here, the etching of the plasma oxide layer 408 may be performed by full etching.

As shown in FIG. 4E, the substrate of the bottom portion of the first recess pattern 407 is etched to form a second recess pattern 409 that is wider than the first recess pattern 407.

Here, the second recess pattern 409 may be formed by etching a substrate on the bottom of the first recess pattern 408 to form a second recess pattern 409 and to widen the width of the second recess pattern 409. The process may be performed in-situ in the same chamber as the formation of the first recess pattern 407.

First, a mixed gas of HBr and Cl ₂ is used to form the second recess pattern 409, and etching may be performed using a mixed gas in which a flow ratio of HBr: Cl ₂ is mixed at 0.5 to 2: 1. . Further, a pressure of 10 mT to 30 mT, a top power of 500 kPa to 1000 kPa, and a bottom power of 200 kPa to 500 kPa is applied to etch a depth of 700 kPa to 1000 kPa from the bottom of the first recess pattern 407, but with a slight isotropic etching (Small). Isotropic etching is performed so that the center of the second recess pattern 409 has a bowing profile. This is to minimize the dots formed between the first and second recess patterns 407 and 409 and the adjacent device isolation layer 402.

Subsequently, in order to widen the width of the second recess pattern 409, isotropic etching is performed by adding any one selected from the group of O ₂ and SF ₆ , CF-based gas and NF-based gas to the mixed gas of HBr and Cl ₂ The width of the second recess pattern is increased by 10 nm to 15 nm by applying a pressure of 20 mT to 100 mT, a source power of 500 mW to 1500 mW, and a bottom power of at least 50 mW or less.

As described above, the first and second recess patterns 407 and 409 are formed by forming a second recess pattern 409 that is wider than the first recess pattern 407 and has a boeing profile and widens the width thereof. And the additives formed between the adjacent device isolation layers 402 may be minimized. In particular, since the point where the point is formed is the depth at which the second recess pattern 409 is formed, the sidewall protection layer 408A is formed on the sidewall of the first recess pattern 407 to protect the sidewall while the second recess pattern is formed. Since only 409 is selectively widened, a fine pattern can be formed.

As shown in FIG. 4F, the sidewall protective film 408 and the sacrificial oxide film 403 are removed.

Subsequently, a gate insulating layer 410 is formed on the substrate 401 including the first and second recess patterns 407 and 409. Here, the gate insulating film 410 may be formed of an oxide film. At this time, since the second recess pattern 409 is formed in a boeing profile wider than that of the first recess pattern 407 in FIG. 4E, since the point of contact with the adjacent device isolation layer 402 is minimized, the gate insulating layer 410 is formed. Can be prevented from deteriorating.

Subsequently, a gate electrode 411 is partially formed on the gate insulating layer 410 and partially embedded in the first and second recess patterns 407 and 409, and the other part protrudes over the substrate 401.

5A and 5B are TEM photographs showing an oxide film according to a preferred embodiment of the present invention.

As shown in FIGS. 5A and 5B, an oxide film formed by adding O ₂ / N ₂ or O ₂ / CH ₂ F ₂ when forming a recess pattern may be known.

As described above, the mixed gas of O ₂ / N ₂ or O ₂ / CH ₂ F ₂ used in the present invention can form a plasma oxide layer, but in the case of O ₂ / N ₂ , a thicker oxide layer can be formed.

6A and 6B are TEM photographs for comparing the present invention with the prior art.

As shown in FIGS. 6A and 6B, in the prior art of FIG. 6A, there is almost no horn of an element isolation layer adjacent to the recess pattern in FIG. 6B in comparison to the recess pattern in the present invention. Able to know.

According to the present invention, the bottom portion of the first recess pattern 407 is etched by forming the sidewall protective layer 408A on the sidewall of the first recess pattern 407 and the horn is formed at the same time as the first recess pattern 407 is formed. Even if the second recess pattern 409 having a wider width than the first recess pattern 407 is formed, the sidewalls of the first recess pattern 407 may be protected, thereby forming a fine pattern. .

In addition, the width of the second recess pattern 409 is isotropically etched to widen the first recess and the second recess pattern 407 and 409, and the peaks generated in the portion adjacent to the device isolation layer 402 may be removed. Degradation of the 410 can be prevented, and thus, the deterioration of the gate insulating film 410 can be prevented from causing a leakage current to the stress concentration point.

In addition, by isotropically etching the second recess pattern 409, there is an advantage in that the "Ｖ" profile of the recess pattern is alleviated to remove the peaks and to secure the channel length and reduce the ion implantation concentration.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above forms a device isolation film in an oblique profile for reducing the size of the recess pattern and gap fill of the device isolation film in the process of ultrafine patterning of the semiconductor device, and thus between the recess isolation pattern and the adjacent device isolation film. Even if the horn increases, a sidewall protective film is formed on the upper portion of the recess pattern, thereby forming a dual profile recess pattern having a wider width than the upper portion of the recess pattern, thereby minimizing steepness.

Therefore, the deterioration of the characteristics of the gate oxide film and the stress concentration point, thereby causing the weak point that acted as a source of leakage current disappears, so that the channel length of the recess pattern and the ion implantation concentration can be reduced. This has the effect of greatly improving.

In addition, it is possible to solve the proposition of securing design rules and maximizing process margins, thereby enabling high integration of semiconductor devices including logic, improved yields, and lower production costs.

Claims (14)

Forming a recess mask pattern on the substrate; Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form sidewall protective layers on sidewalls of the first recess pattern; Etching a substrate of a bottom portion of the first recess pattern to form a second recess pattern; Widening the width of the second recess pattern; And Forming a gate electrode having a gate insulating layer interposed therebetween in the first and second recess patterns; A semiconductor device manufacturing method having a recess gate comprising a. The method of claim 1, Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form a sidewall protective layer on sidewalls of the first recess pattern. Forming a plasma oxide layer on the surface of the substrate exposed by the etching simultaneously with etching for forming the first recess pattern; And Etching the plasma oxide layer on the bottom portion of the first recess pattern to form the sidewall protective layer by leaving the plasma oxide layer on the sidewall of the first recess pattern. Method of manufacturing a semiconductor device having a recess gate comprising a. The method of claim 2, Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form a sidewall protective layer on sidewalls of the first recess pattern. And a recess gate for mixing the gas for etching the substrate and the gas for plasma oxidation. The method of claim 3, The gas for etching the substrate is HBr, the gas for plasma oxidation is a semiconductor device manufacturing method having a recess gate, characterized in that using the O ₂ / N ₂ or O ₂ / CHF-based gas. The method of claim 4, wherein The CHF-based gas is CHF ₃ or CH ₂ F ₂ A semiconductor device manufacturing method having a recess gate, characterized in that. The method according to any one of claims 2 to 5, Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form a sidewall protective layer on sidewalls of the first recess pattern. A method of manufacturing a semiconductor device having a recess gate, wherein the method is performed by TCP (Transformer Coupled Plasma) or ICP (Inductively Coupled Plasma). The method of claim 6, Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form a sidewall protective layer on sidewalls of the first recess pattern. A method of manufacturing a semiconductor device having a recess gate, characterized by etching to a depth of 200 mW to 500 mW by applying a pressure of 5 mT to 20 mT, a source power of 700 mW to 1500 mW, and a bottom power of 200 mW to 500 mW. The method according to any one of claims 2 to 5, Etching the substrate to form a first recess pattern and simultaneously oxidizing the substrate to form a sidewall protective layer on sidewalls of the first recess pattern. Method for manufacturing a semiconductor device having a recess gate, characterized in that performed in any one of the etching equipment selected from the group of MDS (Microwave Down Stream), ECR (Electron Cyclotron Resonance) and HELICAL. delete The method of claim 1, Forming the second recess pattern and widening the width of the second recess pattern include: And a recess gate in-situ in the same chamber as the step of forming the first recess pattern. The method of claim 10, Etching the substrate of the bottom portion of the first recess pattern to form a second recess pattern, A method of manufacturing a semiconductor device having a recess gate, comprising using a mixed gas of HBr and Cl ₂ and mixing a flow rate ratio of HBr: Cl ₂ at 0.5 to 2: 1. The method of claim 11, Etching the substrate of the bottom portion of the first recess pattern to form a second recess pattern, Applying 10mT ~ 30mT pressure, 500Ｗ ~ 1000Ｗ top power, 200Ｗ ~ 500Ｗ bottom power to etch the depth of 700Å ~ 1000 하고 and isotropic etching to make the middle of the second recess pattern the bowing profile. A semiconductor device manufacturing method having a recess gate, characterized in that it is carried out to have. The method of claim 10, Expanding the width of the second recess pattern, A method of manufacturing a semiconductor device having a recess gate, wherein the gas isotropically etched by mixing any one selected from the group consisting of SF ₆ , CF-based gas and NF-based gas with HBr, Cl ₂ and O ₂ . The method of claim 13, Expanding the width of the second recess pattern, A pressure of 20 mT to 100 mT, a source power of 500 kW to 1500 kW, and a bottom power lower than the step of forming the second recess pattern are applied to increase the width of the second recess pattern by 10 nm to 15 nm. A semiconductor device manufacturing method having a recess gate, characterized in that.

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