KR20080089031A - Method for fabricating recess gate in semiconductor device - Google Patents

Method for fabricating recess gate in semiconductor device Download PDF

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Publication number
KR20080089031A
KR20080089031A KR1020070031994A KR20070031994A KR20080089031A KR 20080089031 A KR20080089031 A KR 20080089031A KR 1020070031994 A KR1020070031994 A KR 1020070031994A KR 20070031994 A KR20070031994 A KR 20070031994A KR 20080089031 A KR20080089031 A KR 20080089031A
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recess
pattern
substrate
isolation layer
gate
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KR1020070031994A
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Korean (ko)
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유병화
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주식회사 하이닉스반도체
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Publication of KR20080089031A publication Critical patent/KR20080089031A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

A method for manufacturing a recess gate of a semiconductor device is provided to secure a uniform refresh in a wafer by etching a silicon substrate after etching an isolation layer. An isolation layer(35A) is formed on a predetermined region of a substrate(31). A hard mask pattern(36) is formed to open the substrate and the isolation layer at the same time. A part of the opened isolation layer is etched to form a first recess pattern(R1). A part of the opened substrate is etched to form a second recess pattern(R2). The hard mask pattern is removed. A gate dielectric is formed on the substrate where the first and second recess patterns are formed. Parts of the first and second recess patterns are gap-filled to form a gate pattern that has a shape being protruded on a surface of the substrate. Before the second recess pattern is formed, the first recess pattern is formed. The second recess pattern is formed so that it has high selectivity for the isolation layer.

Description

반도체소자의 리세스게이트 제조 방법{METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE}Recess gate manufacturing method of semiconductor device {METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 리세스게이트 제조 방법을 간략히 도시한 도면.1 is a view schematically showing a method for manufacturing a recess gate according to the prior art.

도 2는 첨점이 발생된 SEM 사진.Figure 2 is a SEM photograph of the cusp generated.

도 3은 본 발명의 실시예에 따른 리세스게이트의 평면도.3 is a plan view of a recess gate according to an exemplary embodiment of the present invention.

도 4a 내지 도 4e는 본 발명의 실시예에 따른 반도체소자의 리세스게이트 제조 방법을 도시한 공정 단면도.4A through 4E are cross-sectional views illustrating a method of manufacturing a recess gate of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 실리콘기판 32 : 패드산화막31 silicon substrate 32 pad oxide film

33 : 패드질화막 34 : 트렌치33: pad nitride film 34: trench

35A : 소자분리막 36 : 하드마스크패턴35A: device isolation layer 36: hard mask pattern

37 : 게이트절연막37: gate insulating film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 리세스게이트 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a recess gate.

최근에, 서브 100nm급 DRAM을 제조할 때 채널 길이가 짧아 소자의 리프레시 특성이 악화되는데, 이를 극복하기 위하여 활성영역을 수십 nm 정도 리세스(Recess)시켜 리세스에 게이트의 일부를 매립시키는 리세스 게이트(Recess Gate; R-gate) 기술이 제안되었다.Recently, when fabricating a sub-100nm DRAM, the channel length is short and the refresh characteristics of the device are deteriorated. To overcome this, recesses recessing the active region by several tens of nm to fill a portion of the gate in the recesses are recessed. Recess Gate (R-gate) technology has been proposed.

위와 같이 리세스 게이트를 갖는 반도체소자를 제조하면, 소자의 집적화에 따라 짧아지는 채널길이(Channel length)보다 더 긴 채널길이를 확보할 수 있어서 리프레시 특성을 크게 향상시킬 수 있다.When the semiconductor device having the recess gate is manufactured as described above, the channel length longer than the channel length shortened by the integration of the device can be ensured, thereby greatly improving the refresh characteristics.

도 1은 종래기술에 따른 리세스게이트 제조 방법을 간략히 도시한 도면이다.1 is a view briefly illustrating a method for manufacturing a recess gate according to the prior art.

도 1을 참조하면, 실리콘기판(11)에 소자분리막(12)을 형성한 후, 리세스식각을 진행하여 리세스패턴(13)을 형성한다.Referring to FIG. 1, after the device isolation layer 12 is formed on the silicon substrate 11, a recess pattern 13 is performed to form a recess pattern 13.

그러나, 종래기술은 리세스식각시 첨점(A-A'선에 따른 단면의 '14' 참조)이 발생되는 문제가 있다.However, the prior art has a problem in that a sharp point (see '14' of the cross section along the line A-A ') occurs during the recess etching.

도 2는 첨점이 발생된 SEM 사진이다.2 is a SEM photograph of the occurrence of the puncturing.

첨점(Horn, 14)은 실리콘기판(11)의 리세스식각시 소자분리막(12)으로 사용된 산화막이 식각장벽으로 작용하여 식각이 완전히 이루어지지 않기 때문에 발생한다. 이처럼, 산화막이 식각장벽으로 작용하는 것은 소자분리막 공정시 형성하는 트렌치의 슬로프(Slope, 도면부호 'S' 참조)에 기인한다.Horn (14) occurs because the oxide film used as the device isolation film 12 during the recess etching of the silicon substrate 11 acts as an etch barrier and is not completely etched. As such, the oxide film acts as an etch barrier due to the slope of the trench formed during the device isolation process (see 'S').

이와 같은 첨점(14)이 제거되지 않으면, 셀 문턱전압을 저하시키며, 웨이퍼 내 균일도도 열화시켜 리프레시 특성 열화를 유발시킨다.If such peaks 14 are not removed, the cell threshold voltage is lowered, and the uniformity in the wafer is also degraded, causing the refresh characteristics to deteriorate.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 리세스게이트 공정시 소자분리막과 활성영역간 경계부분에서 발생되는 첨점을 억제할 수 있는 반도체소자의 리세스게이트 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a recess gate of a semiconductor device capable of suppressing a sharpness generated at the boundary between the device isolation layer and the active region during the recess gate process. There is a purpose.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 리세스게이트 제조 방법은 기판의 소정영역에 소자분리막을 형성하는 단계; 상기 기판과 소자분리막의 표면을 동시에 오픈시키는 하드마스크패턴을 형성하는 단계; 상기 오픈된 소자분리막을 일부 식각하여 제1리세스패턴을 형성하는 단계; 상기 오픈된 기판을 일부 식각하여 제2리세스패턴을 형성하는 단계; 상기 하드마스크패턴을 제거하는 단계; 상기 제1 및 제2리세스패턴이 형성된 기판 상에 게이트절연막을 형성하는 단계; 및 상기 제1 및 제2리세스패턴에 일부가 매립되고 상기 기판의 표면 위로 돌출되는 형상을 갖는 게이트패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.Recess gate manufacturing method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a device isolation film in a predetermined region of the substrate; Forming a hard mask pattern for simultaneously opening the surfaces of the substrate and the device isolation film; Partially etching the open device isolation layer to form a first recess pattern; Partially etching the open substrate to form a second recess pattern; Removing the hard mask pattern; Forming a gate insulating film on the substrate on which the first and second recess patterns are formed; And forming a gate pattern having a shape partially embedded in the first and second recess patterns and protruding above the surface of the substrate.

바람직하게, 상기 제1리세스패턴을 형성하는 단계는 상기 제2리세스패턴을 형성하는 단계보다 먼저 진행하는 것을 특징으로 한다.The forming of the first recess pattern may be performed before the forming of the second recess pattern.

바람직하게, 상기 제1리세스패턴을 형성하는 단계는 상기 기판에 대해 높은 선택비를 갖도록 하여 식각하고, 상기 제2리세스패턴을 형성하는 단계는 상기 소자 분리막에 대해 높은 선택비를 갖도록 하여 식각하는 것을 특징으로 한다.The forming of the first recess pattern may be performed by etching the substrate having a high selectivity with respect to the substrate, and the forming of the second recess pattern may be performed by having a high selectivity with respect to the device isolation layer. Characterized in that.

바람직하게, 상기 제1리세스패턴과 제2리세스패턴은 깊이와 선폭을 동일하게 하는 것을 특징으로 한다.Preferably, the first recess pattern and the second recess pattern have the same depth and line width.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 3은 본 발명의 실시예에 따른 리세스게이트의 평면도로서, 실리콘기판(31)에 활성영역(31A)을 정의하는 소자분리막(35A)이 형성된다. 그리고, 활성영역(31A)과 소자분리막(35A)을 동시에 가로지르는 게이트패턴(G)이 형성되고, 게이트패턴 아래에는 채널로 작용하는 리세스패턴(R)이 형성되어 있다. 여기서, 리세스패턴(R)은 소자분리막(35A)측에 일정 깊이로 형성된 제1리세스패턴(R1)과 활성영역(31A)측에 일정 깊이로 형성된 제2리세스패턴(R2)으로 이루어지고, R1과 R2는 동일 선폭 및 동일 깊이다. 여기서, 실질적으로 채널은 제2리세스패턴(R2)에서 작용한다.3 is a plan view of a recess gate according to an exemplary embodiment of the present invention, in which a device isolation layer 35A defining an active region 31A is formed in a silicon substrate 31. A gate pattern G is formed across the active region 31A and the device isolation layer 35A at the same time, and a recess pattern R serving as a channel is formed under the gate pattern. The recess pattern R may include a first recess pattern R1 formed at a predetermined depth on the device isolation layer 35A and a second recess pattern R2 formed at a predetermined depth on the active region 31A. R1 and R2 are the same line width and the same depth. Here, the channel substantially operates in the second recess pattern R2.

도 4a 내지 도 4e는 본 발명의 실시예에 따른 반도체소자의 리세스게이트 제조 방법을 도시한 공정 단면도이다. 이하, 좌측의 공정 단면도는 도 3의 B-B'선에 따른 단면도이고, 우측의 공정단면도는 도 3의 C-C'선에 따른 단면도이다.4A through 4E are cross-sectional views illustrating a method of manufacturing a recess gate of a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, the process cross section of the left side is sectional drawing along the line BB 'of FIG. 3, and the process cross section of the right side is sectional drawing along the line C-C' of FIG.

도 4a에 도시된 바와 같이, 실리콘기판(31) 상에 패드산화막(32)을 형성한 후, 패드산화막(32) 상에 패드질화막(33)을 형성한다.As shown in FIG. 4A, after the pad oxide film 32 is formed on the silicon substrate 31, the pad nitride film 33 is formed on the pad oxide film 32.

이어서, 사진 공정 및 식각공정을 진행하여 실리콘기판(31)에 소자분리영역 이 될 트렌치(34)를 형성한다. 이러한 트렌치(34)에 의해 활성영역(31A)이 정의된다. 그리고, 트렌치(34)는 경사(Slope)를 갖는다.Subsequently, a trench 34 to be an isolation region is formed on the silicon substrate 31 by performing a photo process and an etching process. The active region 31A is defined by the trench 34. The trench 34 has a slope.

이어서, 측벽산화(Wall oxidation) 공정 및 라이너질화막(Liner nitridation) 공정(도면 부호 생략)을 진행한 후, 트렌치(34)를 갭필하도록 산화막(35)을 증착한다. 이때, 산화막(35)은 고밀도플라즈마산화막(High Density Plasma Oxide)이다.Subsequently, after performing a side wall oxidation process and a liner nitridation process (not shown), an oxide film 35 is deposited to gap fill the trench 34. At this time, the oxide film 35 is a high density plasma oxide (High Density Plasma Oxide).

도 4b에 도시된 바와 같이, CMP(Chemical Mechanical Polishing) 공정을 이용하여 산화막(35)을 평탄화한다. 이로써, 트렌치(34) 내부에는 산화막으로 된 소자분리막(35A)이 형성된다. 한편, CMP 공정시 패드질화막(33)이 연마정지막 역할을 한다. As shown in FIG. 4B, the oxide film 35 is planarized by using a chemical mechanical polishing (CMP) process. As a result, an isolation layer 35A made of an oxide film is formed in the trench 34. On the other hand, the pad nitride film 33 serves as a polishing stop film during the CMP process.

위와 같은 소자분리막(35A)은 경사를 갖는 트렌치(34) 내부에 매립되어 형성되므로 STI(Shallow Trench Isolation) 구조라 한다.Since the device isolation layer 35A is embedded in the trench 34 having the inclination, the isolation layer 35A is referred to as a shallow trench isolation (STI) structure.

도 4c에 도시된 바와 같이, 하드마스크패턴(36)을 형성한다. 이때, 하드마스크패턴(36)은 산화막, 질화막, 폴리실리콘막 또는 비정질카본 중에서 선택된 어느 하나이고, 감광막패턴을 이용하여 식각하여 형성한 것이다. 그리고, 하드마스크패턴(36)은 식각장벽 역할을 한다.As shown in FIG. 4C, the hard mask pattern 36 is formed. At this time, the hard mask pattern 36 is any one selected from an oxide film, a nitride film, a polysilicon film, or an amorphous carbon, and is formed by etching using a photosensitive film pattern. In addition, the hard mask pattern 36 serves as an etch barrier.

위와 같은 하드마스크패턴(36)은 라인패턴으로서 실리콘기판(31)과 소자분리막(35)을 동시에 라인 형태로 오픈시킨다.The hard mask pattern 36 as described above opens the silicon substrate 31 and the device isolation layer 35 in a line form simultaneously as a line pattern.

이어서, 하드마스크패턴(36)을 식각장벽으로 하여 패드질화막(33)과 패드산화막(32)을 식각한다.Subsequently, the pad nitride film 33 and the pad oxide film 32 are etched using the hard mask pattern 36 as an etch barrier.

이어서, 하드마스크패턴(36)을 식각장벽으로 하여 소자분리막(35A)을 식각하여 제1리세스패턴(R1)을 형성한다. 이때, 소자분리막(35A)이 산화막이므로, 실리콘기판(31)에 대해 높은 선택비를 가져 산화막만 선택적으로 식각할 수 있는 레시피를 적용한다. Subsequently, the device isolation layer 35A is etched using the hard mask pattern 36 as an etch barrier to form a first recess pattern R1. At this time, since the device isolation film 35A is an oxide film, a recipe capable of selectively etching only the oxide film with a high selectivity with respect to the silicon substrate 31 is applied.

예를 들어, CF4 가스와 CHF3 가스를 혼합하여 식각하며, 식각공정은 TCP(Transformer Coupled Plasma), ICP(Inductively Coupled Plasma) 또는 MERIE(Magnetically Enhanced Reactive Ion beam Etching) 플라즈마 소스를 이용하여 식각공정을 실시한다. 한편, CF4/CHF3의 혼합가스를 메인가스로 하고 O2 가스와 Ar 가스를 첨가하여 진행할 수도 있다. For example, a mixture of CF 4 gas and CHF 3 gas is etched, and the etching process is performed using a TCP (Transformer Coupled Plasma), ICP (Inductively Coupled Plasma) or MERIE (Magnetically Enhanced Reactive Ion beam Etching) plasma source. Is carried out. On the other hand, the mixed gas of CF 4 / CHF 3 may be used as the main gas, and O 2 gas and Ar gas may be added to proceed.

이와 같이, 리세스패턴이 형성될 지역의 소자분리막(35A)을 미리 식각하므로써, 후속 실리콘기판(31) 식각시 식각장벽 역할을 하는 산화막을 미리 제거해준다.As such, by etching the device isolation layer 35A in the region where the recess pattern is to be formed in advance, the oxide layer serving as an etch barrier during the subsequent etching of the silicon substrate 31 is removed in advance.

여기서, 제1리세스패턴(R1)은 하드마스크패턴(36)을 식각장벽으로 하여 형성하므로 일정 깊이의 리세스패턴이 된다.Here, since the first recess pattern R1 is formed using the hard mask pattern 36 as an etch barrier, the first recess pattern R1 is a recess pattern having a predetermined depth.

도 4d에 도시된 바와 같이, 하드마스크패턴(36)을 식각장벽으로 하여 실리콘기판(31)을 일정 깊이 식각한다. 이때, 실리콘기판(31)의 식각시 HBr, Cl2를 사용하여 소자분리막(35A)에 대해 높은 선택비를 가져 실리콘기판(31)만 선택적으로 식각되도록 한다. 식각공정은 TCP(Transformer Coupled Plasma), ICP(Inductively Coupled Plasma) 또는 MERIE(Magnetically Enhanced Reactive Ion beam Etching) 플라즈마 소스를 이용하여 식각공정을 실시한다. 실리콘기판(31)의 식각시 소자분 리막(35A)에 대해 높은 선택비를 갖도록 하므로, 제1리세스패턴(R1)의 깊이가 깊어지지 않는다.As shown in FIG. 4D, the silicon substrate 31 is etched to a predetermined depth using the hard mask pattern 36 as an etch barrier. At this time, when the silicon substrate 31 is etched, only the silicon substrate 31 is selectively etched by using HBr and Cl 2 to have a high selectivity with respect to the device isolation layer 35A. The etching process is performed using a transformer coupled plasma (TCP), an inductively coupled plasma (ICP) or a magnetically enhanced reactive ion beam etching (MERIE) plasma source. Since the silicon substrate 31 is etched to have a high selectivity with respect to the device isolation film 35A, the depth of the first recess pattern R1 is not deepened.

실리콘기판(31)의 식각 깊이는 제1리세스패턴(R1)의 깊이와 동일하게 하여, 실리콘기판(31)의 식각이 완료되면 일정 깊이의 제2리세스패턴(R2)이 라인 형태로 형성된다. 따라서, 제2리세스패턴(R2)과 제1리세스패턴(R1)은 동일 깊이 및 동일 선폭의 라인패턴이 되고, 결국 제1리세스패턴(R1)과 제2리세스패턴(R2)은 라인형태의 일체형 리세스패턴(R)이 된다.The etching depth of the silicon substrate 31 is the same as the depth of the first recess pattern R1. When the etching of the silicon substrate 31 is completed, the second recess pattern R2 having a predetermined depth is formed in a line shape. do. Accordingly, the second recess pattern R2 and the first recess pattern R1 become line patterns having the same depth and the same line width, and thus, the first recess pattern R1 and the second recess pattern R2 are the same. The integrated recess pattern R in a line form is obtained.

도 4e에 도시된 바와 같이, 하드마스크패턴(36)을 제거한 후, 패드질화막(33)과 패드산화막(32)을 제거한다.As shown in FIG. 4E, after the hard mask pattern 36 is removed, the pad nitride film 33 and the pad oxide film 32 are removed.

이어서, 게이트절연막(37)을 형성한다. Subsequently, a gate insulating film 37 is formed.

이어서, 게이트절연막(37) 상에 리세스패턴(R)에 일부 매립되고, 나머지는 실리콘기판(31) 상부로 돌출되는 게이트패턴(G)을 형성한다. 여기서, 게이트패턴(G)은 폴리실리콘전극(38), 메탈전극(39)과 게이트하드마스크(40)가 순차로 적층된 구조로 형성하되, 메탈전극(39)은 예컨대 텅스텐 또는 텅스텐실리사이드로 형성할 수 있다.Subsequently, a gate pattern G is partially formed in the recess pattern R on the gate insulating layer 37, and the remaining part protrudes over the silicon substrate 31. Here, the gate pattern G is formed of a structure in which the polysilicon electrode 38, the metal electrode 39, and the gate hard mask 40 are sequentially stacked, and the metal electrode 39 is formed of, for example, tungsten or tungsten silicide. can do.

상술한 실시예에 따르면, 본 발명은 소자분리막(35A)을 먼저 식각한 후에 실리콘기판(31)을 식각하므로써 첨점(Horn)이 없는 리세스패턴(R)을 형성할 수 있다.According to the embodiment described above, the present invention may form the recess pattern R having no horn by etching the silicon isolation layer 31 after the device isolation layer 35A is etched first.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 소자분리막을 먼저 식각한 후에 실리콘기판을 식각하므로써 첨점(Horn)이 없는 리세스패턴을 형성할 수 있으며, 이로서 균일한 셀문턱전압을 유지하여 웨이퍼내 균일한 리프레시를 확보할 수 있는 효과가 있다.According to the present invention described above, by etching the device isolation layer first, the silicon substrate is etched to form a recess-free recess pattern, thereby maintaining a uniform cell threshold voltage to ensure uniform refresh in the wafer. It has an effect.

Claims (9)

기판의 소정영역에 소자분리막을 형성하는 단계;Forming an isolation layer in a predetermined region of the substrate; 상기 기판과 소자분리막의 표면을 동시에 오픈시키는 하드마스크패턴을 형성하는 단계;Forming a hard mask pattern for simultaneously opening the surfaces of the substrate and the device isolation film; 상기 오픈된 소자분리막을 일부 식각하여 제1리세스패턴을 형성하는 단계;Partially etching the open device isolation layer to form a first recess pattern; 상기 오픈된 기판을 일부 식각하여 제2리세스패턴을 형성하는 단계;Partially etching the open substrate to form a second recess pattern; 상기 하드마스크패턴을 제거하는 단계;Removing the hard mask pattern; 상기 제1 및 제2리세스패턴이 형성된 기판 상에 게이트절연막을 형성하는 단계; 및Forming a gate insulating film on the substrate on which the first and second recess patterns are formed; And 상기 제1 및 제2리세스패턴에 일부가 매립되고 상기 기판의 표면 위로 돌출되는 형상을 갖는 게이트패턴을 형성하는 단계Forming a gate pattern having a shape partially embedded in the first and second recess patterns and protruding above the surface of the substrate; 를 포함하는 반도체소자의 리세스게이트 제조 방법.Recess gate manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1리세스패턴을 형성하는 단계는 상기 제2리세스패턴을 형성하는 단계보다 먼저 진행하는 반도체소자의 리세스게이트 제조 방법.The forming of the first recess pattern may be performed before the forming of the second recess pattern. 제1항에 있어서,The method of claim 1, 상기 제1리세스패턴을 형성하는 단계는,Forming the first recess pattern may include: 상기 기판에 대해 높은 선택비를 갖도록 하여 식각하는 반도체소자의 리세스게이트 제조 방법.A method for manufacturing a recess gate of a semiconductor device to be etched to have a high selectivity to the substrate. 제1항에 있어서,The method of claim 1, 상기 제2리세스패턴을 형성하는 형성하는 단계는,Forming to form the second recess pattern, 상기 소자분리막에 대해 높은 선택비를 갖도록 하여 식각하는 반도체소자의 리세스게이트 제조 방법.Recess gate manufacturing method of a semiconductor device to be etched to have a high selectivity to the isolation layer. 제1항에 있어서,The method of claim 1, 상기 제1리세스패턴과 제2리세스패턴은 깊이와 선폭을 동일하게 하는 반도체소자의 리세스게이트 제조 방법.And a first recess pattern and a second recess pattern having the same depth and line width. 제1항에 있어서,The method of claim 1, 상기 기판은 실리콘기판이고, 상기 소자분리막은 산화막인 반도체소자의 리세스게이트 제조 방법.And the substrate is a silicon substrate, and the device isolation layer is an oxide film. 제1항에 있어서,The method of claim 1, 상기 하드마스크패턴은 라인 패턴인 반도체소자의 리세스게이트 제조 방법.And the hard mask pattern is a line pattern. 제1항에 있어서,The method of claim 1, 상기 하드마스크패턴은 질화막인 반도체소자의 리세스게이트 제조 방법.And the hard mask pattern is a nitride film. 제1항에 있어서,The method of claim 1, 상기 소자분리막은 경사를 갖는 트렌치 내부에 매립되는 STI(Shallow Trench Isolation) 구조인 반도체소자의 리세스게이트 제조 방법.The device isolation layer is a recess trench manufacturing method of a semiconductor device having a shallow trench isolation (STI) structure embedded in the trench having a slope.
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