KR100848461B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
KR100848461B1
KR100848461B1 KR1020070082080A KR20070082080A KR100848461B1 KR 100848461 B1 KR100848461 B1 KR 100848461B1 KR 1020070082080 A KR1020070082080 A KR 1020070082080A KR 20070082080 A KR20070082080 A KR 20070082080A KR 100848461 B1 KR100848461 B1 KR 100848461B1
Authority
KR
South Korea
Prior art keywords
chemical mechanical
mechanical polishing
polishing process
semiconductor substrates
interlayer insulating
Prior art date
Application number
KR1020070082080A
Other languages
Korean (ko)
Inventor
민대홍
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020070082080A priority Critical patent/KR100848461B1/en
Application granted granted Critical
Publication of KR100848461B1 publication Critical patent/KR100848461B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device according to an embodiment may include forming an interlayer insulating film having via holes formed on a plurality of semiconductor substrates on which an element formation region and a scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on a first semiconductor substrate of the plurality of semiconductor substrates; Measuring a first profile of a first interlayer dielectric layer pattern formed in a first scribe lane region of the first semiconductor substrate; And changing a condition of the first chemical mechanical polishing process according to the first profile, and performing a second chemical mechanical polishing process on the plurality of semiconductor substrates except for the first semiconductor substrate.

Description

Method of manufacturing semiconductor device

The embodiment relates to a method of manufacturing a semiconductor device.

The semiconductor device undergoes a complicated process in which a plurality of exposure masks are overlapped and used, and alignment between the exposure masks used step by step is performed based on a mark of a specific shape.

The mark is called a photo key or alignment key and is used for layer to layer alignment between different masks or between dies for one mask.

A stepper, which is an exposure apparatus used in the manufacturing process of a semiconductor element, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment.

The stage is aligned automatically or manually with respect to the photokey, and if the photokey formed on the scribe lane is damaged, it leads to wafer scrap in a subsequent process.

Therefore, the process yield is reduced due to damage of the photo key.

The embodiment of the present invention provides a semiconductor device capable of preventing excessive polishing of the scribe lane area during a chemical mechanical polishing process for forming a tungsten (W) plug when forming a metal wiring, thereby preventing defects caused by a photokey during a subsequent process. It provides a manufacturing method.

A method of manufacturing a semiconductor device according to an embodiment may include forming an interlayer insulating film having via holes formed on a plurality of semiconductor substrates on which an element formation region and a scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on a first semiconductor substrate of the plurality of semiconductor substrates; Measuring a first profile of a first interlayer dielectric layer pattern formed in a first scribe lane region of the first semiconductor substrate; And changing a condition of the first chemical mechanical polishing process according to the first profile, and performing a second chemical mechanical polishing process on the plurality of semiconductor substrates except for the first semiconductor substrate.

The method of manufacturing a semiconductor device according to the embodiment can minimize wafer scrap in a lot unit that may occur due to excessive polishing in a chemical mechanical polishing process for forming a tungsten plug.

A method of manufacturing a semiconductor device according to an embodiment may include forming an interlayer insulating film having via holes formed on a plurality of semiconductor substrates on which an element formation region and a scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on a first semiconductor substrate of the plurality of semiconductor substrates; Measuring a first profile of a first interlayer dielectric layer pattern formed in a first scribe lane region of the first semiconductor substrate; And changing a condition of the first chemical mechanical polishing process according to the first profile, and performing a second chemical mechanical polishing process on the plurality of semiconductor substrates except for the first semiconductor substrate.

A method of manufacturing a semiconductor device according to an embodiment may include forming an interlayer insulating film having via holes formed on a plurality of semiconductor substrates on which an element formation region and a scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on the first interlayer insulating film of the first semiconductor substrate among the plurality of semiconductor substrates; Measuring a first profile of a first interlayer dielectric layer pattern formed in a first scribe lane region of the first semiconductor substrate; In accordance with the first profile, the second chemical mechanical polishing process is performed on the second interlayer insulating film of the second semiconductor substrate by changing the conditions of the first chemical mechanical polishing process, and thus the second scribe lane of the second semiconductor substrate. Measuring a second profile of a second interlayer insulating film pattern formed in the region; And modifying the conditions of the first and second chemical mechanical polishing processes in accordance with the first and second profiles to perform a third chemical mechanical polishing process on the plurality of semiconductor substrates except for the first and second semiconductor substrates. Including the step of proceeding.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 is a plan view of a semiconductor device, showing an element formation region A and a scribe lane region B. FIG.

As shown in FIG. 1, the semiconductor device is formed of an element formation region A and a scribe lane region B. As shown in FIG.

An element such as a transistor may be formed in the element formation region A, and an alignment key or photo key used for alignment of the wafer is formed in the scribe lane region B. Can be.

The photokey is formed to match the overlay of the metal wiring to be formed in the element formation region A. FIG.

2 to 5B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.

A method of manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 2 to 5B.

As shown in FIG. 2, an interlayer insulating film 20 is formed on the semiconductor substrate 10 in the element formation region A and the scribe lane region B. Referring to FIG.

Devices such as transistors may be formed in the semiconductor substrate 10 in the device formation region A.

As shown in FIG. 3, the via hole 30 is formed in the interlayer insulating film 20 to form the interlayer insulating film pattern 25.

The via hole 30 may be formed by forming a photoresist pattern on the interlayer insulating layer 20 and then performing an etching process.

The via hole 30 is formed to form a contact plug connecting a metal wiring (not shown) and an element (not shown) formed in the element formation region A. FIG.

Next, as shown in FIG. 4, tungsten (W, 40) is formed on the interlayer insulating film pattern 25 including the via hole 30.

The tungsten 40 is then subjected to a first chemical mechanical polishing process.

Since the via hole 30 of the element formation region A is denser than the via hole 30 of the scribe lane region B, the scribe lane region B is further formed during the first chemical mechanical polishing process. Excessive polishing occurs.

In this case, since the chemical mechanical polishing process is performed in units of 1 lot (1 lot = 25 wafers), the first chemical mechanical polishing process is performed only on the first semiconductor substrate among the plurality of semiconductor substrates.

At this time, the remaining plurality of semiconductor substrates are waiting for an input / output port.

After the first chemical mechanical polishing process, as shown in FIG. 5A5B, excessive polishing occurs, so that a part of the interlayer insulating layer pattern 25 of the scribe lane region B may be removed. .

Part of the interlayer insulating film pattern 25 of the scribe lane area B is removed, so that the photokey cannot be recognized, so that a scrap can be generated on the wafer since the alignment cannot be performed during the subsequent metallization process. do.

Therefore, in the present embodiment, when the photokey of the first semiconductor substrate cannot be recognized among the plurality of semiconductor substrates, the polishing conditions are changed, and as shown in FIG. 5B, the second semiconductor substrate of the plurality of semiconductor substrates is changed to the second one. The chemical mechanical polishing process may be performed to form the contact plug 45.

Subsequently, although not shown, a metal film may be formed on the interlayer insulating layer pattern 25 including the contact plug 45, and then a metal wiring may be formed by performing a photo-etching process.

6 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.

First, an interlayer insulating film is formed on a plurality of semiconductor substrates on which elements are formed, and vias are formed in the interlayer insulating film (S101).

Then, tungsten (W) is formed on the interlayer insulating film including the vias (S102).

In this case, tungsten is formed on the interlayer insulating layer in the plurality of semiconductor substrates, and is waited at an I / O port for a chemical mechanical polishing process.

Subsequently, a first chemical mechanical polishing process is performed on the first semiconductor substrate among the plurality of semiconductor substrates queued in the I / O port.

In addition, a profile of the first interlayer dielectric layer pattern formed in the first scribe lane region of the first semiconductor substrate is measured.

After measuring the profile of the first interlayer insulating film pattern, it is determined whether a first photo key formed in the first scribe lane region can be recognized (S105).

That is, it is possible to know whether the first interlayer insulating film pattern remains to the extent that the first photo key can be recognized by the profile.

If excessive polishing occurs in such a way that the first photo key formed in the first scribe lane region cannot be recognized, the polishing time of the semiconductor substrate to be subsequently performed is set using APC (Auto Parameter Control). S106)

Subsequently, a second chemical mechanical polishing process is performed on the plurality of semiconductor substrates waiting for the I / O port under the polishing conditions set again (S107).

Subsequently, the second chemical mechanical polishing process is performed to form an undamaged second photokey in the second scribe lane, and then a metal film is formed on the interlayer insulating film including the tungsten plug.

After aligning the second photo key (S109), the metal layer may be patterned by performing a photo-etching process (PEP) (S110), thereby forming a metal wire that is exactly aligned with the tungsten plug.

The method of manufacturing a semiconductor device according to the embodiment can minimize wafer scrap in a lot unit that may occur due to excessive polishing in a chemical mechanical polishing process for forming a tungsten plug.

6 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment.

First, an interlayer insulating film is formed on a plurality of semiconductor substrates on which elements are formed, and vias are formed in the interlayer insulating film (S201).

Then, tungsten (W) is formed on the interlayer insulating film including the vias (S202).

In this case, tungsten is formed on the interlayer insulating layer in the plurality of semiconductor substrates, and is waited at an I / O port for a chemical mechanical polishing process.

Subsequently, a first chemical mechanical polishing process is performed on the first semiconductor substrate among the plurality of semiconductor substrates queued in the I / O port (S203).

In addition, a first profile of the first interlayer dielectric layer pattern formed in the first scribe lane region of the first semiconductor substrate is measured (S204).

After measuring the first profile of the first interlayer insulating film pattern, it is determined whether the first photo key formed in the first scribe lane region can be recognized (S205).

That is, it may be known whether the first interlayer insulating film pattern remains to the extent that the first photo key can be recognized by the first profile.

If excessive polishing occurs in such a way that the first photo key formed in the first scribe lane region cannot be recognized, the polishing time of the semiconductor substrate to be subsequently performed is set using APC (Auto Parameter Control). S206)

Subsequently, a second chemical mechanical smoke deposition process is performed under the polishing conditions that are reset only to the second semiconductor substrate among the semiconductor substrates waiting for the I / O port (S203).

Subsequently, a second profile of the second interlayer dielectric layer pattern formed in the second scribe lane region of the second semiconductor substrate is measured (S204).

After measuring the profile of the second interlayer insulating film pattern, it is determined whether a second photo key formed in the second scribe lane region can be recognized (S205).

That is, the second profile may determine whether the second interlayer insulating film pattern remains enough to recognize the second photo key.

If the second photokey cannot be recognized, the polishing time is again set using APC (S206), and then a third chemical mechanical polishing process is performed on the third semiconductor substrate (S203), and the third scribe lane region is The third profile of the third photokey may be measured (S204).

That is, the polishing process may be repeated by adjusting the polishing condition until the photo key can be recognized, and the polishing condition may be a polishing time.

If the second photo key or the third photo key can be recognized, a fourth chemical mechanical polishing process is performed on the plurality of semiconductor substrates held in the I / O port under the same conditions as the second or third chemical mechanical polishing process. Proceed (S207).

Subsequently, the fourth chemical mechanical polishing process is performed to form an undamaged fourth photokey in the fourth scribe lane, and then a metal film is formed on the interlayer insulating film including the tungsten plug.

After aligning the fourth photo key (S209), the metal layer may be patterned by performing a PEP process (S210), thereby forming a metal wire that is exactly aligned with the tungsten plug.

The method of manufacturing a semiconductor device according to the embodiment can minimize wafer scrap in a lot unit that may occur due to excessive polishing in a chemical mechanical polishing process for tungsten plug formation.

1 is a plan view of a semiconductor device, showing an element formation region A and a scribe lane region B. FIG.

2 to 5B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.

6 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an embodiment.

7 is a flowchart illustrating a method of manufacturing a semiconductor device according to another embodiment.

Claims (7)

Forming an interlayer insulating film having via holes formed on the plurality of semiconductor substrates on which the device formation region and the scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on a first semiconductor substrate of the plurality of semiconductor substrates; Measuring a first profile of a first interlayer dielectric layer pattern formed in a first scribe lane region of the first semiconductor substrate; And And performing a second chemical mechanical polishing process on the remaining plurality of semiconductor substrates except the first semiconductor substrate. The method of claim 1, After performing the second chemical mechanical polishing process on the plurality of semiconductor substrates except for the first semiconductor substrate, Forming a metal film on the plurality of semiconductor substrates; And And aligning the photo keys formed after the second chemical mechanical polishing process and performing a photo process on the plurality of semiconductor substrates to form metal wirings. The method of claim 1, When the photo key can be recognized according to the first profile of the first interlayer insulating film pattern, the time for performing the first chemical mechanical polishing process and the time for performing the second chemical mechanical polishing process are the same. If the photo key cannot be recognized according to the first profile of the first interlayer insulating film pattern, the semiconductor device includes a time different from that of the first chemical mechanical polishing process and a time different from the second chemical mechanical polishing process. Method of preparation. Forming an interlayer insulating film having via holes formed on the plurality of semiconductor substrates on which the device formation region and the scribe lane region are formed; Forming tungsten (W) on the interlayer insulating film including the via hole; Performing a first chemical mechanical polishing process on the first interlayer dielectric layer of the first semiconductor substrate among the plurality of semiconductor substrates, and forming a first profile of the first interlayer dielectric layer pattern formed in the first scribe lane region of the first semiconductor substrate Measuring; Performing a second chemical mechanical polishing process on the second interlayer dielectric layer of the second semiconductor substrate, and measuring a second profile of the second interlayer dielectric layer pattern formed in the second scribe lane region of the second semiconductor substrate; And And performing a third chemical mechanical polishing process on the plurality of semiconductor substrates except the first and second semiconductor substrates. The method of claim 4, wherein After performing the third chemical mechanical polishing process on a plurality of semiconductor substrates except the first and second semiconductor substrates, Forming a metal film on the plurality of semiconductor substrates; And And aligning the photo keys formed after the third chemical mechanical polishing process and performing a photo process on the plurality of semiconductor substrates to form metal wirings. The method of claim 4, wherein If the photo key can be recognized according to the second profile of the second interlayer insulating film pattern, the time for performing the second chemical mechanical polishing process and the time for performing the third chemical mechanical polishing process are the same. If the photo key cannot be recognized according to the second profile of the second interlayer insulating film pattern, the semiconductor device includes a time different from that of the second chemical mechanical polishing process and a time different from the time of the third chemical mechanical polishing process. Method of preparation. The method of claim 4, wherein A time period during which the first chemical mechanical polishing process is performed and a time when the second chemical mechanical polishing process is performed are different.
KR1020070082080A 2007-08-16 2007-08-16 Method of manufacturing semiconductor device KR100848461B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070082080A KR100848461B1 (en) 2007-08-16 2007-08-16 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070082080A KR100848461B1 (en) 2007-08-16 2007-08-16 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR100848461B1 true KR100848461B1 (en) 2008-07-25

Family

ID=39825214

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070082080A KR100848461B1 (en) 2007-08-16 2007-08-16 Method of manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100848461B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030097410A (en) * 2002-06-21 2003-12-31 주식회사 하이닉스반도체 Method for preventing attack in chemical mechanical polishing process
KR20040038788A (en) * 2002-10-29 2004-05-08 실리콘 스토리지 테크놀로지 인크 Method of planarizing a semiconductor die
JP2005285904A (en) 2004-03-29 2005-10-13 Yamaha Corp Semiconductor wafer and manufacturing method therefor
KR20070013030A (en) * 2005-07-25 2007-01-30 주식회사 하이닉스반도체 Method of forming a alignment key in a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030097410A (en) * 2002-06-21 2003-12-31 주식회사 하이닉스반도체 Method for preventing attack in chemical mechanical polishing process
KR20040038788A (en) * 2002-10-29 2004-05-08 실리콘 스토리지 테크놀로지 인크 Method of planarizing a semiconductor die
JP2005285904A (en) 2004-03-29 2005-10-13 Yamaha Corp Semiconductor wafer and manufacturing method therefor
KR20070013030A (en) * 2005-07-25 2007-01-30 주식회사 하이닉스반도체 Method of forming a alignment key in a semiconductor device

Similar Documents

Publication Publication Date Title
US10373826B2 (en) Metal interconnect structure
KR0185298B1 (en) Forming method of plug for contact hole
KR100602131B1 (en) Semiconductor device and method for fabricating the same
KR100848461B1 (en) Method of manufacturing semiconductor device
JP2009081219A (en) Semiconductor wafer, semiconductor chip cut away from same semiconductor wafer, and manufacturing method of semiconductor wafer
US6706611B2 (en) Method for patterning a dual damascene with retrograde implantation
JP2009004793A (en) Method of forming alignment key of semiconductor device
JPH1022236A (en) Semiconductor device and its manufacture
KR100505414B1 (en) method for forming align key
KR100527583B1 (en) Manufacturing method for semiconductor device
KR100681679B1 (en) Method for fabricating of semiconductor device
KR100816211B1 (en) Method of fabricating semiconductor device for improving exposure alignment
KR100632627B1 (en) Manufacturing method of semiconductor device
KR100226726B1 (en) Method for forming metal interconnection layer of semiconductor device
KR100403351B1 (en) Method for forming etch monitoring box in dual damascene process
JP3788422B2 (en) Inspection method of semiconductor device
KR100571389B1 (en) Manufacturing Method of Semiconductor Device
KR100868634B1 (en) Semiconductor device and manufacturing method of semiconductor device
KR100887019B1 (en) Mask having multi overlay mark
KR100259583B1 (en) Method of aligning pattern layer of wafer
US20090001597A1 (en) Semiconductor device having an interconnect electrically connecting a front and backside thereof and a method of manufacture therefor
CN117995665A (en) Method for improving wafer warpage
KR100683387B1 (en) Semiconductor device and method of fabricating pad in the semiconductor device
KR101199436B1 (en) Method of manufacturing a semiconductor device
KR20010003781A (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee