KR100833934B1 - Multi-layer plating lead frame and method of manufacturing the same - Google Patents

Abstract

A multilayer plating lead frame for semiconductor devices and a method of manufacturing the lead frame. In the multilayer plating lead frame for semiconductor devices, a nickel plating layer, a palladium plating layer, a gold alloy plating layer, and an outermost plating layer are sequentially stacked, the nickel plating layer is nickel or nickel alloy, the palladium plating layer is palladium or palladium alloy, and the outermost plating layer is silver Or silver alloy.

The method of manufacturing a multilayer plating leadframe for semiconductor devices includes forming a nickel plating layer made of nickel or nickel alloy on the upper surface of an iron-based metal substrate, and using palladium or palladium as a main component on the upper surface of the nickel plating layer, and using any one of gold and silver. Forming an intermediate plating layer comprising a; forming a gold alloy plating layer containing gold or gold as a main component on the upper surface of the intermediate plating layer and any one of palladium and silver, and silver or silver alloy on the upper surface of the gold alloy plating layer It characterized in that it comprises the step of forming the outermost plating layer consisting of.

Description

Multi-layer plating lead frame and method of manufacturing the same

1 is a schematic plan view showing the structure of a conventional lead frame,

Figure 2 is a cross-sectional view showing an embodiment of a conventional multilayer plating lead frame,

Figure 3 is a cross-sectional view showing another embodiment of a conventional multi-layer plating lead frame,

Figure 4 is a cross-sectional view showing another embodiment of a conventional multi-layer plating lead frame,

5 is a cross-sectional view of a multi-layer plating lead frame according to an embodiment of the present invention;

Figure 6 is a cross-sectional view of a multi-layer plating lead frame according to another embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11 ... pad 12 ... inner lead

13 ... Outer lead 41 ... Metal substrate (Fe-Ni)

42 Nickel plated layer 43 Palladium plated layer

44 gold alloy plated 45 first nickel plated layer

46 1st palladium plated layer 47 1st alloy layer

48.Outer plated layer

The present invention relates to a multi-layer plating lead frame and a method of manufacturing the lead frame, and more particularly, to a lead plating lead frame (Pre-Plated Frame), the multilayer structure of the plating layer is improved to improve the laminated structure of the plated lead frame and A method for manufacturing this lead frame.

The semiconductor lead frame is one of the core components of the semiconductor package together with the semiconductor chip, and serves as a lead connecting the internal and external circuits of the semiconductor package and a support supporting the semiconductor chip. ). Such a semiconductor lead frame is typically manufactured by a stamping method or an etching method.

The stamping method is a method of punching and manufacturing a thin sheet of material sequentially transferred into a predetermined shape using a press mold apparatus, which is mainly applied to mass production of lead frames.

The etching method is a chemical etching method of forming a product by corroding a local part of a material by using a chemical, which is a manufacturing method mainly applied to a small amount of lead frame production.

The semiconductor lead frame manufactured by any one of the two manufacturing methods described above may have various structures depending on the form of mounting on the substrate, but the conventional structure is as shown in FIG. 1.

1 is a view showing the structure of a conventional lead frame. Specifically, a pad 11 for mounting a chip such as a memory device to maintain a static state, an inner lead 12 and an external circuit connected to the chip by wire bonding. It consists of a structure including an outer lead (13, outer lead) for connection with the.

The semiconductor lead frame having such a structure forms a semiconductor package through an assembly process with other components of the semiconductor, for example, a chip, which is a memory device.

The semiconductor manufacturing process can be classified into three categories: wafer manufacturing process, assembly process, and test process. The dual assembly process is generally divided into die attach, wire bonding, molding, marking and trim / form processes.

The die attaching step is a step of attaching each die on the wafer to a predetermined lead frame. Here, a die refers to an integrated circuit (IC) forming a chip. The wire bonding process is a process of connecting the die attached to the lead frame and each pin of the lead. Inside the die there is a bonding pad according to each pin number, which is connected as a wire to a lead for each pin. The molding process is a process of forming a body of each die as a package material such as plastic. The marking process is a process of marking the name of the integrated circuit and the manufacturer's symbol on the outside of the body. Finally, the separation process is a process of individually separating a series of integrated circuits attached to the lead frame, and may be divided into a process of cutting the lead frame and a process of bending the cut lead to a predetermined shape.

In order to improve the wire bonding between the semiconductor chip and the inner lead of the lead frame and the die characteristics of the die pad portion during the assembly process of the semiconductor, a metal material having predetermined characteristics is plated on the die pad 11 and the inner lead 12. In many cases, solder (Sn-Pb) plating is performed on a portion of the outer lead 13 to improve solderability for mounting the substrate after molding. However, since the plating solution frequently penetrates to the inner lead 12 in the solder plating process, there is a problem of requiring an additional process for removing the plating solution.

In order to solve this problem, a pre-plated frame method is proposed. According to this method, the structure of the plating layer is schematically illustrated in FIG. 2 as forming a plating layer by applying a material having good solder wettability to the semiconductor substrate before the semiconductor package process.

2 is a view showing the structure of the lead frame leaded. Specifically, the nickel layer 22 and the palladium / nickel alloy layer 23 are sequentially stacked as the intermediate plating layer on the copper substrate 21, and the palladium layer 24 is formed on the palladium / nickel alloy layer 23. It forms the plating layer of the multilayered structure formed with the outermost plating layer. In the multilayer plating layer, the nickel layer 22 is used to prevent the copper atoms of the copper substrate 21 from diffusing to the outermost surface to form a copper compound such as copper oxide or copper sulfide. It is formed to act as a stop layer. In addition, the intermediate plating layer including the nickel layer 22 and the palladium / nickel alloy layer 23 serves to protect the copper substrate 21 when a crack occurs in the palladium layer 24.

However, the lead method is only applied when the material of the substrate is copper or a copper alloy, but not to alloy 42 material. The alloy 42 is composed of 42% nickel, 58% iron, and a small amount of other elements, and is widely used as a lead frame material. This is because galvanic coupling is caused by a large difference in the dielectric series between the iron component of alloy 42 and palladium, which is a plated layer component.

In order to solve the above problems, a method of plating a copper or copper alloy on an alloy 42 and then plating nickel, cobalt or nickel-copper alloy thereon and plating precious metals (Pd, Au, Ag) on the same is proposed. It is. However, this could not be put to practical use for the following reasons. First, CN- is most often used as a copper plating bath. The CN-ion adsorbed during the plating process greatly degrades the adhesion and corrosion resistance of the palladium plating layer which is subsequently plated. Second, since the thickness of the intermediate plating layer of copper and nickel is too thick, cracks occur in the lead forming step, and the quality required in the semiconductor, such as solderability and wire bonding property, is inferior.

A multilayer plating leadframe for solving this problem is disclosed in Korean Laid-Open Patent Publication No. 1998-060697.

As shown in FIG. 3, the multi-layered lead frame includes a copper strike plating layer 32, a first strike plating layer 34, a nickel plating layer 35 and a palladium alloy plating layer on a substrate 31 made of alloy 42. 36 is sequentially stacked, and the first strike plating layer 34 is made of any one metal or an alloy thereof selected from the group consisting of palladium (Pd), platinum (Pt), and gold (Au). In addition, as shown in FIG. 4, between the copper strike plating layer 32 and the first strike plating layer 34, nickel (Ni), cobalt (Co), tungsten (W), and silver (Ag) may be formed. The first alloy plating layer 33 made of any one metal or an alloy thereof selected from the group may be further included. Such multilayer plated leadframes have improved corrosion resistance, solderability and wire bonding.

However, such a multilayer plating lead frame also has a too thick plating layer, causing cracks in the lead forming step, so that solderability and wire bonding properties deteriorate, and when copper is plated, copper atoms diffuse to the outermost surface and are soldered. It has the problem of dropping the sex significantly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a multilayer plating lead frame excellent in corrosion resistance, solderability, wire bonding property, and the like and a method of manufacturing the lead frame by improving the laminated structure of the plating layer. .

In order to achieve the above object, the multilayer plating leadframe for semiconductor devices of the present invention is characterized in that a nickel plating layer, a palladium plating layer, a gold alloy plating layer, and an outermost plating layer are sequentially stacked on an upper surface of an iron-based metal substrate.

In addition, the nickel plated layer is formed of nickel or nickel alloy, the thickness is 1 to 5㎛, during plating, the pulse frequency is 100 to 10,000 kHz, the duty cycle is 50 to 90%, and the periodic reverse current (PR) It is characterized in that the application.

In addition, the palladium plated layer is composed of palladium or palladium as a main component, and any one of gold and silver is added, and the thickness thereof is 0.0025 to 0.025 µm, and the pulse frequency is 1,000 to 100,000 Hz during the plating, and the duty cycle is 10 to 50. It is characterized by applying a current of%.

In addition, the gold alloy plating layer is characterized in that the main component of the gold, and any element of palladium, silver is added, the thickness is 0.0025 to 0.025㎛.

In addition, the outermost plating layer is made of silver or silver alloy and its thickness is 0.005 to 0.5㎛, the plating pulse frequency is 100 to 10,000 kHz, the duty cycle is characterized in that by applying a current of 50 to 90% .

In addition, another embodiment of the multi-layer plating lead frame of the present invention for achieving the above object is a nickel plated layer, a palladium plated layer and a gold alloy plated layer is sequentially laminated two to three times and the outermost plating layer is laminated on the upper surface, the nickel plated layer Silver nickel or nickel alloy and the palladium plating layer is palladium or palladium alloy and the outermost plating layer is characterized in that the silver or silver alloy.

In addition, an embodiment of the manufacturing method of the multi-layer plating lead frame of the present invention for achieving the above object, the step of forming a nickel plated layer made of nickel or nickel alloy on the upper surface of the metal substrate, the palladium on the upper surface of the nickel plated layer Forming a palladium plated layer containing one of gold and silver as a main component, and forming a gold alloy plated layer containing gold as a main component and one of palladium and silver added to the upper surface of the palladium plated layer And forming an outermost plating layer made of silver or silver alloy on the upper surface of the gold alloy plating layer.

Hereinafter, a multilayer plating lead frame and a method of manufacturing the lead frame according to a preferred embodiment of the present invention with reference to the accompanying drawings.

Referring to FIG. 5, in the multilayer plating lead frame according to the exemplary embodiment of the present invention, the nickel plating layer 42, the palladium plating layer 43, and the gold alloy plating layer 44 are formed on the upper surface of the metal substrate 41 constituting the semiconductor lead frame. , The outermost plating layer 48 is sequentially stacked.

The metal substrate 41 is composed of 42% of nickel (Ni), 58% of iron (Fe), and a small amount of other elements.

The nickel plating layer 42 is formed on the upper surface of the metal substrate 41. The nickel plating layer 42 is formed of nickel or nickel alloy. The nickel plating layer 42 is formed on the upper surface of the alloy 42 material to reduce the surface potential difference with the metal substrate 41 to prevent corrosion of the metal substrate. The nickel plated layer 42 has a thickness of 1 to 5 µm, a plating pulse frequency of 100 to 10,000 Hz, and a duty cycle of 50 to 90% of a current applied. When the thickness of the nickel plated layer is 1 μm or less, there is almost no corrosion preventing effect. When the thickness of the nickel plated layer is 5 μm or more, it becomes thick and cracks are likely to occur during forming. If the pulse frequency is 100 Hz or less, it is hardly effective in improving the corrosion resistance. If the pulse frequency is 10,000 Hz or more, the grains of nickel are denser and cracks are severe during forming. In the duty cycle, the current application time becomes longer at 50% or less, and the nickel grains are dense, resulting in severe cracking during forming, and in the case of 90% or more, the corrosion cycle hardly occurs due to little effect on improving corrosion resistance.                     

The palladium plating layer 43 is formed on the upper surface of the nickel plating layer 42. The palladium plating layer 43 is plated with an alloy formed of palladium as a main component and added with any one of gold and silver. The palladium plated layer 43 made of a noble metal such as palladium, gold, and silver can conceal pores on the surface of the nickel plated layer 42 and make the surface roughness uniform, thereby uniformizing the thickness of the gold alloy plated layer 44 to be electrodeposited. I can keep it. This has the effect of significantly reducing local corrosion, which is a typical corrosion phenomenon under a salty atmosphere. In addition, the palladium plating layer 43 serves as a medium for increasing the bonding force between the nickel plating layer 42 and the gold alloy plating layer 44. Through the strengthening of the adhesive force, it is possible to minimize the generation and progress of the micro cracks generated during the trimming and forming process after mounting the semiconductor chip on the pad of the lead frame. The palladium plating layer 43 has a thickness of 0.0025 to 0.025 µm, and is preferably plated by applying a current having a pulse frequency of 1,000 to 100,000 Hz and a duty cycle of 10 to 50%. If the thickness of the palladium plated layer 43 is reduced to 0.0025 μm or less, the above function cannot be achieved. If the thickness of the palladium plated layer 43 is less than 0.025 μm, the manufacturing cost increases, but the quality characteristic does not increase any more. If the pulse frequency is 1,000 kHz or less, there is almost no effect on the prevention of local corrosion. If the duty cycle is less than 10%, microcracks of the palladium plated layer are generated during forming, and if more than 50%, local corrosion is severely generated.

The gold alloy plating layer 44 is formed on the upper surface of the palladium plating layer 43. The gold alloy plated layer 44 has gold as its main component, and any one of palladium and silver is added thereto. The gold alloy plating layer 44 has a thickness of 0.0025 to 0.025㎛. Corrosion resistance is improved as the thickness of the gold alloy plating layer 44 is thicker than 0.0025 μm. If the thickness of the gold alloy plating layer 44 is 0.025㎛ or more, it is not economical. The gold alloy plating layer 44 serves to reduce the potential difference with the outermost plating layer 48 by increasing the surface potential of the alloy 42 to prevent corrosion. In addition, by forming the gold alloy plating layer 44, the adhesion to the outermost plating layer 48 to be subsequently electrodeposited is improved.

The outermost plating layer 48 is formed on the upper surface of the gold alloy plating layer 44. The outermost plating layer 48 is made of silver or an alloy thereof. An alloy with gold is preferable at the time of alloying. In the case of silver or an alloy of silver, the bonding property with the wire may be improved during wire bonding due to the silver present in the outermost plating layer 48. In addition, by plating on the gold alloy plating layer 44 using the high oxidation resistance of silver, it is possible to effectively prevent oxidation of the surface of the palladium plating layer 43 to improve solderability. However, if the outermost plating layer 48 is formed of pure gold, the outermost plating layer 48 is formed when the sealing resin used for molding the semiconductor package is bonded to the outermost plating layer 48 of the lead frame. Poor bonding strength between resin and resin causes mold delamination defects, and also reduces the reliability and defects due to the bonding between the outermost plating layer 48 and the resin surface during package reliability test after packaging. Cause. And, if the outermost plating layer 48 is formed of pure gold, the lead wettability is good at the time of soldering, but has local brittleness due to the interaction of tin and gold in the solder, so that the semiconductor is mounted on the substrate. Later, there is a problem of brittleness in the soldering portion due to external impact or the like, so that the outermost plating layer 48 forms a plating layer of silver or an alloy thereof. In addition, when gold is limitedly applied to the outermost plating layer 48 as an alloy with silver, the resin bonding property of the semiconductor package may be improved and local brittleness may be minimized after mounting of the substrate. In addition, since the alloy of silver and gold has better corrosion resistance than pure gold, the corrosion resistance can be increased. This is one of the factors that determine the corrosiveness of the palladium plated layer 43 is the amount of hydrogen (hydrogen storage amount) diffused into the plating layer when the plating layer is formed, which is very small alloy of silver and gold compared to pure palladium. Because. The outermost plating layer 48 has a thickness of 0.005 to 0.5 μm, and at a pulse frequency of 100 to 10,000 kHz and a duty cycle of 50 to 90%, corrosion resistance and adhesion to the mold can be further improved than when using a DC current.

Referring to FIG. 6, in the multilayer plating lead frame according to another embodiment of the present invention, the nickel plating layer 42, the palladium plating layer 43, and the gold alloy plating layer 44 are sequentially stacked on the upper surface of the metal substrate 41. The outermost plating layer 48 is plated on the upper surface thereof. That is, the nickel plating layer 42, the palladium plating layer 43, the gold alloy plating layer 44, the first nickel plating layer 45, the first palladium plating layer 46, the first gold alloy plating layer 47, the outermost plating layer 48 It is stacked in this order.

Here, the same reference numerals as in the above-described drawings indicate the same members having the same function, and the detailed description thereof will be omitted since they are substantially the same as described above.

It is preferable that the 1st nickel plating layer 45 is 1-5 micrometers which is the same thickness as the said nickel plating layer 42. FIG. The first nickel plating layer 45 plays the same role as the nickel plating layer 42.

It is preferable that the 1st palladium plating layer 46 is 0.0025-0.025 micrometer. The first palladium plating layer 46 is formed on the bottom surface of the first alloy plating layer 47 and the outermost plating layer 48 and is formed to be thicker than the palladium plating layer because it is a plating layer for improving solderability and wire bonding property.

The effect of the leadframe according to the present invention can be more clearly understood by the following experiment.

Experimental Example 1

In this experiment, the multilayer plated lead frame of the present invention was used as an alloy of iron and nickel of 0.127mm, and the experiment was conducted as described below. At the time of forming the outermost plating layer, a sample was made of silver. The outermost plating layer is formed to a thickness of 0.025 μm. The first comparative sample was a sample in which copper (0.25 μm), nickel (1.5 μm), palladium (0.025 μm), gold (97%)-palladium (3%) alloy (0.005 μm) were sequentially stacked on a metal substrate. The second comparison sample is a sample in which silver (0.25 μm) is formed on the outermost side of the first comparison sample. The third comparative sample is a sample in which nickel (3 μm), palladium (0.025 μm) and gold-palladium alloy (0.005 μm) were sequentially stacked on a metal substrate. In the comparative sample, copper was plated with Cu current 100g / l, Cyanide 80g / l, pH 10.5, temperature at 65 ° C. with an average current density of 5A / dm 2, and nickel sulfamic acid using DC current. In the nickel bath, plating was performed at an average current density of 20 A / dm 2 at 120 g / l nickel, 35 g / l boric acid, 6 g / l nickel chloride, and pH 3.5 at 60 ° C. The palladium plated layer had an average current density of 2 A / dm 2, The gold alloy plated layer was plated using an average current density of 0.50 A / dm 2, the silver plated layer using an average current density of 1 A / dm 2 and a DC current.

The first embodiment sample is a sample in which nickel (3 μm), palladium (0.025 μm), gold (97%)-palladium (3%) alloy (0.005 μm), and silver (0.25 μm) are sequentially stacked on the metal substrate. In this case, the nickel condition was produced with an average current density of 20 A / dm 2 using a duty cycle of 80% pulse and a periodic reverse current (PR) frequency of 100 Hz, and palladium averaged using a duty cycle of 20% frequency of 10,000 mA. The current density was 2A / dm 2, and the gold alloy plated layer was fabricated with an average current density of 0.5A / dm 2 using DC current. The silver plating layer had a pulse condition of 90% duty cycle, a frequency of 1,000 Hz, and an average current density of 1A /. Plating was carried out using dm 2. The sample for the second embodiment was prepared on the metal substrate in the same manner as the production conditions of the sample for the first embodiment, and the nickel (1.5 μm), palladium (0.01 μm), gold-palladium alloy (0.0025 μm), nickel (1.5 μm), and palladium ( 0.025 μm), a gold-palladium alloy (0.005 μm), and an outermost plating layer of silver.

Corrosion resistance was evaluated based on the salt spray test (JESD22-A107-A). The concentration of sodium chloride (Nacl) was 3.5%, and the salt spray was sprayed with 35 g of sodium chloride every 24 hours. In addition, the solderability test conditions were heated in a furnace at 175 ° C. for 2 hours and then steam aged at 93 ° C. for 8 hours and 16 hours. After that, the solder temperature was 245 ° C and deposited for 5 seconds.

Table 1 shows the measurement results for corrosion resistance and solderability.

Sample First Comparative Materials Second comparison book Third Comparative Materials First embodiment Second embodiment Corrosion resistance Partial corrosion No corrosion Partial corrosion No corrosion No corrosion Steam Aging 8 hours Solderability (Before Bending) 100% 100% 100% 100% 100% Solderability (After Bending) 100% 100% 100% 100% 100% Steam Aging 16 hours Solderability (Before Bending) 100% 100% 100% 100% 100% Solderability (After Bending) 40% 70% 90% 100% 100%

In addition, test conditions for wire bonding are as follows.

The gold wire used for bonding is 0.95 mm in diameter and is rated at 40 pieces. Bonding power and bonding force at the chip site and inner lead are 60mW, 100mN, 60mW, and 100mN, respectively. And it carries out at the temperature of 230 degreeC.

Table 2 shows the measurement results of the breaking strength of the wire bonded by the lead wire at the intermediate point between the inner lead of the lead frame and the bonding part of the chip.

Sample  First Comparative Materials  Second Comparative Materials Third Comparative Materials First embodiment First embodiment Bondability (average) 6.32 g 8.55 g 7.23 g 9.49 g 9.81 g Opening rate  12%   0% 0% 0%  0%

The mold adhesion test conditions are as follows.

EMC measured shear strength using Cheil Industries' 7300MES. Molding temperature is carried out at 175 ℃, mold cured at 175 ℃ for 4 hours, temperature is maintained at 85 ℃, humidity at 168 hours at 168 hours, and after reaching maximum reflow temperature of 245 ℃ (3 times) Shear Strength was measured using a Strength Tester.

Sample First Comparative Materials Second comparison book Third Comparative Materials First embodiment Second embodiment Shear Strength (kgf) 8.37 62.7 9.1 68.5 70.9 Delamination 100% 20% 90% 10% 10%

As shown in Tables 1, 2, and 3 above, it can be seen that corrosion resistance, solderability, wire bonding property, and mold adhesion of the present invention are greatly improved.

As described above, the multilayer plating lead frame and the method of manufacturing the lead frame according to the present invention improve the overall characteristics of the lead frame such as corrosion resistance, wire bonding property and solderability by improving the laminated structure of the plating layer, It is possible to improve the adhesive strength of the semiconductor package, thereby increasing the yield in the semiconductor package process, and thus improving the productivity.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

Claims (9)

A nickel plating layer, a palladium plating layer, a gold alloy plating layer and the outermost plating layer are sequentially stacked, the nickel plating layer is nickel or nickel alloy, the palladium plating layer is palladium or palladium alloy and the outermost plating layer is silver or silver alloy. Multilayer plating leadframe for semiconductor devices. The method of claim 1, The nickel plating layer is a multilayer plating lead frame for a semiconductor device, characterized in that formed by a pulse periodic reverse current plating method. The method of claim 1, The nickel plated layer is a multilayer plating lead frame for a semiconductor device, characterized in that the thickness of 1 to 5㎛. The method of claim 1, The palladium plating layer is a multilayer plating lead frame for a semiconductor device, characterized in that the thickness of 0.0025 to 0.025㎛. The method of claim 1, The palladium plating layer is a multilayer plating lead frame for a semiconductor device, characterized in that formed by the pulse plating method. The method of claim 1, The gold alloy plating layer has a thickness of 0.0025 to 0.025㎛ multi-layer plating lead frame for a semiconductor device. The method of claim 1, The outermost plating layer is a multilayer plating lead frame for a semiconductor device, characterized in that the thickness of 0.005 to 0.5㎛. The nickel plating layer, the palladium plating layer and the gold alloy plating layer are sequentially stacked two times, and the outermost plating layer is laminated on the upper surface, the nickel plating layer is nickel or nickel alloy, the palladium plating layer is palladium or palladium alloy, and the outermost plating layer is silver or silver alloy. A multilayer plating lead frame for semiconductor devices, characterized in that it is gold. Forming a nickel plating layer made of nickel or a nickel alloy on an upper surface of the iron-based metal substrate; Forming an intermediate plating layer including palladium or palladium as a main component on an upper surface of the nickel plating layer and including any one of gold and silver; Forming a gold alloy plating layer including gold or gold as a main component on the upper surface of the intermediate plating layer, and one of palladium and silver added thereto; And And forming an outermost plating layer made of silver or silver alloy on the top surface of the gold alloy plating layer.

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