KR100812554B1 - 디지탈 신호 처리기용의 타이밍 복원 회로망 - Google Patents

디지탈 신호 처리기용의 타이밍 복원 회로망 Download PDF

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Publication number
KR100812554B1
KR100812554B1 KR1020050071968A KR20050071968A KR100812554B1 KR 100812554 B1 KR100812554 B1 KR 100812554B1 KR 1020050071968 A KR1020050071968 A KR 1020050071968A KR 20050071968 A KR20050071968 A KR 20050071968A KR 100812554 B1 KR100812554 B1 KR 100812554B1
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KR
South Korea
Prior art keywords
signal
interpolator
transmitter
coupled
sample
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Expired - Lifetime
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KR1020050071968A
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English (en)
Korean (ko)
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KR20070095473A (ko
Inventor
고다드 크누트슨 폴
라마스와미 쿠마
로웰 맥닐리 데이빗
Original Assignee
톰슨 콘슈머 일렉트로닉스, 인코포레이티드
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Priority claimed from KR1019970007028A external-priority patent/KR100745382B1/ko
Application filed by 톰슨 콘슈머 일렉트로닉스, 인코포레이티드 filed Critical 톰슨 콘슈머 일렉트로닉스, 인코포레이티드
Publication of KR20070095473A publication Critical patent/KR20070095473A/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H04L7/0335—Gardner detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multimedia (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Synchronizing For Television (AREA)
  • Details Of Television Systems (AREA)
KR1020050071968A 1996-02-27 2005-08-05 디지탈 신호 처리기용의 타이밍 복원 회로망 Expired - Lifetime KR100812554B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1233996P 1996-02-27 1996-02-27
US012,339 1996-02-27
US721,780 1996-09-25
US08/721,780 US5943369A (en) 1996-02-27 1996-09-25 Timing recovery system for a digital signal processor
KR1019970007028A KR100745382B1 (ko) 1996-02-27 1997-02-27 디지탈신호처리기용의타이밍복원회로망

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1019970007028A Division KR100745382B1 (ko) 1996-02-27 1997-02-27 디지탈신호처리기용의타이밍복원회로망

Publications (2)

Publication Number Publication Date
KR20070095473A KR20070095473A (ko) 2007-10-01
KR100812554B1 true KR100812554B1 (ko) 2008-03-13

Family

ID=26683446

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050071968A Expired - Lifetime KR100812554B1 (ko) 1996-02-27 2005-08-05 디지탈 신호 처리기용의 타이밍 복원 회로망

Country Status (10)

Country Link
US (1) US5943369A (enExample)
EP (1) EP0793363B1 (enExample)
JP (2) JP4212067B2 (enExample)
KR (1) KR100812554B1 (enExample)
CN (1) CN1157904C (enExample)
BR (1) BR9700851B1 (enExample)
DE (1) DE69738879D1 (enExample)
ID (1) ID16554A (enExample)
MY (1) MY114450A (enExample)
SG (1) SG64965A1 (enExample)

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US6421396B1 (en) * 1997-04-16 2002-07-16 Broadcom Corporation Variable rate modulator
TW371758B (en) * 1997-06-04 1999-10-11 Siemens Ag Method to optimize the signal-propagation-time in a reprogrammable switching circuit and reprogrammable switching circuit with program-code optimized in said signal-propagation time
GB2331210A (en) * 1997-09-12 1999-05-12 Daewoo Electronics Co Ltd Timing recovery in vestigial sideband modulation
US6144712A (en) 1997-10-09 2000-11-07 Broadcom Corporation Variable rate modulator
US6128357A (en) * 1997-12-24 2000-10-03 Mitsubishi Electric Information Technology Center America, Inc (Ita) Data receiver having variable rate symbol timing recovery with non-synchronized sampling
JP3363768B2 (ja) * 1997-12-26 2003-01-08 株式会社ケンウッド ディジタル復調器
US6351293B1 (en) * 1998-05-18 2002-02-26 Sarnoff Corporation Decision directed phase detector
US6381291B1 (en) * 1998-09-28 2002-04-30 Harris Corporation Phase detector and method
KR100324749B1 (ko) * 1998-10-09 2002-03-13 구자홍 최대 가능성 심볼 타이밍 복원기
US6563862B1 (en) * 1998-10-21 2003-05-13 Thomson Licensing Sa Digital variable symbol rate modulation
US6370160B1 (en) * 1998-12-29 2002-04-09 Thomson Licensing S. A. Base to handset epoch synchronization in multi-line wireless telephone
EP1052800B1 (fr) * 1999-05-11 2006-09-20 Koninklijke Philips Electronics N.V. Système de transmission et récepteur avec dispositif de décimation
KR100346783B1 (ko) * 1999-07-19 2002-08-01 한국전자통신연구원 보간 필터를 사용한 타이밍 복원장치 및 방법
US7039139B1 (en) * 1999-07-21 2006-05-02 Honeywell International Inc. System for increasing digital data demodulator synchronization timing resolution using training sequence correlation values
US6480535B1 (en) * 1999-07-26 2002-11-12 Sony Corporation Generating multi-channel outputs simultaneously in a receiver using polyphase filter
US6545532B1 (en) * 1999-09-08 2003-04-08 Atmel Corporation Timing recovery circuit in a QAM demodulator
US6600495B1 (en) 2000-01-10 2003-07-29 Koninklijke Philips Electronics N.V. Image interpolation and decimation using a continuously variable delay filter and combined with a polyphase filter
DE10002964A1 (de) * 2000-01-25 2001-07-26 Philips Corp Intellectual Pty Anordnung zur Filterung digitaler Daten
US6816328B2 (en) 2000-06-20 2004-11-09 Infineon Technologies North America Corp. Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel
DE60132425T2 (de) * 2000-10-11 2009-02-26 Ntt Electronics Corp. Phasenvergleichsschaltung
US6993104B2 (en) * 2001-04-27 2006-01-31 Adtran, Inc. Apparatus and method for adaptively adjusting a timing loop
US6775341B2 (en) 2001-11-30 2004-08-10 Motorola, Inc. Time recovery circuit and method for synchronizing timing of a signal in a receiver to timing of the signal in a transmitter
US20030149907A1 (en) * 2001-12-26 2003-08-07 Singh Chandra Mauli Method and apparatus for uplink clock extraction in a communication system
EP1588263A4 (en) * 2003-01-17 2006-09-27 Thomson Licensing METHOD FOR USING A SYNCHRONOUS SENSING DESIGN IN A FESTRATIVE SENSING MODE
US7450655B2 (en) * 2003-07-22 2008-11-11 Intel Corporation Timing error detection for a digital receiver
DE10334064B3 (de) * 2003-07-25 2005-04-14 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Kalibrieren eines den Abtastzeitpunkt eines Empfangssignals beeinflussenden Abtastungssteuersignales eines Abtastphasenauswahlelements
KR100752735B1 (ko) * 2006-04-10 2007-08-28 삼성전기주식회사 패킷기반 무선통신의 타이밍 위상 오차 검출 시스템 및 그검출 방법
US8045670B2 (en) * 2007-06-22 2011-10-25 Texas Instruments Incorporated Interpolative all-digital phase locked loop
GB0815458D0 (en) * 2008-08-26 2008-10-01 Zarlink Semiconductor Inc Method of transferring timing information over packet network
KR20160037656A (ko) * 2014-09-29 2016-04-06 삼성전자주식회사 에러 검출기 및 발진기의 에러 검출 방법
US11038602B1 (en) 2020-02-05 2021-06-15 Credo Technology Group Limited On-chip jitter evaluation for SerDes
US10992501B1 (en) 2020-03-31 2021-04-27 Credo Technology Group Limited Eye monitor for parallelized digital equalizers
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US20240106688A1 (en) * 2022-09-28 2024-03-28 Texas Instruments Incorporated Joint Timing Recovery and Decision Feedback Equalizer Adaptation in Wireline Network Receivers

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Also Published As

Publication number Publication date
MY114450A (en) 2002-10-31
SG64965A1 (en) 1999-05-25
JPH09247569A (ja) 1997-09-19
MX9701490A (es) 1998-06-30
EP0793363A3 (en) 2004-07-07
CN1168027A (zh) 1997-12-17
BR9700851A (pt) 1998-09-01
JP4974247B2 (ja) 2012-07-11
KR20070095473A (ko) 2007-10-01
JP4212067B2 (ja) 2009-01-21
BR9700851B1 (pt) 2009-08-11
EP0793363A2 (en) 1997-09-03
EP0793363B1 (en) 2008-08-06
ID16554A (id) 1997-10-16
US5943369A (en) 1999-08-24
HK1005396A1 (en) 1999-01-08
JP2008301537A (ja) 2008-12-11
DE69738879D1 (de) 2008-09-18
CN1157904C (zh) 2004-07-14

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