MXPA97001490A - Time recovery system for a digital signal processor - Google Patents

Abstract

The present invention relates to a time recovery network in a digital signal processing system for receiving a signal representing successive symbols from a transmitter, comprising: a source of samples representing the received signal, an interpolator coupled to the source of samples and responding to a control signal representing a predetermined delay signal from a controlled delay network, to produce samples taken at times synchronized to successive symbols from the transmitter, and a control network to provide the signal of control, the control network that includes the controlled delay network that responds to (a) an output signal of the interpolator and to (b) a delay deviation signal nomin

Description

TIME RECOVERY SYSTEM FOR A DIGITAL SIGNAL PROCESSOR This invention relates to a digital signal processing system. In particular, the invention relates to a time recovery system suitable for use in a digital signal receiver, such as a television signal receiver. The retrieval of data from a transmitted signal containing digital video and related information in a digital receiver usually requires the implementation of three time recovery functions for symbol synchronization, bearer recovery (frequency demodulation) and equalization. The recovery of time, is the process by which the receiver clock (time base) is synchronized with the relay transmitter. This allows the received signal to be tested at the optimum point in time to reduce the opportunity for a division error associated with the decision-directed processing of received symbol values. In some receivers, the received signal is tested in a multiple circuit of the transmitter symbol rate. For example, some receivers test the received signal at twice the rate of the transmitter symbol. In any case, the test relay of the receiver must be synchronized with the symbol clock of the transmitter. The recovery of the conveyor is the process by which a received RF signal, after the frequency is changed to a lower intermediate frequency step band, is a frequency changed to the baseband to allow the retrieval of the information from modulated base band. Equalization is a process which compensates for the effects of alterations in the transmission channel on the received signal. More specifically, equalization removes the interference between symbols (ÍES) caused by alterations of the transmission channel, causing the value of a given symbol to be altered by the values of preceding and subsequent symbols. This and other related functions are described in more detail by Lee and Messerschmitt in Digital Communication (Kluwer Academic Press, Boston, MA, USA). The above receivers required a relatively stable source of a test clock signal, still controllable so that it could be set to the symbol clock of the transmitter. For this function controlled crystal oscillators (VCXOs) were used. The clock signal produced by a VCXO is stable, but controllable on a relatively narrow scale, so that it can be set to the symbol clock of the transmitter. However, a voltage oscillator controlled tai such as VCXO is an analogous component, so it is relatively expensive, and tends to be derived during its lifetime. In addition, it is necessary to receive signals from different transmitters that have different symbol clock frequencies (such as in European satellite systems), it is necessary to have a separate VCXO for each of said transmitters, further increasing the cost of the receiver.

It is convenient to provide a symbol time recovery system that can support more than one set of symbols. It is further considered convenient to provide such a time recovery system that offers performance benefits and cost benefits such as in terms of hardware requirements, compared to known types of time recovery systems, for example, those that include multiple VCXOs for each regime of symbols received. In accordance with the principles of the present invention, a time recovery system for a digital signal receiver receives a signal, representing successive symbols of a transmitter. An interpolator coupled to the symbol source responds to a control signal to produce samples taken at times synchronized with the successive symbols of the transmitter. A control network that provides the control signal includes a delayed controlled network that responds to an output signal from said interpolator and to a nominal delay deviation signal. More specifically, the system comprises a source of samples representing the received signal, the samples taken at a fixed frequency. An interpolator is coupled to the sample source and responds to a control signal. The interpolator produces samples taken at times synchronized with the successive symbols of the transmitter. A phase error detector is coupled to the interpolator, detects a phase error between the sample times of the synchronized samples of the transmitter produced by the interpolator and the successive times of the transmitter symbols, and supplies a phase error signal . The phase error signal is coupled to an input terminal of an adder and a nominal delay signal source is coupled to the other. A numerically controlled delay produces the control signal for the interpolator in response to the adder signal. A time recovery system according to the present invention operates by initially testing the received signal at a fixed frequency slightly greater than twice the highest symbol rate of the desired transmitter. The signal initially tested is then processed by an interpolator to generate a sequence of samples synchronized with the symbol regime of the transmitter. These synchronized samples are supplied to a digital phase error detector. The output of the digital phase error detector is supplied to a second order closed loop filter. A predetermined value, representing a nominal test time delay, is added to the output signal of the closed loop filter. The combination of the predetermined nominal delay and the output signal of the closed-loop filter controls a numerically controlled delay which provides signals of integer and fractional clock delay components. The integer portion of the clock delay component signal is used to control the production of the receiver's test clock signal at the symbol rate of the transmitter. This test clock signal can be further divided into frequency to provide a clock signal of receiver symbols. The fractional portion of the delay component is applied to a control input of the interpolation filter so that the tested signal produced by the interpolation filter represents the value of the received signal at the desired test time. A time recovery system according to the present invention advantageously supports the time recovery of the variable symbol rate, without requiring the use of multiple analog crystal oscillators with controlled voltage for symbol time reference. This is achieved by entering the predetermined nominal delay in the closed time control circuit. A nominal delay record, which can be controlled by a processor in the receiver, allows the choice of any test regime of the desired receiver, less than half of the initial test regime. The problems associated with the use of multiple specific crystal oscillators for specific symbol regimes, such as increased hardware complexity and cost and acquisition time depending on how quickly the tuner frequencies can be avoided. The digital system described, performs the function of the voltage controlled crystal oscillator, advantageously allowing the use of a single fixed frequency oscillator. For a receiver that tests the input signal at twice the symbol rate of the transmitter below half the initial fixed test regime. The required frequency accuracy is easily obtained with available crystals, given that the scale of tested takes is greater than +/- 1000 ppm. It has been proven and shown that the system manages to set the time in a relatively short period, revealing the constellation after 500 samples and fixing the constellation after a few thousand samples, even with a time deviation of 1000 ppm. The performance advantages, combined with the elimination of a VCXO, make the system of the present invention attractive even in cases involving a single symbol regime. More specifically, the described system advantageously supports multiple symbol schemes such as those used in European satellite applications. In the example discussed above, the receiver tests the input signal at twice the symbol rate of the transmitter. For example, it has been shown that the described time recovery system supports symbolic regimes of 20 million symbols per second (M symbols / sec) at 30 M symbols / sec, using an initial clock frequency of 62 MHz. This gives ratios of initial frequency from test clock to clock frequency of symbols of 62/30 and 62/20. In these expressions, the numerator is the test regime starts! (MHz) of a single controlled oscillator of fixed crystals. Brief Description of the Drawings In the drawing: Figure 1 is a block diagram representation of a receiver for a QPSK modulated input signal including a time recovery network according to principles of the present invention; Figure 2 is a block diagram of a symbol time recovery system according to the principles of the present invention; Figure 3 is a more detailed block diagram of an interpolator used in the system of Figure 2; and Figure 4 is a more detailed block diagram of a phase error detector used in the system of Figure 2. Figure 1 is a block diagram of a receiver of a QPSK modulated input signal, v .gr., a direct diffuser satellite receiver, including a time recovery network according to principles of the present invention. The blocks shown in Figure 1 have a conventional function and arrangement, except for the unit 266 which is a symbol time recovery network, according to the present invention. An input terminal (INPUT) is coupled to a source (not shown) of a modulated QPSK signal, such as an antenna or cable connection. The input terminal (INPUT) is coupled to an input processor 262 which includes a tuner of input channels, amplifiers of FR (radio frequency), an amplifier of Fl (intermediate frequency) and mixer stage to convert in an inverted manner the input signal to a lower frequency band suitable for further processing an automatic gain corrtrol network and an analog to digital output (CAD) converter, none of which is shown, but all of which are arranged in a known manner . A fixed frequency oscillator 261, which, for example, can be a crystal oscillator, provides a fixed test frequency clock AD to the CAD, and to the other elements of the circuit (e.g. time 266) in a manner that will be described in more detail below. A baseband output signal near unit 262 is provided to a time recovery network 266 according to the invention. The time recovery network 266, produces samples representing the transmitted signal that is synchronized to the symbol clock of the transmitter, and other time signals, in a manner that will be described in greater detail below. In the illustrated mode, two samples are produced per transmitted symbol. A carrier recovery network 64 is provided with synchronized samples from the transmitter and other time signals, which demodulate the signal to the baseband and include an equalizer, rotor, splitter, phase error detection network, as well as a controller. of phases to control the operation of the equalizer and rotor, as it is known. The demodulated signal of the baseband of the vehicle recovery unit 264 is decoded by the Viterbi decoding unit 272 and is deinterestratified by the deinterestrating unit 274 before having errors detected and corrected by the error detection and correction unit. Reed-Solomon 276. The functions of these units are described, for example, in the text of Lee and Messerschmitt previously mentioned, among others. The error corrected signal from the Reed-Solomon error detection and correction unit 276 is optionally delaminated in the delaminating unit 278. The signal from the delaminating unit 278 is provided to an output processor 280, which supplies the functions necessary to form an interface between the demodulated data with other signal processing networks. These functions include shaping the data at appropriate logical levels and providing clock signals to facilitate the formation of interfaces with other networks. The data from the output processor 280 is processed by an MPEG 282 compatible transport processor, which provides synchronization and error indication information used in decompression of video data., although MPEG compatibility is not essential in a system starting with the present invention. The transport processor 282 also separates data according to the type based on a header information analysis. The output data of the processor 282 is decompressed by the MP EG 284 to provide suitable video data for encoding them in a predetermined format, such as NTSC or PAL, for example, the video coding unit 286. The signals of the video encoder unit 286, apply to a video and display processor 288, which includes an image display device (not shown). A system microprocessor 268 provides initialization parameters and other control signals to the respective elements in the receiver in a known manner, including the time recovery network 266. The specific parameter and control signals provided by the system microprocessor 268 to the time recovery network 266, will be described in more detail below. Figure 2 is a more detailed block diagram of a symbol time recovery system according to the principles of the present invention. In Figure 2, analog or simple digital signals are illustrated by thin lines and complex digital signals, comprising signals of real (in phase) and imaginary (quadrature) components in a known manner, illustrated as thick lines. In the symbol time recovery system shown in Figure 2, advantageous aspects include a nominal delay record that allows a designer to choose any desired symbol regime less than half the sample entry rate and the ability to use a more precise interpolator design for higher order constellations. The derivation of clocking signals of symbols and samples at the output of a numerically controlled delay operation advantageously allows a completely synchronous design without requiring analogous components to block the phase and the frequency. In Figure 2, an analog input signal IN, which represents a signal received from a transmitter, is initially tested and converted to a complex digital form by an analog-to-digital converter (CAD) 19 (which is part of the processor). input 262 in Figure 1). CAD 10 is clocked by the fixed frequency sample clock AD locally generated by the fixed frequency crystal oscillator 261 (of FIG. 1). The complex digital data stream of CAD 10 is applied to a complex 4-socket current interpolator 12 (described in more detail below) which is also secured by the fixed-frequency initial sample clock signal AD. The interpolation function described above is essentially a time-adjustment function and has sometimes been referred to as a rate conversion and digital phase test. The output of the interpolator 12 is a stream of complex samples, produced in synchronism with fixed frequency sample clock signal AD, which is subjected to filtering in the form of pulses by the filter 14 in the form of fixed complex pulses (not adaptable) , which is responsible for the fixed frequency sample clock signal AD and a signal that enables the sample clock (generated as described below). The output of the filter 14 is a stream of filtered complex samples, which is provided to other system units illustrated in Figure 1. The output of the interpolator 12 is also applied to a phase error detector 16 (described in more detail more ahead). The output of the phase error detector 16 is coupled to the respective dividers 20 and 22, which in the embodiment illustrated, are implemented as barrel changers. An integral constant Ki of the closed-loop filter is applied to the exchanger 20, and a proportional constant Kp of the closed circuit, is applied to the exchanger 22. The values of the integral constant Ki of the closed circuit and the proportional constant Kp of the closed circuit are calculated by the microprocessor of the system 268 (of Figure 1) in a known manner and supplied to the dividers 20 and 22, respectively. The output of the divider 20 is coupled to a first input terminal of an adder 23. The output of the adder 24, is coupled to a delay unit 26, and the output of the delay unit 26, is coupled to a second terminal of input of the adder 24 and a first input terminal of an adder 28. The signal of the divider 20 is added to the adder 24 with a delayed version of that delay signal 26. The output terminal of the divider 22 is coupled to a second input terminal of the adder 28. The signal of the delay unit 26, and is added in the adder 28 with the output of the divider 22. The output of the adder 28, is inverted with unity gain by the unit of the inverter 30. first and second divisors, 20 and 22, the add-ons 24 and 28, the delay unit 26 and the inverter unit 30, in combination, form a second closed circuit source of the second order. The output of the inverter unit 30 forms the output of the closed-loop filter. This output represents the difference between the interpolated time when the sample from the interpolator 12 is produced, and the ideal test time is synchronized with the transmitter clock. A nominal delay register 31 receives a microprocessor value from the system 268 of FIG. 1, representing a nominal or expected time delay between the test times synchronized by the transmitter. This nominal delay value is calculated by the system microprocessor in a manner that will be described in more detail below. In the illustrated embodiment, the received signal is tested at double the symbol rate, so that the nominal delay between the test signals is one half of the expected interval between transmitted symbols. The output of the nominal delay register 31 is coupled to a first input terminal of an adder 32. The output of the closed-circuit source is summed with the predetermined nominal delay value in the adder 32. The output signal of the adder 32, is a digital signal that represents the value of instantaneous delay between samples as they are synchronized with the signal symbol of the transmitter. The nominal delay register 31 is provided to allow the closed circuit of the receiver to initially approximate closely to the input symbol rate in order to accelerate the acquisition. The adjustment to synchronism of the system is limited only by the characteristics of the phase error detector 16.

The value of the adder 32 signal is expressed in terms of a number of fixed frequency clock periods and contains a portion of integers representing the number of clock pulses of fixed full frequency between test times and a portion fractional, which represents the test time between two adjacent fixed-frequency samples. In the illustrated embodiment, the digital signal of the adder 32 is a 22-character fixed-point digital signal with the two most important characters carrying the portion of integers and the remaining characters bearing the fractional portion. The microprocessor of the system (of Fig. 1) inserts a value in the nominal delay register 31 in the following manner. First, the nominal delay register 31 has a signal valued as "1" logical, inserted therein. Then the signal changes 20 places to the left. This places a logical "1" signal, in the least important character of the whole number portion. This can be expressed by the digital logic expression: 1 < < RS-IS (1) where RS is the nominal delay record size, v.gr. 22 characters in the illustrated mode and IS is the size of the portion of integers, eg, 2 characters in the present modality. In the illustrated mode, this expression is converted to: 1 < < (22-2) (2) Then, a calculation is made by the microprocessor of the system to determine the nominai reiraso between the synchronized samples of the transmitter expressed as a number of fixed frequency clock periods: D = FR / (2-S ) (3) where D is the nominal delay between the synchronized symbols of the transmitter expressed as a number of fixed frequency periods, FR is the fixed frequency clock frequency, and S is the frequency of the transmitter symbol. The result of this calculation is combined with the previous content of the nominal delay record 31. In order to compensate for the value '1' already inserted in the nominal delay record 31 by the results of expressions (1) and / or (2), the value 1 must be subtracted from the nominal delay value D calculated in equation (3). Therefore, the expression describing the nominal delay value placed in the nominal delay register 31 by the system microprocessor (of FIG. 1) is: DR31 = (1 <<(22-2)) * (FR / (2 «S) -1 (4) where DR31 is the value stored in the nominal delay register 31 by the system microprocessor.The output signal of the adder 32, is applied to an input of a multiplexer 34. The other input of the multiplexer receives a value representing a value of -1, an adder 36 receives a first input from the output of the multiplexer 34. The output of the adder 36 is coupled to a delay unit 38 which operates As an accumulator, the accumulator 38 is clocked by the AD of clock signals of fixed frequency samples, the same clock signal that drives the CAD 10. The output of the delay unit 38 is a digital signal MU representing a time delay to the next synchronized sample of the transmitter.The digital signal MU contains a p integer array representing the number of periods of fixed frequency clock signals AD, up to the next synchronized sample of the transmitter, and a fractional portion representing the time delay of the last fixed frequency clock signal up to the time for the synchronized sample of the transmitter. In the illustrated mode, the digital signal MU is a 22-character fixed-point digital signal with the two most important characters carrying the portion of integers and the remaining characters carrying the fractional portion. A person skilled in the art of digital arithmetic circuitry will understand that different sizes and formats can be used. For example, in a QAM receiver, a 26-character digital signal is used to represent the time delay. The time-delay signal MU is supplied to an integer portion selector 40. which selects the two most important characters of the MU signal (MU: 0-1). The portion of integers is supplied to a comparison circuit 41, which compares the whole number to a signal valued at zero and generates a signal when the portion of integers is equal to zero. The MU time delay signal is also supplied to a fractional portion selector! 48 which generates a signal containing the eight most important characters of the fractional portion of the MU signal (MU: 2-9), that is, the most important character of the fractional portion of the time delay signal MU. This most important character of the fractional portion is coupled to an input terminal of control of the interpolator 12. The time delay signal of 22 complete MU characters is coupled to a second input terminal of the adder 36. The output of the comparator 41 , is applied to a control input of the multiplexer 34 and a delay element 42. The delay element 42, provides a delay necessary to equalize the delay between the time delay signal MU and the corresponding output of the phase detector 16 generated in response to the MU time delay signal (discussed in more detail below). The output of the time delay element 42 is the signal that enables the sample clock and is supplied to an input terminal of a 2-module counter 44, and to a first input terminal of a 46 AND gate. A output terminal of the 2-module counter 44 is coupled to a second input terminal of the gate 46 AND. The output of gate 46 AND, produces a signal that enables the symbol relay. The 2-module meter 44 includes, for example, a sudden change of type D and in this example it is divided by 2. This operation is used in this application where two samples are provided per symbol. In other applications, such as where four samples are used per symbol, the counter 44 could be a 4 module counter, and provide a division function between 4. In operation, the frequency of the fixed frequency sample clock AD, is slightly higher than twice the expected upper frequency of the transmitter symbols. The system microprocessor 268 (of Figure 1) calculates the nominal or expected sample time for the symbol rate of the signal currently being received, and loads the nominal delay record 31 with this value. This initiates the operation of the numerically controlled delay (RCN) approximately in the correct sample period. The phase error detector 16 and associated closed-loop filter cooperates to adjust and set the RCN to the current sample rate of the transmitted signal. The signal that enables the sample clock of the delay element 42, and the signal that enables the symbolization of gate 46 AND, are used by other processing elements in the receiver (illustrated in Figure 1). For example, the pulse configuration filter 14 (of Figure 2) receives both the fixed frequency sample AD and the clock signal that enables samples. As described above, the adder 32 produces a digital signal representing the instantaneous time delay of the last synchronized sample of the transmitter, until the next synchronized sample of the transmitter and the accumulator 38 of RNC, produces a digital signal representing the remaining time until the next synchronized time of samples of the transmitter In the illustrated mode, these representative time signals are represented by a binary word of 22 fixed-point characters with the two most significant characters carrying the portion of integers, and the remaining characters carrying the fractional portion. The value of the time represented by these signals is expressed in terms of the clock periods of fixed frequency samples AD. Said representative time signal has a scale from 0 to 4 - 2"20. For example, a value" 1"represents a period of the fixed frequency sample clock AD, and has the value 010000000000000000002, in which the suffix 2 denotes that the value is represented in the base 2 format, or binary. If the integer portion of the time delay stored in the accumulator 38 is greater than zero, the output of the comparator 41 is a logical '0' signal. In this condition, more than one fixed-frequency sample clock cycle AD must elapse before the next synchronized sample from the transmitter is taken. The portion of integers of the value of the accumulator 38 is counted downwards. The multiplexer 34 is conditioned by the logical '0' signal in the comparator 41, to couple the signal of value -1 to the adder 36. The adder 36, in turn, adds the signal -1 (i.e., subtracts one del) to the value of the signal in the accumulator 38, and stores the newly reduced value in the accumulator 38. In addition, because the output of the comparator 41 is a logical 0 'signal, nor the signal that enables the sample clock , they are not active nor the signal that enables the reioj of symbols (both delayed properly by the unit of delay 42). The fractional part of the accumulator value 38, represents the fraction of a fixed frequency sample clock cycle AD until the next synchronized sample of the transmitter is taken. The eight most important characters of the fractional part are used to control the delay of the interpolator 12. This essentially divides the time between the fixed frequency sample clock cycles AD into 256 parts. Therefore, the interpolator can be a 256-phase polyphase filter bank. When there are no more complete clock cycles of fixed frequency sample AD, remaining until the next synchronized sample of the transmitter is taken, the integer portion of the signal in accumulator 38 is 0. In this case. the output signal of comparator 41, is a logic '1' signal. When the output signal of comparator 41 is a signal of Logical '1', a sample of the interpolator 12 is taken at the time controlled by the most important character of the fractional part of the value of the accumulator 38, and a signal is generated that enables the sample clock, to enable the downstream circuitry to time and process this newly generated sample. In addition, the counter 44 of two modules is clocked, and if it is a symbol time of the transmitter, the AND gate 46 also produces a signal that enables the symbol clock. At the same time, the multiplexer 34 is conditioned to pass the signal of the adder 32 to the adder 36. The adder 36 combines the desired synchronized test time of the transmitter and the fractional part of the accumulator 38 of RNC (the number portion). integer is zero, as described above) so that when the next synchronized sample of the transmitter is going to be taken, the time is placed in the accumulator 38. The circuit is closed by the RNC value that changes in response to the signal from the transmitter. output of the phase error detector 16 via the closed-loop filter. The signal that enables the sample clock is supplied to system elements such as units 14, 16, 26, 44 and 46, and the other downstream processing units (of Figure 1) that process each synchronized sample of the transmitter . Said units require the signal that enables the sample in addition to the clock signal of fixed frequency samples AD. The symbol clock allows the signal to be activated for the synchronized samples of the transmitter taken at times of transmitted symbols. The signal enabling the symbol clock is provided to those elements of the system operating on transmitted symbols, for example, the decision-driven elements associated with the carrier recovery network such as the carrier recovery unit 264 (of the Figure). 1). These elements operate in response to both the fixed-frequency sample clock signal AD and the signal that enables the symbol clock. For example, if the illustrated mode is adapted for use in a satellite broadcast system (eg, Satlink), the frequency of the fixed-frequency sample clock signal AD is made at 62 MHz. of an illustrative broadcast signal is 30 M symbols / sec. Because the received signal is tested at twice the symbol rate, the signal that enables the sample clock disables the AD frequency clock signal in such a way that it brings the average sample rate to the desired sample rate of 2. samples by symbols. Therefore, for 30 M symbols / sec, it will be 60 M Samples / sec., And 2 million clock cycles of fixed frequency samples AD disabled per second. Interpolator 12 produces interpolated samples so that in each clock cycle of fixed frequency samples disabled, the sample appears to have been taken from a CAD 10 that was clocked at the appropriate test frequency, 50 MHz in this example. appear on the transitions of the fixed clock signal of AD frequency of 62 MHz, with occasional clock signals jumped (2 million per second). When the described system is used to process a QPSK input signal, it was observed that the character error rate degrades no more than 0.1 dB at the 4 dB signal-to-sound threshold (SNR) near where they often become ineffective ios error correction codes. The closed-loop time control fully converged within 3000 samples. The closed circuit seems to converge to 0 dB SNR, with degradation of approximately 0.5 dB. These performance characteristics indicate that the described time recovery system is also suitable for use with a vestigial sideband modulated (BLV) input signal of the type proposed for use with the Grand Alliance HDTV system. The following table summarizes the performance of the system for certain SR ratios, where the SR ratio is the ratio of the fixed-frequency sample rate (analog-to-digital conversion rate) to the symbol regime, using two samples per symbol.

In systems, such as QAM systems, which test the input signal in both the phase (I) and quadrature components, it is possible to test the input signals I and quadrature Q in less than two times the symbol regime with the present system, and to generate a digital sequence of synchronized samples of the transmitter at twice the rate of synchronized symbols of the transmitter, with the proviso that the fixed signal sample rate of the fixed frequency sample AD, is greater than a defined value by the equation: FR = S x BWE + M (5) where FR is the fixed clock rate frequency frequency AD; S is the regime of symbols; BWE is a fraction of excessive bandwidth; and M is a margin for the uniform amplitude and bandwidth of group delay of the interpolator. In systems with small excess bandwidths, this could reduce the A / D sample regimes by 10% to 30% (49.9% under ideal conditions). The digital processing system after the interpolator may need to process multiple samples per unit clock, so it may need to operate at a higher clock rate or process data using a parallel method. Figure 3 illustrates a parabolic interpolator 12 in the form of Farrow architecture pieces (of Figure 2) implemented in fixed point arithmetic for hardware design. Interpolator 12 uses a parabolic filter in the form of pieces because, in this example, it provides a low complexity interpolator with adequate performance. For higher order constellations such as 64 QAM or 256 QAM, a more complex interpolation filter may be required. The addition of a nominal delay signal to the output signal of the closed-loop filter, as shown in the adder 32 (of FIG. 2), advantageously allows the microprocessor of the system (not shown) to control the nominal delay between the The synchronized samples of the transmitter desired and the closed circuit need only maintain the regime.

Specifically, interpolator 12 of Figure 3 is a parabolic filter in the form of 4-socket pieces of the type suggested by Lars, and others, in Interpolator in Digital Modems, Part II: Implementation and Performance, IEEE Transactions on Communications. In Figure 3, an input terminal IN is coupled to the output terminal of the CAD 10 (of Figure 2). The input terminal IN receives a sample of 6 characters, carrying a scale of values from -32 to + 31, and is coupled to: a serial connection of a delay element 50, an adder 60, a delay element 51, an adder 61, a delay element 52, an adder 62, and a delay element 53; and a serial connection of a delay element 54, an inverting input terminal of an adder 63, and a delay element 57. The input terminal IN is also coupled to respective inversion input terminals of the adders 60, 61 and 65, and to a non-reversing input terminal of the adder 62. The input terminal IN is also coupled to an input terminal of a multiplier x2 68, whose output terminal is coupled to an input terminal of an adder 67 and an inverting input terminal of an adder 66. The adder 66 is coupled to an input terminal of the adder 63 and the adder 67 is coupled to an input terminal of the adder 64. The input terminal IN is also coupled to terminals respective input inputs of the adders 60, 61 and 65. and input terminal without inversion of the adder 62. The input terminal IN is also coupled to an input terminal of a multiplier x2 68, whose output terminal is coupled to an input terminal of an adder 67 and an inverting input terminal of an adder 66. The adder 66 is coupled to an input terminal of the adder 63 and the adder 67 is coupled to a terminal Admitter input 63 and the adder 67 is coupled to an input terminal of the adder 64. The input terminal IN is also coupled to respective second input terminals of the adders 66 and 67. The input terminal IN is furthermore coupled to a series connection of a delay element 92 of 6 periods and a multiplier x2 94. A control input terminal MU is coupled to the most important character octet of the fractional portion of the accumulator 38 of the controlled delay (of Figure 2). The control input terminal MU is coupled to a serial connection of a multiplier 70, a delay element 72, a multiplier 74, a limiter 76, a delay element 78, a multiplier 80, a relay element 84, and an adder 90. An output terminal of the delay element 53 is coupled to a second input terminal of multiplier 70; an output terminal of the delay element 57 is copied to a second input terminal of the multiplier 74; and an output terminal of the multiplier x2 94 is coupled to a second input terminal of the adder 90. A two-period delay element is coupled between the control input terminal MU and a second input terminal of the multiplier 80. A output terminal of the adder 90, produces the synchronized sample of the transmitter and is coupled to the OUTPUT output terminal. The OUTPUT output terminal is coupled to the pulse configuration filter 14 (of Figure 2). The interpolator 12 illustrated in Figure 3 operates in a manner described in the Lars and others article discussed above. The control signal MU represents a fractional time between the adjacent cycles of the fixed frequency sample clock AD, from which a synchronized sample of the transmitter is taken. The interpolator 12 illustrated in Figure 3 operates to interpolate between adjacent CAD samples 10 at the time represented by the MU control signal to produce an interpolated sample at the OUTPUT output terminal. In the illustrated embodiment, there is a three-period delay of AD of the fixed clock signal of the frequency of the input of the control signal MU to the interpolated sample output. This delay must be compensated for in the generation of the sample and the symbol clock enable signals produced by the numerically controlled delay (from Figure 2). The delay element 42 (of Figure 2) provides this time compensation, and in the illustrated mode is a delay element of three clock cycles. Figure 4 is a more detailed block diagram of the phase error detector 16 of Figure 2. In Figure 4. the input terminals i IN and Q IN input signals in phase (i) and quadrature (Q ) produced in quadrature phases mutually, are stored to corresponding output terminals of the interpolator 12 (of Figure 2). The phase-in terminal I IN is coupled to a series connection of a delay element 102, a delay element 103 and an inverting input terminal of an adder 108. The input terminal I IN in phase, also it is coupled to a second input terminal of the adder 108. An output terminal of the adder 108 is coupled to a first input terminal of a multiplier 110, and an output terminal of the delay element 102 is coupled to a second one. input terminal of a multiplier 110. An output terminal of the multiplier 110, is coupled to a first input terminal of an adder 114. The quadrature input terminal Q IN is coupled to a series connection of a delay element 104. , a delay element 105 and an inversion input terminal of an adder 106. The quadrature input terminal Q IN is also coupled to a second input terminal of the adder 106. An output terminal of the adder 106, is coupled to a first input terminal of a multiplier 112, and an output terminal of the delay element 104 is coupled to a second input terminal of the multiplier 112. An output terminal of the multiplier 112, is coupled to a second terminal of input of the adder 114. An output terminal of the adder 114, produces a signal representing the phase error between the synchronized test signal of the transmitter, generated by the numerically controlled delay element in the receiver, and the test time reai of the transmitted signal, all in a known way.

The time recovery system described herein is advantageously capable of processing a multi-symbol rate input signal in association with a single clock produced by a fixed frequency oscillator. In addition, both the signals that enable the sample clock and those that enable the symbol clock are derived from the input signal by itself. As explained elsewhere in the text, the signal that enables the sample clock indicates an interpolator output of samples at a rate that is a multiple of the symbol regime. The described system advantageously supports multiple sample rates with a fixed pulse configuration filter 14, and a fixed frequency clock oscillator 261. The configuration of the filter 14 need not be adapted to accommodate the multiple tap symbol regimes. The tap configuration filter 14, located after the time recovery network, filters the signal with the same pulse configuration feature, thus increasing its signal to sound performance. The symbol time recovery system, according to the present invention, is applicable to BPSK, QPSK, CAP and QAM, for example, as well as to the VSB modulation systems such as those employed by the Grand Aliance High system. Definition Television (HDTV) proposed for use in the United States. Someone with experience in the field will recognize which design changes are needed to adapt to the desired modulation, the symbol time recovery system described, and will understand how to design the illustrated components to operate with the desired modulation. It has been observed that the system illustrated above acquires fixation in a relatively short time. A constellation of QPSK symbols has been observed, fixed after a few thousand samples, and the constellation is visible after 500 samples even with a time deviation of 1000 ppm. These performance attributes, coupled with the reduced hardware requirements because it digitally performs the controlled voltage oscillator function, makes the system attractive for use even when the system is intended to operate with respect to a single symbol regime. In the described embodiment, the signal that enables the sample clock, enables and disables the clock signal AD via clock enable / disable terminals in the respective units, instead of enabling and disabling the fixed frequency oscillator 261 by itself . One option is also to place doors on the clock and can be considered in accordance with the requirements of a particular system.

Claims (12)

1. CLAIMS 1. A time recovery network in a digital signal processing • system for receiving a signal representing successive symbols, characterized by: a source of samples (10) representing the received signal; an interpolator (12), coupled to the sample source and responding to a control signal, to produce samples taken at times synchronized with the successive symbols of the transmitter, and a control network (16, 20-30, 34-36) ) to provide said control signal, said control network including a controlled delay network that responds to (a) an output signal from said interpolator and to (b) a nominal delay deviation signal (31).
2. 2. A time recovery network according to claim 1, characterized in that said control network comprises: a phase error detector, coupled to the interpolator, to detect a phase error between the sample times of the synchronized samples of the transmitter produced by the interpolator and times of the successive symbols of the transmitter; a source of a nominal delay signal; an adder to the phase detector and the nominal delay signal source; and a numerically controlled delay, coupled to the adder, to produce the control signal for the interpolator.
3. 3. A system according to claim 1, characterized in that: said samples are taken at a fixed frequency.
4. The system of claim 2, characterized in that the numerically controlled delay comprises: an accumulator for maintaining a signal representing the time remaining before the interpolator takes the next synchronized sample from the transmitter; circuitry, stored in the accumulator, to generate a signal that enables the synchronized sample clock of the transmitter, when a synchronized sample of the transmitter is going to be taken; and circuitry, coupled to the accumulator, to generate the control signal of the interpolator.
5. The system of claim 4, further characterized by a source of a clock signal having the fixed frequency, wherein: the accumulator comprises circuitry for maintaining a number of fixed points having a portion of integers and a fractional portion wherein the value of the number is expressed in terms of the period of the fixed frequency clock signal; the circuitry for generating a synchronized signal that enables the transmitter's sample clock, which comprises circuitry, responds to the fixed clock frequency signal, to count down the portion of integer numbers in the accumulator until it reaches zero; and the circuitry for generating an interpolator control signal, responds to the fractional portion of the number in the accumulator.
6. The system of claim 2, characterized in that the interpolator comprises a parabolic filter in the form of four-socket pieces.
7. The system of claim 2, characterized in that: the received signal represents symbols produced in one of a plurality of symbol regimes; the nominal delay signal source generates the nominal delay signal having a delay value corresponding to the nominal delay of time between successive symbols in the received signal.
8. The system of claim 7, characterized in that the fixed frequency is greater than two times the synchronized upper expected rate of transmitter samples.
9. The system of claim 3, characterized in that the fixed frequency is greater than twice the synchronized sample rate of the transmitter.
10. The system of claim 9, characterized in that the fixed frequency is 62 MHz and the synchronized symbol rate of the transmitter is 30 M symbols / sec.
11. The system of claim 9, characterized in that the fixed frequency is 62 MHz and the synchronized symbol rate of the transmitter is 20 M symbols / sec.
12. 12. The system of claim 2, further characterized by a closed circuit filter coupled between the phase error detector and the adder.