KR100772848B1 - Ｍｏｓ 디바이스의 전류를 시뮬레이션하기 위한 레이트 방정식 방법 및 장치 - Google Patents

Ｍｏｓ 디바이스의 전류를 시뮬레이션하기 위한 레이트 방정식 방법 및 장치 Download PDF

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KR100772848B1
KR100772848B1 KR1020000065162A KR20000065162A KR100772848B1 KR 100772848 B1 KR100772848 B1 KR 100772848B1 KR 1020000065162 A KR1020000065162 A KR 1020000065162A KR 20000065162 A KR20000065162 A KR 20000065162A KR 100772848 B1 KR100772848 B1 KR 100772848B1
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channel
voltage
current
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KR20010060250A (ko
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마티아존폴
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루센트 테크놀러지스 인크
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020000065162A 1999-11-03 2000-11-03 Ｍｏｓ 디바이스의 전류를 시뮬레이션하기 위한 레이트 방정식 방법 및 장치 Expired - Fee Related KR100772848B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/433,702 1999-11-03
US09/433,702 US6493848B1 (en) 1999-11-03 1999-11-03 Rate equation method and apparatus for simulation of current in a MOS device

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KR20010060250A KR20010060250A (ko) 2001-07-06
KR100772848B1 true KR100772848B1 (ko) 2007-11-02

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US (1) US6493848B1 (enExample)
EP (1) EP1098259B1 (enExample)
JP (1) JP4988981B2 (enExample)
KR (1) KR100772848B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234420A (ja) * 2002-02-06 2003-08-22 Mitsubishi Electric Corp シミュレーション方法
US7100131B2 (en) * 2002-11-07 2006-08-29 Semiconductor Energy/Laboratory Co., Ltd. Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medium recording the program, and dose amount control apparatus
CN101726274B (zh) * 2009-12-01 2011-04-27 中国科学院上海微系统与信息技术研究所 利用mosfet输入输出特性确定mosfet bsim模型参数宽度偏移量的方法
CN105893325A (zh) * 2016-06-03 2016-08-24 江西理工大学 一种金属矿山人工矿柱稳定性判别方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404109A (en) * 1991-09-20 1995-04-04 Itt Corporation Method and apparatus for testing circuits containing active devices
US5687355A (en) * 1995-08-21 1997-11-11 Motorola, Inc. Apparatus and method for modeling a graded channel transistor
KR20000017553A (ko) * 1998-08-26 2000-03-25 루센트 테크놀러지스 인크 집적 회로에서 이중 폴리실리콘 구조 및 이를 제조하는 방법
KR20000048093A (ko) * 1998-12-11 2000-07-25 루센트 테크놀러지스 인크 실리콘 게이트 전계 효과 트랜지스터 장치 제조 방법
US6275059B1 (en) * 1997-04-04 2001-08-14 University Of Florida Method for testing and diagnosing MOS transistors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59409758D1 (de) * 1993-10-01 2001-06-28 Infineon Technologies Ag Simulationsverfahren für MOS-Schaltkreise
JPH09191039A (ja) * 1996-01-09 1997-07-22 Sony Corp 半導体シミュレーション方法および半導体シミュレーション装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404109A (en) * 1991-09-20 1995-04-04 Itt Corporation Method and apparatus for testing circuits containing active devices
US5687355A (en) * 1995-08-21 1997-11-11 Motorola, Inc. Apparatus and method for modeling a graded channel transistor
US6275059B1 (en) * 1997-04-04 2001-08-14 University Of Florida Method for testing and diagnosing MOS transistors
KR20000017553A (ko) * 1998-08-26 2000-03-25 루센트 테크놀러지스 인크 집적 회로에서 이중 폴리실리콘 구조 및 이를 제조하는 방법
KR20000048093A (ko) * 1998-12-11 2000-07-25 루센트 테크놀러지스 인크 실리콘 게이트 전계 효과 트랜지스터 장치 제조 방법

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Publication number Publication date
JP4988981B2 (ja) 2012-08-01
EP1098259A2 (en) 2001-05-09
JP2001168331A (ja) 2001-06-22
KR20010060250A (ko) 2001-07-06
EP1098259B1 (en) 2014-09-24
EP1098259A3 (en) 2004-12-08
US6493848B1 (en) 2002-12-10

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