JP4988981B2 - Ｍｏｓ素子の電流をシミュレートするためにレート方程式を用いる方法及び装置 - Google Patents

Ｍｏｓ素子の電流をシミュレートするためにレート方程式を用いる方法及び装置 Download PDF

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JP4988981B2
JP4988981B2 JP2000335373A JP2000335373A JP4988981B2 JP 4988981 B2 JP4988981 B2 JP 4988981B2 JP 2000335373 A JP2000335373 A JP 2000335373A JP 2000335373 A JP2000335373 A JP 2000335373A JP 4988981 B2 JP4988981 B2 JP 4988981B2
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current
voltage
source
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JP2001168331A (ja
JP2001168331A5 (enExample
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ポール マッティア ジョン
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アルカテル−ルーセント ユーエスエー インコーポレーテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2000335373A 1999-11-03 2000-11-02 Ｍｏｓ素子の電流をシミュレートするためにレート方程式を用いる方法及び装置 Expired - Fee Related JP4988981B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/433,702 US6493848B1 (en) 1999-11-03 1999-11-03 Rate equation method and apparatus for simulation of current in a MOS device
US09/433702 1999-11-03

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JP2001168331A JP2001168331A (ja) 2001-06-22
JP2001168331A5 JP2001168331A5 (enExample) 2007-11-29
JP4988981B2 true JP4988981B2 (ja) 2012-08-01

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JP2000335373A Expired - Fee Related JP4988981B2 (ja) 1999-11-03 2000-11-02 Ｍｏｓ素子の電流をシミュレートするためにレート方程式を用いる方法及び装置

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US (1) US6493848B1 (enExample)
EP (1) EP1098259B1 (enExample)
JP (1) JP4988981B2 (enExample)
KR (1) KR100772848B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234420A (ja) * 2002-02-06 2003-08-22 Mitsubishi Electric Corp シミュレーション方法
US7100131B2 (en) * 2002-11-07 2006-08-29 Semiconductor Energy/Laboratory Co., Ltd. Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medium recording the program, and dose amount control apparatus
CN101726274B (zh) * 2009-12-01 2011-04-27 中国科学院上海微系统与信息技术研究所 利用mosfet输入输出特性确定mosfet bsim模型参数宽度偏移量的方法
CN105893325A (zh) * 2016-06-03 2016-08-24 江西理工大学 一种金属矿山人工矿柱稳定性判别方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404109A (en) * 1991-09-20 1995-04-04 Itt Corporation Method and apparatus for testing circuits containing active devices
DE59409758D1 (de) * 1993-10-01 2001-06-28 Infineon Technologies Ag Simulationsverfahren für MOS-Schaltkreise
US5687355A (en) * 1995-08-21 1997-11-11 Motorola, Inc. Apparatus and method for modeling a graded channel transistor
JPH09191039A (ja) * 1996-01-09 1997-07-22 Sony Corp 半導体シミュレーション方法および半導体シミュレーション装置
WO1998045719A1 (en) * 1997-04-04 1998-10-15 University Of Florida Method for testing and diagnosing mos transistors
JP2000124326A (ja) * 1998-08-26 2000-04-28 Lucent Technol Inc 集積回路の形成方法
US6339246B1 (en) * 1998-12-11 2002-01-15 Isik C. Kizilyalli Tungsten silicide nitride as an electrode for tantalum pentoxide devices

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Publication number Publication date
KR100772848B1 (ko) 2007-11-02
EP1098259A3 (en) 2004-12-08
US6493848B1 (en) 2002-12-10
JP2001168331A (ja) 2001-06-22
KR20010060250A (ko) 2001-07-06
EP1098259A2 (en) 2001-05-09
EP1098259B1 (en) 2014-09-24

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