KR100723466B1 - Photomask for dual damascene process, method thereof and method of forming dual damascene interconnection using the photomask - Google Patents

Abstract

A photomask for a dual damascene process, a manufacturing method thereof, and a method for forming a dual damascene wiring using the photomask are disclosed. The photomask is formed in a wiring region and a wiring region having a plurality of etching patterns having a line shape in the region defined by the opaque layer pattern formed on the transparent substrate and having a phase difference of 170 ° to 190 ° with the surface of the substrate. And a contact region having a phase difference of 0 ° from the surface of the substrate. The photomask manufacturing method includes the steps of forming an opaque layer pattern on a transparent substrate, etching the opaque layer using the opaque layer pattern as an etch mask, and etching formed on the entire surface of the substrate and the opaque layer. Forming a wiring region pattern having a phase difference between the surface of the substrate and a plurality of line shapes having a phase difference of 170 to 190 degrees on the mask layer, and etching the substrate using the wiring region pattern as an etch mask; It is used for formation method. By forming a wiring area formed of a plurality of etching patterns having a line shape and a phase difference between the surface of the substrate and the surface of the substrate from 170 ° to 190 °, a uniform exposure intensity distribution can be ensured in the wiring area and the influence of HTPS can be eliminated.

Photomask, dual damascene, half tone phase shift (HTPS), phase difference, exposure intensity

Description

Photomask for dual damascene process, method approximately and method of forming dual damascene interconnection using the photomask

1 to 3 are plan views, cross-sectional views and diagrams for explaining a conventional photomask for the dual damascene process.

4 to 6 are plan views, cross-sectional views and diagrams for explaining the photomask for the dual damascene process according to the present invention.

7A to 7E are cross-sectional views illustrating a method of manufacturing a photomask for a dual damascene process according to the present invention.

8A to 8E are cross-sectional views illustrating a method of forming dual damascene wiring using a photomask according to the present invention.

* Explanation of symbols for main parts of the drawings

100; Substrate 102; Wiring area

104; Contact area 106; Opaque layer pattern

108; HTPS site 202; HTPS Correction Site

302; Opaque layer 304; 1st etching mask layer

306; First pattern 308; 2nd etching mask layer                 

310; Second pattern 402; Conductive layer

404; Insulating film 406; Etch Mask Layer

408; Conductive material layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a photomask for a semiconductor device and a method for forming a dual damascene wiring using the photomask.

In the process of manufacturing a semiconductor device, a contact hole is formed in a wiring region formed in an insulating film, and then a metal layer is deposited, and the metal wiring is formed through a chemical mechanical polishing (CMP) process. Drinking process is introduced. The advantage of this process is to simplify the process by forming contact and metallization at the same time, and to improve the margin in the subsequent photographic process since no local step is generated after the process is completed.

Referring to the current dual damascene process, an insulating film is deposited on a substrate, and then a wiring region is formed on the insulating film by exposure-> developing-> anisotropic etching using a photomask for forming a wiring region. Subsequently, a contact hole is formed in the wiring area using the contact hole forming photomask. Next, a conductive material such as copper is deposited on the wiring region and the entire surface of the substrate and planarized using a CMP process.                         

By the way, such a wiring forming method is subjected to an exposure-> etching process with a separate photomask for forming the wiring region and the contact hole, which is not only complicated by the process but also due to the alignment error between the wiring region and the contact hole. This can reduce the overlap margin.

Therefore, in order to solve this problem, the wiring area and the contact hole are manufactured as a single photomask, but the light transmittance of the part corresponding to the wiring area and the part corresponding to the contact hole on the photomask is different from each other. For example, if the light transmittance of the portion corresponding to the contact hole is 100%, the light transmittance of the portion corresponding to the wiring area is adjusted to be an appropriate value (for example, 50%) between 100% and 0%. In the remaining part, a photomask is manufactured so that light transmittance is 0%. This is because, when the positive photoresist undergoes application-> exposure-> development, the thickness of the photoresist remaining after development is proportional to the intensity of the irradiated light.

As a result, all the photoresist of the portion corresponding to 100% transmittance is removed, and the photoresist of the portion corresponding to the light transmittance of 0 to 100% remains by a certain thickness, and the photoresist of the portion having 0% light transmittance Is almost intact and preserved. When anisotropic etching is performed on the insulating film after the development is completed, the amount of etching is inversely proportional to the thickness of the photoresist. In other words, the insulating film without the photoresist is etched from the initial etching to the substrate, but the insulating film having a part of the photoresist is etched only to a certain depth since all remaining photoresist is etched and then etched. The portion where the photoresist is not damaged is not etched. After etching, portions of the photoresist remaining form wiring regions, and portions of the photoresist removed all form contact holes. Subsequently, when the metal material is embedded and planarized by the CMP process, the metal wiring and contacts as in the conventional dual damascene process are obtained.

Hereinafter, a conventional photomask for a dual damascene process will be described with reference to the accompanying drawings.

1 to 3 are plan views, cross-sectional views and diagrams for explaining a conventional photomask for the dual damascene process.

1 is a plan view illustrating a conventional photomask for a dual damascene process.

Referring to FIG. 1, the wiring region 102 defined by the opaque layer pattern 106 on the substrate 100 is formed by a phase inversion layer having a light transmittance greater than 0% and less than 100%. In 102, a contact region 104 having a light transmittance of 100% is formed. Corresponding to the dual damascene process, the contact region 104 having a light transmittance of 100% forms a contact hole, and the phase inversion layer having a light transmittance of greater than 0% and less than 100% has a wiring region 102 and a light transmittance. At this 0% portion, an insulating film is formed. In this way, the photomask for the dual damascene process can be formed on one photomask.

2 is a cross-sectional view illustrating a conventional photomask for a dual damascene process.

Referring to FIG. 2, the contact region 104 is formed surrounded by a region composed of a phase inversion layer in the region defined by the opaque layer pattern 106. Here, the phase inversion layer is formed by applying a material causing the phase difference with the substrate or by adjusting the thickness of the layer. Here, the phase inversion layer may be amorphous carbon, MoSiON, SiN, or spin on glass (SOG).

FIG. 3 is a diagram showing the intensity of light exposed using a photomask formed as shown in FIGS. 1 and 2.

3, light having a light transmittance of 100% and phase inverted light having a light transmittance of between 0% and 100% cause mutual interference at the edge of the wiring region 102. Due to this effect, the HTPS region 108 is generated at the edge of the wiring region 102 due to an inversion effect called half-tone phase shift (HTPS). However, when exposure is performed using the photomask shown in FIG. 1 to etch the wiring region 102 of the portion corresponding to the HTPS region 108, the exposure intensity is significantly reduced. In this case, since it is difficult to ensure uniform exposure intensity in the HTPS region 108 in the wiring region 102, the photoresist remaining after development becomes larger than an appropriate amount. In severe cases, a poor contact between the metal wiring and the contact formed after the CMP process may occur.

Accordingly, the technical problem to be achieved by the present invention is to provide a photomask for a dual damascene process comprising a photomask that ensures a uniform exposure intensity distribution in a portion forming a wiring region and excludes the influence of HTPS.

In addition, another technical problem to be achieved by the present invention is to provide a method of manufacturing a photomask for the dual damascene process comprising a photomask to ensure a uniform exposure intensity distribution in the site forming the wiring area and to exclude the influence of HTPS. will be,                         

In addition, another technical problem to be achieved by the present invention is to use a dual damascene process photomask consisting of a photomask to ensure a uniform exposure intensity distribution in the site forming the wiring area and to exclude the influence of HTPS. To provide a method for forming a drank wiring,

Dual damascene process photomask according to the present invention for achieving the above technical problem is a line in the region defined by a transparent substrate, an opaque layer pattern formed on the transparent substrate, and the opaque layer pattern A wiring area having a plurality of etching patterns having a phase difference of 170 ° to 190 ° from a surface of the substrate and a contact area formed in the wiring area and having a phase difference of 0 ° from the surface of the substrate.

Here, it is preferable that the etching pattern has a phase difference of 180 ° from the surface of the substrate, and the contact region is present inside a plurality of etching patterns having the phase difference of 170 ° to 190 °.

Further, the opaque layer pattern may be formed in contact with an etching pattern having a phase difference of 170 ° to 190 ° in the wiring area, or the opaque layer pattern may be in contact with an area where the phase difference is 0 ° in the wiring area. Do.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a photomask for a dual damascene process, including providing a transparent substrate, depositing an opaque layer on the transparent substrate, and a front surface of the opaque layer. Applying a first etch mask layer, forming a first pattern defining a wiring region in the first etch mask layer, etching the opaque layer using the first pattern as an etch mask, Removing the first etch mask layer, applying a second etch mask layer on the entire surface of the substrate and the opaque layer, and forming a second pattern having a plurality of line shapes on the second etch mask layer. And etching the substrate using the second pattern as an etch mask, and removing the second etch mask layer.

Here, it is preferable that the depth at which the substrate is etched is 1200 kPa to 2000 kPa.

In addition, the dual damascene wiring forming method according to the present invention for achieving the above technical problem, the step of forming an insulating film on the substrate, the step of applying an etching mask layer on the insulating film, the etching mask layer Forming a pattern using a photomask manufactured by a photomask manufacturing method for a dual damascene process, etching the insulating layer using the substrate as an end point using the pattern as an etch mask, and etching the layer And forming a wiring by embedding a conductive material in front of the etched and unetched portions of the insulating layer.

The etching mask may be a positive photoresist, and the insulating layer may be formed of a first insulating layer and a second insulating layer, and an etch stop layer may be formed between the first insulating layer and the second insulating layer.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions have been emphasized for clarity, and when a layer is described as "on" another layer or substrate, the layer may exist in direct contact with another layer or substrate, or There may be a third layer in the.

4 to 6 are a plan view, a cross-sectional view and a diagram for explaining a photomask for a dual damascene process according to an embodiment of the present invention.

4 is a plan view illustrating a photomask for a dual damascene process according to a first embodiment of the present invention.

Referring to FIG. 4, the wiring area 102 defined by the opaque layer pattern 106 on the substrate 100 has a plurality of etching patterns having a line shape and a phase difference between the surface of the substrate and 170 ° to 190 °. Meanwhile, in order to form a contact hole, the contact region 104 having a light transmittance of 100% is preferably formed inside a plurality of etching patterns having a phase difference of 170 ° to 190 °. However, the contact region 104 does not necessarily need to be formed inside the plurality of etching patterns having a phase difference of 170 ° to 190 ° from the surface of the substrate, and in some cases, the contact area 104 may be formed outside the etching pattern in the wiring area 102. It may be formed in. According to the dual damascene process, the contact region 104 having a light transmittance of 100% is a region where a contact hole is formed, and is a line shape and has a plurality of etching patterns having a phase difference of 170 ° to 190 ° with a surface of the substrate. The silver wiring region 102 and the opaque layer pattern 106 having a light transmittance of 0% form an insulating film. Here, the opaque layer pattern 106 may be formed in the wiring region 102 while contacting an etching pattern having a phase difference of 170 ° to 190 ° with the surface of the substrate, or contacting an area having a phase difference of 0 ° with the surface of the substrate. It may be formed while.

5 is a cross-sectional view illustrating a photomask for a dual damascene process according to an embodiment of the present invention.

Referring to FIG. 5, a wiring region 102 defined by an opaque layer pattern 106 on a substrate 100 is formed. The wiring area 102 is formed of a plurality of etching patterns having a line shape and having a phase difference of 170 ° to 190 ° with the surface of the substrate. In addition, the region having a phase difference of 170 ° to 190 ° from the surface of the substrate is formed by etching the substrate 100 to a predetermined depth. In this case, the material forming the opaque layer pattern 106 may be a nickel layer, a chromium layer, a molybdenum layer, or an alloy layer thereof. In some cases, it may be an oxide layer of nickel, chromium or molybdenum.

FIG. 6 is a diagram illustrating the intensity of light exposed using a photomask formed as shown in FIGS. 4 and 5.

Referring to FIG. 6, at the edge of the wiring region 102, there is little interference between light having a light transmittance of 100% and light exposed in the wiring region 102. This phenomenon can be confirmed by the disappearance of the HTPS phenomenon as shown in the diagram. Accordingly, the HTPS correction portion 202 is formed at the edge of the wiring region 102 with the exposure intensity corrected as compared with the conventional case. In this case, since the uniform exposure intensity is secured in the wiring region 102, an appropriate amount of photoresist remains after the development in the wiring region 102, thereby forming a wiring region having a uniform thickness.

7A to 7E are cross-sectional views illustrating a method of manufacturing a photomask for a dual damascene process according to an exemplary embodiment of the present invention.

Referring to FIG. 7A, an opaque layer 302 and a first etching mask layer 304 are sequentially formed on the substrate 100. Here, the opaque layer 302 typically uses chromium.

Referring to FIG. 7B, a first pattern 306 defining the wiring region 102 is formed in the first etching mask layer 304.

Referring to FIG. 7C, the opaque layer 302 is etched using the first etch mask layer 304 as an etch mask. As a result, the wiring region 102 is formed by removing the opaque layer 302 and exposing the substrate 100.

Referring to FIG. 7D, a second etching mask layer 308 is formed on the entire surface of the substrate 100 and the first pattern 306. Subsequently, a second pattern 310 having a plurality of line shapes is formed on the second etching mask layer 308. Next, the substrate 100 is etched using the second pattern 310 as an etch mask.

Referring to FIG. 7E, when the substrate 100 is etched, a wiring region 102 is formed in the substrate 100. However, the depth at which the substrate 100 is etched may be appropriately determined according to the wavelength of the light to be exposed. In general, it is preferable that the depth at which the substrate 100 is etched is 1200 kPa to 2000 kPa.

8A to 8E are cross-sectional views illustrating a method for forming a dual damascene wiring according to an embodiment of the present invention using the photomask manufactured by FIGS. 7A to 7E.

Referring to FIG. 8A, an insulating film 404 and an etching mask layer 406 are sequentially formed on the substrate 100 on which the conductive layer 402 is formed. The conductive layer 402 may be a source and drain region, a gate electrode, a bit line contact pad, or a word line contact pad formed on a semiconductor substrate. In addition, the insulating film 404 is preferably a silicon oxide film. In some cases, the conductive layer 402 may not be formed. In the etching mask layer 406, a positive type photoresist is preferably used. Positive photoresists change from insoluble to soluble when exposed to light, called photolysis. This photolysis is proportional to the exposure intensity, which is the intensity of the light to be exposed. That is, when the intensity of the exposed light is large, photolysis of the photoresist occurs a lot, and when the intensity of light is low, photolysis occurs less.

Referring to FIG. 8B, the etching mask layer 406 is exposed and developed using a photomask manufactured through FIGS. 7A to 7E. At this time, the contact region 104, which is a portion where the contact hole is formed, is completely removed by the photoresist, and the portion of the wiring region 102 is developed by the amount of photoresist proportional to the light transmittance. Photoresist of a certain thickness remains after development.

Referring to FIG. 8C, anisotropic etching is performed using the etching mask layer 406 as an etching mask. When etching starts, the insulating film 404 at the portion where the contact region 104 is formed is etched, and the photoresist at the portion forming the wiring region 102 is also etched to make the thickness thinner, but the insulating film 404 is etched. It doesn't. As the etching proceeds, the photoresist at the portion forming the wiring region 102 becomes thinner and eventually disappears, so that the insulating film 404 at that portion is also etched. At the same time, the insulating film 404 in the portion forming the contact region 104 is also continuously etched.                     

Referring to FIG. 8D, etching of the insulating layer 404 in the portion forming the contact region 104 proceeds until the conductive layer is exposed. While the etching for forming the wiring region 102 continues while the etching for forming the contact region 104 proceeds, when the etching is stopped, the wiring region 102 and the contact region 104 are formed in the insulating film 404. Is formed.

Referring to FIG. 8E, a conductive material layer 408, for example, a copper layer, is embedded in the entire surface of the insulating layer 404 and the exposed conductive layer 402. Subsequently, the conductive material layer 408 is removed and planarized until the insulating film 404 is exposed using a CMP process. As described above, the dual damascene wiring is formed.

Although the present invention has been described in detail above, the present invention is not limited to the above embodiments, and many modifications and improvements can be made by those skilled in the art. For example, in FIG. 8A, the insulating film 404 may be formed of the first insulating film and the second insulating film, and an etch stop film may be formed between the first insulating film and the second insulating film.

In the photomask for the dual damascene process according to the present invention, a manufacturing method thereof, and a method for forming a dual damascene wiring using the photomask, the wiring region defined by the opaque layer pattern has a line shape and a phase difference from the surface of the substrate. By forming a plurality of etching patterns having a 170 ° to 190 ° to ensure a uniform exposure intensity distribution in the wiring area region, it is possible to eliminate the influence of the HTPS. In addition, it is possible to prevent the contact between the metal wiring and the contact when the metal wiring is formed by depositing a conductive material such as metal.

Claims (10)

Transparent substrates; An opaque layer pattern formed on the transparent substrate; A wiring region in a region defined by the opaque layer pattern, the wiring region having a plurality of etching patterns having a line shape and having a phase difference of 170 ° to 190 ° with a surface of the substrate; And A contact region formed in the wiring region and having a phase difference of 0 ° from the surface of the substrate; Dual damascene process photomask comprising a. The photomask of claim 1, wherein the etching pattern has a phase difference of 180 ° from a surface of the substrate. The method of claim 1, The photomask for a dual damascene process, wherein the contact region is present in a plurality of etching patterns having a phase difference of 170 ° to 190 °. The photomask for a dual damascene process of claim 1, wherein the opaque layer pattern is formed in contact with an etching pattern having a phase difference of 170 ° to 190 ° in the wiring area. The photomask for dual damascene process according to claim 1, wherein the opaque layer pattern is in contact with a region where the phase difference is 0 degrees in the wiring region. Providing a transparent substrate; Depositing an opaque layer on the transparent substrate; Applying a first etching mask layer on the entire surface of the opaque layer; Forming a first pattern defining a wiring region in the first etching mask layer; Etching the opaque layer using the first pattern as an etching mask; Removing the first etching mask layer; Applying a second etching mask layer on the entire surface of the substrate and the light transmitting layer; A second line including a plurality of line shapes in the second etching mask layer, a wiring region having a phase difference of 170 ° to 190 ° with a surface of the substrate, and a contact region having a phase difference of 0 with a surface of the substrate therein; Forming a pattern; Etching the substrate using the second pattern as an etching mask; And Removing the second etching mask layer; Photomask manufacturing method for a dual damascene process comprising a. 7. The method of claim 6, wherein the substrate is etched at a depth of 1200 Pa to 2000 Pa. Forming an insulating film on the substrate; Applying an etch mask layer on the insulating film; A wiring region and a wiring region having a plurality of etching patterns having a line shape in a region defined by an opaque layer pattern formed on the substrate on the etching mask layer and having a phase difference of 170 ° to 190 ° from the surface of the substrate; Forming a pattern using a photomask having a contact region having a phase difference of 0 ° from a surface of the substrate; Etching the insulating layer with the substrate as an end point by using the pattern as an etch mask; Removing the etch mask layer; And Forming a wiring by filling a conductive material in front of an etched portion and an unetched portion of the insulating film; Dual damascene wiring forming method comprising a. The method of claim 8, wherein the etching mask is a positive type photoresist. The method of claim 8, And forming an insulating film between the first insulating film and the second insulating film and forming an etch stop film between the first insulating film and the second insulating film.

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