KR100701687B1 - Method for etching gate electrodes - Google Patents
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- KR100701687B1 KR100701687B1 KR1020030095547A KR20030095547A KR100701687B1 KR 100701687 B1 KR100701687 B1 KR 100701687B1 KR 1020030095547 A KR1020030095547 A KR 1020030095547A KR 20030095547 A KR20030095547 A KR 20030095547A KR 100701687 B1 KR100701687 B1 KR 100701687B1
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- 238000005530 etching Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920000642 polymer Polymers 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 238000004140 cleaning Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000011149 sulphuric acid Nutrition 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
본 발명은 게이트전극 식각방법에 관해 개시한 것으로서, 반도체기판 위에 게이트산화막 및 게이트전극용 다결정실리콘막을 차례로 형성하는 단계와, HBr 및 O2가스를 공급시켜 상기 다결정실리콘막의 일부를 식각하여 게이트전극을 형성하며 이와 동시에 상기 게이트전극의 측벽 및 상기 게이트산화막의 표면 상에 폴리머가 발생되는 단계와, 결과물에 세정공정을 진행하여 상기 폴리머만을 선택적으로 제거하는 단계를 포함한다.The present invention relates to a method of etching a gate electrode, comprising the steps of sequentially forming a gate oxide film and a polysilicon film for a gate electrode on a semiconductor substrate, and supplying HBr and O2 gas to etch a portion of the polysilicon film to form a gate electrode. And simultaneously generating a polymer on the sidewalls of the gate electrode and the surface of the gate oxide layer, and selectively removing only the polymer by performing a cleaning process on the resultant.
Description
도 1은 종래기술에 따른 웨이퍼 위치별 다결정실리콘막의 식각비와 잔류된 게이트산화막 두께를 나타낸 그래프.1 is a graph showing the etching ratio and the remaining gate oxide thickness of the polysilicon film for each wafer position according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 게이트전극 식각방법을 설명하기 위한 공정단면도.2A to 2C are cross-sectional views illustrating a gate electrode etching method according to the present invention.
도 3은 본 발명에 따른 웨이퍼 위치별 다결정실리콘막의 식각비와 잔류된 게이트산화막 두께를 나타낸 그래프.Figure 3 is a graph showing the etching ratio and the remaining gate oxide thickness of the polysilicon film for each wafer position according to the present invention.
본 발명은 반도체 소자를 제조하는 기법에 관한 것으로, 더욱 상세하게는 게이트전극용 다결정실리콘막의 식각공정에서, 폴리머(polymer)가 다량발생되어 웨이퍼 센터부위에서의 식각정지현상이 발생되며, 이로인해 게이트전극 간의 브릿지(bridge)현상 및 이후의 공정에서 게이트전극과 비트라인 간의 브릿지을 방지할 수 있는 게이트 식각방법에 관한 것이다.BACKGROUND OF THE
일반적으로, 게이트전극용 다결정실리콘막을 식각하는 경우, 다결정실리콘막이 지나치게 많이 식각되는 것을 방지하기 위해, 폴리머가 다량 발생되는 고폴리머 공정(high polymer process)으로 식각하여 식각후 게이트산화막 두께를 보상하고 있다. 이때, 상기 식각공정은 RIE(Reactive Ion Etching) 및 MERIE(Magnetically Enhanced Reactive Ion Etching) 중 어느하나의 식각장비 내에서 진행한다. 또한, 상기 식각가스로는 HBr 및 O2를 사용하며, HBr은 160∼200sccm의 유량으로, O2는 4∼5sccm 이하의 유량으로 각각 공급한다. 그리고, 상기 식각장비 내의 식각조건은 압력을 25mT이하로, 소오스파워(source power)를 100∼150W이상, 바이어스파워(bias power)를 120W이하로 한다. In general, in the case of etching the gate silicon polysilicon film, in order to prevent the polysilicon film from being etched too much, the gate oxide film thickness is compensated by etching by a high polymer process in which a large amount of polymer is generated. . In this case, the etching process is performed in one of the etching equipment of Reactive Ion Etching (RIE) and Magnetically Enhanced Reactive Ion Etching (MERIE). In addition, HBr and O2 are used as the etching gas, and HBr is supplied at a flow rate of 160 to 200 sccm, and O2 is supplied at a flow rate of 4 to 5 sccm or less. In addition, the etching conditions in the etching equipment are at a pressure of 25 mT or less, source power of 100 to 150 W or more, and bias power of 120 W or less.
한편, 상기 식각공정 결과, 식각 후 잔류된 다결정실리콘막 즉, 게이트전극의 측벽 및 게이트산화막 표면에는 다량의 폴리머가 발생된다.Meanwhile, as a result of the etching process, a large amount of polymer is generated on the polycrystalline silicon film remaining after the etching, that is, the sidewall of the gate electrode and the surface of the gate oxide film.
따라서, 이러한 폴리머를 제거하기 위해, 상기 식각공정을 진행한 다음, 상기 결과물에 별도의 세정공정을 진행한다. 이때, 세정공정에 의해, 폴리머 뿐만 아니라 게이트산화막의 소정두께가 제거된다. 상기 세정액으로는 BOE(Buffer Oxide Etchant)를 이용한다.Therefore, in order to remove such a polymer, the etching process is performed, and then a separate washing process is performed on the resultant product. At this time, the predetermined thickness of the gate oxide film as well as the polymer is removed by the washing step. As the cleaning solution, BOE (Buffer Oxide Etchant) is used.
도 1은 종래기술에 따른 웨이퍼 위치별 다결정실리콘막의 식각비와 잔류된 게이트산화막 두께를 나타낸 그래프로서, 이하에서 도 1을 참고로하여 종래기술의 문제점을 설명한다.FIG. 1 is a graph illustrating an etching ratio of a polysilicon film for each wafer position and a thickness of a remaining gate oxide film according to the prior art, and the problems of the prior art will be described with reference to FIG. 1.
그러나, 종래의 기술에서는, 상술한 고폴리머 식각공정 결과, 도 1에 도시된 바와 같이, 다결정실리콘막의 식각비 측면에서 보면, 웨이퍼 존(wafer zone)별 식각비 측정 시 균일도가 불량하게 나타나며, 특히 웨이퍼 센터부위에서 다량의 폴리 머로 인해 식각정지(etch stop)현상이 발생된다. However, in the related art, as a result of the high polymer etching process described above, as shown in FIG. 1, in view of the etching ratio of the polysilicon film, uniformity is poor in measuring the etching ratio of each wafer zone. A large amount of polymer at the wafer center causes etch stops.
한편, 상기 다결정실리콘막 식각 후 기판 표면에 잔류된 게이트산화막 두께 측면에서 보면, 도 1에 도시된 바와 같이, 웨이퍼 존별 잔류된 게이트산화막 두께균일도가 불량하게 나타나며, 웨이퍼 센터부위에서는 다량의 폴리머로 인해 식각정지현상이 발생된다. 여기서, 상기 게이트산화막의 최초두께는 50∼55Å이며, 다결정실리콘막의 식각 후 웨이퍼 센터부위에서의 게이트산화막 두께를 측정하면 폴리머를 합한 두께인 160Å 가량된다. 이후, 상기 폴리머를 제거하기 위해 세정공정을 진행하는 과정에서 게이트산화막이 과도식각된다.On the other hand, in view of the thickness of the gate oxide film remaining on the substrate surface after etching the polysilicon film, as shown in FIG. 1, the uniform thickness of the gate oxide film remaining for each wafer zone appears poor, due to the large amount of polymer in the wafer center region. Etch stop occurs. Here, the initial thickness of the gate oxide film is 50 to 55 kV. When the thickness of the gate oxide film is measured at the wafer center after etching the polysilicon film, the thickness of the gate oxide film is about 160 kPa. Thereafter, the gate oxide film is excessively etched during the cleaning process to remove the polymer.
따라서, 종래기술에 따른 고폴리머 식각공정으로 인해, 웨이퍼 내 다량의 폴리머가 발생되며, 결국 이로인해 게이트전극 간의 브릿지 뿐만 아니라, 이후의 공정에서 게이트전극과 비트라인 간의 브릿지현상이 발생되는 문제점이 있다.Therefore, due to the high polymer etching process according to the prior art, a large amount of polymer in the wafer is generated, which results in not only the bridge between the gate electrodes, but also a bridge phenomenon between the gate electrode and the bit line in a subsequent process. .
상기 문제점을 해결하고자, 본 발명의 목적은 게이트전극용 다결정실리콘막을 식각 시에 다결정실리콘막과 게이트산화막 간의 식각선택비가 낮은 저폴리머 식각공정을 적용함으로써, 웨이퍼 센터부위에서 다결정실리콘막의 식각정지현상을 방지하고, 폴리머 발생율을 낮춰 식각 후 잔류되는 게이트산화막의 두께를 제어할 수 있는 게이트전극 식각방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to apply a low polymer etching process having a low etching selectivity between the polysilicon film and the gate oxide film when etching the polysilicon film for the gate electrode, thereby eliminating the etching stop phenomenon of the polysilicon film at the wafer center. It is to provide a gate electrode etching method that can prevent and reduce the polymer generation rate to control the thickness of the gate oxide film remaining after etching.
상기 목적을 달성하고자, 본 발명의 게이트전극 식각방법은, 반도체기판 위에 게이트산화막 및 게이트전극용 다결정실리콘막을 차례로 형성하는 단계; 상기 다결정실리콘막을 감광막패턴을 마스크로 이용하면서 HBr 및 O2가스를 사용하여 상기 게이트산화막이 노출되도록 식각해서 게이트전극을 형성함과 동시에 상기 게이트전극의 측벽 및 상기 게이트산화막의 표면 상에 폴리머를 발생시키는 단계; 및 상기 감광막 패턴을 제거하고 상기 결과물에 대해 NH4OH/H2O2/H2O의 케미컬을 사용하는 세정공정을 진행하여 상기 게이트전극의 측벽 및 게이트산화막의 표면 상의 폴리머를 선택적으로 제거하는 단계;를 포함한다.In order to achieve the above object, the gate electrode etching method of the present invention comprises the steps of sequentially forming a gate oxide film and a polysilicon film for the gate electrode on the semiconductor substrate; By using the polysilicon film as a photoresist pattern as a mask, the gate oxide film is etched by using HBr and O 2 gas to be exposed to form a gate electrode, and at the same time, polymer is generated on the sidewall of the gate electrode and the surface of the gate oxide film. step; And removing the photoresist pattern and selectively removing the polymer on the sidewall of the gate electrode and the surface of the gate oxide film by performing a cleaning process using a chemical of NH 4 OH / H 2 O 2 / H 2 O on the resultant.
상기 다결정실리콘막을 RIE 및 MERIE 중 어느 하나의 식각장비 내에서 식각하며, 식각장비는 압력을 50mT이하로, 소오스파워를 250W이상, 바이어스파워를 150W이하로 셋팅한다.The polysilicon film is etched in an etching apparatus of any one of RIE and MERIE, and the etching apparatus sets the pressure to 50 mT or less, the source power to 250 W or more, and the bias power to 150 W or less.
상기 HBr을 100sccm의 유량으로, O2를 4sccm 이하의 유량으로 각각 공급한다.The HBr is supplied at a flow rate of 100 sccm, and the O 2 is supplied at a flow rate of 4 sccm or less, respectively.
상기 NH4OH/H2O2/H2O 케미컬로 세정공정을 진행할 때 상기 NH4OH:H2O2:H2O를 1:3∼5:15∼35의 비율로 혼합하며 20∼100℃온도를 유지한다.When the cleaning process is performed with the NH 4 OH / H 2 O 2 / H 2 O chemical, the NH 4 OH: H 2 O 2: H 2 O is mixed at a ratio of 1: 3 to 5:15 to 35 and maintained at a temperature of 20 to 100 ° C.
(실시예)(Example)
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 게이트전극 식각방법을 설명하면 다음과 같다. Hereinafter, a gate electrode etching method according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 게이트전극 식각방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a gate electrode etching method according to the present invention.
본 발명에 따른 게이트전극 식각방법은, 도 2a에 도시된 바와 같이, 먼저 소정의 반도체기판(1)에 게이트산화막(3) 및 게이트전극용 다결정실리콘막(5)을 차례 로 형성한다. 이때, 상기 게이트산화막(3)은 50∼55Å두께로 형성한다. 이어, 상기 다결정실리콘막(5) 위에 감광막을 도포하고 노광 및 현상하여 게이트전극영역(미도시)을 덮는 감광막패턴(7)을 형성한다.In the gate electrode etching method according to the present invention, as shown in FIG. 2A, first, a gate oxide film 3 and a
그런다음, 상기 감광막패턴(7)을 마스크로 하고 다결정실리콘막에 건식식각공정(10)을 진행하여, 도 2b에 도시된 바와 같이, 게이트전극(5a)을 형성한다. 이때, 상기 건식식각공정(10)은 다결정실리콘막과 게이트산화막의 식각선택비가 낮은 식각가스를 사용한 저폴리머식각공정으로서, RIE 및 MERIE 중 어느하나의 식각장비 내에서 진행한다. 또한, 상기 식각가스로는 HBr 및 O2를 사용하며, HBr은 100sccm의 유량으로, O2는 4sccm 이하의 유량으로 각각 공급한다. 그리고, 상기 식각장비 내의 식각조건은 압력을 50mT이하로, 소오스파워를 250W이상, 바이어스파워를 150W이하로 한다. 한편, 상기 건식식각공정에서, 게이트전극(5a) 측벽 및 게이트산화막(3) 표면에는 폴리머(9)가 소량 형성된다.Then, using the photoresist pattern 7 as a mask, a
그런다음, 상기 게이트전극(5a)을 포함한 기판 전면에 세정공정(12)을 진행하여, 도 2c에 도시된 바와 같이, 상기 건식식각 후 생성된 폴리머를 제거한다. 이때, 상기 세정공정(12)에서 식각액으로서 H2SO4/H2O2 및 NH4OH/H2O2/H2O 중 어느하나의 케미컬을 사용한다. 여기서, 상기 세정공정(12)에서 식각액으로서 H2SO4/H2O2 케미컬을 적용할 경우, 상기 H2SO4/H2O2은 3:1∼300:1의 혼합비율을 가지며, 70∼110℃온도를 유지한다. 또는, 상기 세정공정(12)에서 식각액으로서 NH4OH/H2O2/H2O 케미컬을 적용할 경우, 상기 NH4OH/H2O2/H2O은 1:3∼5:15∼35의 혼합비율을 가지며, 20∼100℃온도를 유지한다. Thereafter, a
한편, 상기 세정공정(12)을 통해 게이트산화막 두께는 그대로 유지하면서 폴리머만이 선택적으로 제거된다.On the other hand, only the polymer is selectively removed through the
도 3은 본 발명에 따른 웨이퍼 위치별 다결정실리콘막의 식각비와 잔류된 게이트산화막 두께를 나타낸 그래프이다.3 is a graph showing the etch ratio of the polysilicon film for each wafer position and the thickness of the gate oxide film remaining in accordance with the present invention.
본 발명은, 도 3에 도시된 바와 같이, 다결정실리콘막의 식각비는 기존과 대비해보면 식각균일도 측면에서 크게 개선됨을 알 수 있다.As shown in FIG. 3, the etch ratio of the polysilicon film can be seen to be greatly improved in terms of etching uniformity as compared with the conventional method.
또한, 잔류된 게이트산화막 두께를 기존과 대비하여 보면, 기존에는 웨이퍼 위치별 잔류된 게이트산화막 두께는 폴리머를 합한 두께로서, 특히 웨이퍼 센터부위에서 두껍게 나타났지만, 본 발명을 적용한 결과 웨이퍼 위치별 잔류된 게이트산화막 두께가 일정하며, 웨이퍼 센터부위에서 식각정지현상이 없어짐을 알 수 있다. 따라서, 잔류된 게이트산화막의 균일도 측면에서 개선됨을 알 수 있다. In addition, compared to the remaining gate oxide thickness compared to the conventional, the thickness of the gate oxide film remaining by the wafer position in the past was the sum of the polymer, especially in the wafer center portion appeared thick, but as a result of applying the present invention It can be seen that the gate oxide film thickness is constant, and the etch stop phenomenon is eliminated at the wafer center. Therefore, it can be seen that the improved uniformity of the remaining gate oxide film.
또한, 잔류된 게이트산화막의 절대값은 기존에서는 세정공정 이전 폴리머를 합한 두께인 130Å였지만 본 발명에서는 폴리머 발생율이 낮아짐에 따라 80Å으로 하향됨을 알 수 있다. 이러한 잔류된 게이트산화막의 절대값 하향은 이후의 세정공정을 거치면서 최소화되어야 한다. 왜냐하면, 잔류되는 게이트산화막의 절대값 하향 현상은 실리콘 정션 위 게이트산화막을 과도하게 디핑(dipping)되는 현상을 보여주는 것으로서, 리플래쉬를 저하시키는 원인이 되기 때문이다. 따라서, 이러한 리플래쉬 저하를 막기위해, 본 발명에서는 세정공정을 기존의 BOE 대신 H2SO4/H2O2 및 NH4OH/H2O2/H2O 중 어느 하나의 케미컬을 적용시켜 폴리머만을 선택적으로 제거한다. 이로써, 세정공정 이후에 잔류되는 게이트산화막을 적어도 30Å이상 확보할 수 있다.In addition, although the absolute value of the remaining gate oxide film was conventionally 130 mW, which is the sum of the polymers before the cleaning process, it can be seen that the present invention is lowered to 80 mW as the polymer generation rate is lowered. Absolute reduction of the remaining gate oxide film should be minimized through the subsequent cleaning process. This is because the downward decrease of the absolute value of the gate oxide film shows excessive dipping of the gate oxide film on the silicon junction, which causes a decrease in refresh rate. Therefore, in order to prevent such a decrease in the refresh rate, the present invention selectively removes only the polymer by applying the chemical of any one of H2SO4 / H2O2 and NH4OH / H2O2 / H2O instead of the conventional BOE. Thus, the gate oxide film remaining after the cleaning process can be at least 30 kV or more.
이상에서와 같이, 본 발명은 게이트전극용 다결정실리콘막에 저폴리머 식각공정을 진행함으로써, 상기 다결정실리콘막의 식각비 및 잔류 옥사이드막의 균일도가 개선되고, 이와 동시에 식각정지현상이 방지되어 게이트전극용 다결정실리콘막이 잔류됨에 따른 브릿지현상을 방지할 수 있다.As described above, according to the present invention, by performing a low polymer etching process on the polysilicon film for the gate electrode, the etch ratio of the polysilicon film and the uniformity of the remaining oxide film are improved, and at the same time, the etch stop phenomenon is prevented so that the polycrystalline silicon for the gate electrode is prevented. It is possible to prevent the bridge phenomenon caused by the remaining silicon film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481229A (en) * | 1987-09-22 | 1989-03-27 | Nec Corp | Manufacture of semiconductor device |
| KR930020600A (en) * | 1992-03-04 | 1993-10-20 | 김주용 | Polymer removal method after etching polysilicon |
| KR950025492A (en) * | 1994-02-03 | 1995-09-18 | 김주용 | Polymer removal method during polysilicon etching |
| KR20010003451A (en) * | 1999-06-23 | 2001-01-15 | 김영환 | Method of manufacturing semiconductor device |
| KR20020035992A (en) * | 2000-11-07 | 2002-05-16 | 박종섭 | Method for fabricating semiconductor device |
| KR20030053320A (en) * | 2001-12-22 | 2003-06-28 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481229A (en) * | 1987-09-22 | 1989-03-27 | Nec Corp | Manufacture of semiconductor device |
| KR930020600A (en) * | 1992-03-04 | 1993-10-20 | 김주용 | Polymer removal method after etching polysilicon |
| KR950025492A (en) * | 1994-02-03 | 1995-09-18 | 김주용 | Polymer removal method during polysilicon etching |
| KR20010003451A (en) * | 1999-06-23 | 2001-01-15 | 김영환 | Method of manufacturing semiconductor device |
| KR20020035992A (en) * | 2000-11-07 | 2002-05-16 | 박종섭 | Method for fabricating semiconductor device |
| KR20030053320A (en) * | 2001-12-22 | 2003-06-28 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
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