KR0168208B1 - Polymer removing method - Google Patents
Polymer removing method Download PDFInfo
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- KR0168208B1 KR0168208B1 KR1019950020639A KR19950020639A KR0168208B1 KR 0168208 B1 KR0168208 B1 KR 0168208B1 KR 1019950020639 A KR1019950020639 A KR 1019950020639A KR 19950020639 A KR19950020639 A KR 19950020639A KR 0168208 B1 KR0168208 B1 KR 0168208B1
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- Prior art keywords
- oxide layer
- polypolymer
- semiconductor substrate
- dry etching
- present
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 229920000642 polymer Polymers 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000001312 dry etching Methods 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000009832 plasma treatment Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 9
- 238000002474 experimental method Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 150000002222 fluorine compounds Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 BCl 3 is used Chemical class 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
반도체장치의 제조방법이 개시되어 있다. 본 발명은 반도체장치의 산화층을 건식 식각할 때 생성되는 다중합체를 제거하기 위하여 상기 산화층을 건식 식각한 직후에 산소 플라즈마 처리공정 또는 산소래디클(radical ) 처리공정을 사용하여 상기 다중합체를 제거하는 것을 특징으로 한다.A method for manufacturing a semiconductor device is disclosed. The present invention is to remove the polypolymer using an oxygen plasma treatment process or an oxygen radical treatment process immediately after the dry etching of the oxide layer in order to remove the polypolymer produced when dry etching the oxide layer of the semiconductor device. It is characterized by.
Description
제1도는 본 발명에 따른 다중합체 제거방법을 설명하기 위한 공정순서도이다.1 is a process flow chart for explaining the polypolymer removal method according to the present invention.
본 발명은 반도체장치의 제조시 생성되는 다중합체의 제거방법에 관한 것으로, 특히 산화층을 건식 식각한 후 생성되는 다중합체의 제거방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing polypolymers produced in the manufacture of semiconductor devices, and more particularly, to a method for removing polypolymers produced after dry etching an oxide layer.
최근 반도체장치의 고집적화에 따라 패턴의 크기가 매우 작아지고 있다. 따라서, 도전층 및 절연층을 패터닝하기 위한 식각공정으로 미세패턴 형성에 적합한 건식 식각공정을 주로 사용한다. 이러한 건식식각공정은 식각 대상의 물질에 따라 레서피(recipe)를 다르게 결정한다. 예를 들면, 알루미늄층을 식각할 경우에는 염소(Cl) 화합물, 예컨대 BCl3와 같은 기체를 이용하며, 산화층을 식각할 경우에는 불소(F) 화합물, 예컨대 CF4와 같은 기체를 이용한다. 그러나, 상기 건식 식각공정에 있어서, 불소 화합물을 이용한 레서피로 산화층을 식각하여 그 아래의 도전층, 예컨대 단결정 실리콘층 또는 폴리실리콘층 상에 얇은 산화층을 남기거나 또는 상기 도전층 표면을 노출시킬 경우 도전층 표면에 다중합체가 생성된다. 따라서, 종래에는 이러한 다중합체를 제거하기 위하여 산화층을 건식 식각한 후에 화학용액, 예컨대 HF, NH40H, 또는H2SO4용액으로 세정공정을 실시하였다. 그러나, 상기 화학용액으로 세정공정을 실시한 결과 다중합체가 거의 제거되지 않음을 알 수 있었다. 이에 대한 결과는 본 발명의 효과 설명시 비교예를 통하여 자세히 설명Recently, with the high integration of semiconductor devices, the size of patterns has become very small. Therefore, a dry etching process suitable for forming a fine pattern is mainly used as an etching process for patterning the conductive layer and the insulating layer. This dry etching process determines recipes differently depending on the material to be etched. For example, when etching the aluminum layer, a gas such as a chlorine (Cl) compound such as BCl 3 is used, and when etching an oxide layer, a gas such as a fluorine (F) compound such as CF 4 is used. However, in the dry etching process, the oxide layer is etched using a recipe using a fluorine compound to leave a thin oxide layer on the conductive layer below, for example, a single crystal silicon layer or a polysilicon layer, or to expose the surface of the conductive layer. Polypolymer is produced on the surface of the layer. Therefore, in order to remove such polypolymer, the cleaning process is performed by dry etching the oxide layer, and then using a chemical solution such as HF, NH 4 0H, or H 2 SO 4 solution. However, as a result of the cleaning process with the chemical solution, it was found that the polypolymer was hardly removed. The results for this will be described in detail through a comparative example when explaining the effects of the present invention.
하기로 한다.Let's do it.
상술한 바와 같이 종래 기술에 의하면, 다중합체를 제거함에 있어서 현저한 효과를 보이지 않았다. 이는, 두 도전층 사이의 접촉저항을 크게 중가시키는 요인으로 작용을 하여 반도체장치의 전기적 특성 저하 및 수율 감소에 직접적인 영향을 준다As described above, according to the prior art, there was no significant effect in removing the polypolymer. This acts as a factor that greatly increases the contact resistance between the two conductive layers, thereby directly affecting the electrical characteristics and the yield reduction of the semiconductor device.
따라서, 본 발명의 목적은 산화층을 건식 식각공정으로 식각한 후 생성되는 다중합체를 효과적으로 제거하는 방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a method for effectively removing a polypolymer produced after etching an oxide layer by a dry etching process.
상기 목적을 달성하기 위하여 본 발명은, 반도체장치의 제조방법에 있어서, 산화층을 건식 식각하는 단계 후에 산소 플라즈마 처리공정 또는 산소 래디클(radical) 처리공정을 실시하여, 상기 건식 식각된 표면에 생성된 다중합체를 제거하는 것을 특징으로 하는 다중합체 제거방법을 제공한다.In order to achieve the above object, the present invention, in the method of manufacturing a semiconductor device, after the step of dry etching the oxide layer by performing an oxygen plasma treatment process or an oxygen radical treatment process, it is produced on the dry etched surface Provided is a method for removing a polypolymer, the method comprising removing the polypolymer.
본 발명에 의하면, 산화층을 건식 식각한 후 식각된 표면에 생성되는 다중합체를 제거할 수 있어 두 도전층 사이의 접촉저항을 크게 개선할 수 있다.According to the present invention, after the dry etching of the oxide layer, it is possible to remove the polypolymer generated on the etched surface, thereby greatly improving the contact resistance between the two conductive layers.
이하, 첨부한 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;
제1도는 본 발명에 따른 다중합체 제거방법을 설명하기 위한 공정순서도이 다.1 is a process flow chart for explaining the polypolymer removal method according to the present invention.
제1도를 참조하면, 반도체기판상에 산화층을 형성한다(1). 상기 산화층은 반도체소자의 층간절연층으로 사용되는 모든 CVD 산화층을 포함한다. 예를 들면, 상기 산화층은 플라즈마 산화층, 상압 CVD 산화층, 또는 저압 CVD 산화층으로 형성할 수 있다. 다음에, 상기 산화층을 식각하여 리세스된 흠을 갖는 산화층 패턴을 형성한다(3). 상기 리세스된 홈은 반도체기판의 소정 영역을 노출시키는 콘택흘이거나, 상기 산화층의 일부분이 식각되어 반도체기판을 노출시키지 않는 그루브 형태일 수도 있다. 상기 산화층을 식각하기 위한 식각공정은 불소 화합물 가스, 예컨대 CF4가스 또는 CHF3가스 등을 사용하는 건식식각 공정이 일반적으로 널리 사용된다. 이때, 상기 식각 가스와 산화층이 서로 반응하여 다중합체가 생성된다. 상기 다중합체는 산화층 패턴 표면 또는 노출된 반도체기판 표면에 흡착된다. 이러한 다중합체는 상기 콘택흘을 덮는 도전체막과 반도체기판 사이의 콘택저항을 증가시키어 반도체소자의 전기적인 특성을 저하시킨다. 따라서, 산화층을 식각할 때 생성되는 다중합체는 반드시 제거하여야 한다. 이어서, 상기 산화층 패턴이 형성된 반도체기판을 산소 플라즈마 처리하여 상기 다중합체를 제거한다(5a). 상기 산소 플라즈마 처리 공정 대신에 산소 래디칼 처리 공정을 실시할 수도 있다(5b). 여기서, 상기 산소 플라즈마 처리공정은 5Torr 이하의 압력, 1000w 이하의 RF 전력, 5000sccm 내지 15000sccm의 산소유량, 및 100℃ 내지 500℃의 스테이지 (stage) 온도를 갖는 조건에서 실시하는 것이 바람직하다. 그리고 상기 산소 래디클 처리공정은 오존(O3)을 이용하는 방법으로서, 대기 압 이하의 압혁, 50LPM 내지 200LPM(liter per minute)의 오존유량, 500LPM 내지 1500LPM의 N2O유량, 100℃ 내지 500℃의 스테이지 온도, 및 100℃ 내지 500℃의 디스트로이어(destroyer)온도를 갖는 조건에서 실시하는 것이 바람직하다.Referring to FIG. 1, an oxide layer is formed on a semiconductor substrate (1). The oxide layer includes all the CVD oxide layers used as the interlayer insulating layer of the semiconductor device. For example, the oxide layer may be formed of a plasma oxide layer, an atmospheric pressure CVD oxide layer, or a low pressure CVD oxide layer. The oxide layer is then etched to form an oxide layer pattern with recessed flaws (3). The recessed groove may be a contact hole exposing a predetermined region of the semiconductor substrate or a groove shape in which a portion of the oxide layer is etched to expose the semiconductor substrate. As the etching process for etching the oxide layer, a dry etching process using a fluorine compound gas such as CF 4 gas or CHF 3 gas is generally used. At this time, the etching gas and the oxide layer react with each other to produce a polypolymer. The polypolymer is adsorbed on the oxide layer pattern surface or the exposed semiconductor substrate surface. Such a polypolymer increases the contact resistance between the conductor film covering the contact stream and the semiconductor substrate, thereby lowering the electrical characteristics of the semiconductor device. Therefore, the polypolymer produced when etching the oxide layer must be removed. Subsequently, the semiconductor substrate on which the oxide layer pattern is formed is subjected to oxygen plasma treatment to remove the polypolymer (5a). Instead of the oxygen plasma treatment step, an oxygen radical treatment step may be performed (5b). Here, the oxygen plasma treatment process is preferably carried out under conditions having a pressure of 5 Torr or less, an RF power of 1000 w or less, an oxygen flow rate of 5000 sccm to 15000 sccm, and a stage temperature of 100 ° C. to 500 ° C. In addition, the oxygen radical treatment process is a method using ozone (O 3 ), the reinforcement below atmospheric pressure, ozone flow rate of 50LPM to 200LPM (liter per minute), N 2 O flow rate of 500LPM to 1500LPM, 100 ℃ to 500 ℃ It is preferable to carry out under conditions having a stage temperature of and a destroyer temperature of 100 ° C to 500 ° C.
본 발명자는 상술한 본 발명의 효과를 확인하기 위하여 다음과 같은 실험 을 실시하였다.The present inventors conducted the following experiment to confirm the effects of the present invention described above.
실험방법 및 순서는 1)여러장의 실리콘 웨이퍼 상에 산화층을 동시에 형성하는 단계; 2)상기 여러장의 실리콘 웨이퍼 상에 형성된 산화층을 완전히 제거하기 위하여 동일한 레서피로 과도하게 건식식각하는 단계; 3)상기 산화층이 건식 석각된 실리콘 웨이퍼들의 표면에 대해 엘립소미터(ellipsometer)로 다중합체의 존재여부를 알아보기 위해 잔존 산화층의 두께를 측정하는 단계: 4)상기 잔존 산화층의 두께가 측정된 실리콘 웨이퍼들의 표면을 각각 종래 기술 및 상술한 본 발명에 의한 다중합체 제거방법으로 세정하는 단계: 그리고 5)상기 세정된실리콘 웨이퍼들의 표면에 대해 엘립소미터로 잔존 산화층의 두께를 측정하는 단계로 이루어진다. 여기서, 잔존 산화층의 두께를 측정하는 이유는 다중합체가 제거된 정도를 판단하기 위한 목적이며, 이러한 방법은 일반적으로 널리 사용되고 있다. 그리고 상술한 실험의 제3단계, 즉 산화층이 건식 식각된 실리콘 웨이퍼들의 표면에 대해 잔존 산화층의 두께를 측정한 결과는 약 60Å이었다. 이는 상기 건식 식각공정에 의해 다중합체가 생성되었음을 의미한다.Experimental methods and procedures include the steps of 1) simultaneously forming an oxide layer on several silicon wafers; 2) excessively dry etching with the same recipe to completely remove the oxide layer formed on the plurality of silicon wafers; 3) measuring the thickness of the remaining oxide layer by using an ellipsometer on the surface of the silicon wafer, the oxide layer dry-etched: 4) the thickness of the remaining oxide layer is measured Cleaning the surfaces of the wafers by the polypolymer removal method according to the prior art and the present invention, respectively: and 5) measuring the thickness of the remaining oxide layer with an ellipsometer on the surfaces of the cleaned silicon wafers. Here, the reason for measuring the thickness of the remaining oxide layer is for determining the extent to which the polypolymer is removed, and this method is generally widely used. In addition, the third step of the above experiment, that is, the thickness of the remaining oxide layer on the surfaces of the silicon wafers on which the oxide layer was dry etched was measured to be about 60 GPa. This means that the polymer is produced by the dry etching process.
아래의 표 1은 상기 실험 결과, 즉 종래 기술 및 본 발명에 의한 다중합체 제거방법으로 세정된 각각의 실리콘 웨이퍼의 표면에 대해 잔존산화층의 두께를 측정한 결과이다.Table 1 below is a result of measuring the thickness of the residual oxide layer on the surface of each silicon wafer cleaned by the above experiment results, that is, a polypolymer removal method according to the prior art and the present invention.
상기 표 1로부터 알 수 있듯이 종래 기술에 의한 다중합체 제거방법을 적용한 경우에는 잔존 산화층의 두께가 크게 감소하지 않았음을 알 수 있다. 이는 산화층을 건식 식각한 후 생성된 다중합체가 거의 제거되지 않았음을 의미한다. 그러나, 본 발명에 의한 다중합체 제거방법을 적용한 경우에는 잔존 산화층의 두께가 약 10Å임을 알 수 있다. 이는 통상 실리콘 표면에 형성되는 자연산화층의 두께에 해당하는 값으로 엘립소미터의 측정 한계에 해당하는 값이다. 따라서, 본 발명은 산화층을 통상의 건식 식각공정으로 식각할 때 생성되는 다중합체를 효과적으로 제거할 수 있는 방법을 제공한다.As can be seen from Table 1, it can be seen that the thickness of the remaining oxide layer was not greatly reduced when the method of removing a polymer according to the prior art was applied. This means that almost no polypolymer produced after the dry etching of the oxide layer was removed. However, in the case of applying the polypolymer removal method according to the present invention, it can be seen that the thickness of the remaining oxide layer is about 10 GPa. This is usually a value corresponding to the thickness of the natural oxide layer formed on the silicon surface and corresponding to the measurement limit of the ellipsometer. Accordingly, the present invention provides a method capable of effectively removing the polypolymer produced when the oxide layer is etched by a conventional dry etching process.
아래의 표 2는 본 발명에 대한 상기 실험의 주요 단계가 완료된 후에 그 표면에 대해 엘립소미터로 잔존 산화층의 두께와 아울러 반사율 및 흡수율을 측정한 결과이다. 다시 말해서, 산화층이 형성되지 않은 초기의 실리콘 웨이퍼에 대해 잔존 산화층의 두께, 반사율, 및 흡수율을 측정하고 그 이후의 주요 공정 단계, 즉 산화층을 건식 식각하는 단계 및 본 발명에 의한 다중합체 제거방법을 적용하는 단계 후에 각각 상기 파라미터(잔존 산화층의 두께, 반사율, 및 흡수율)를 측정한 결과이다.Table 2 below shows the results of measuring the thickness and the reflectance and the absorptance of the remaining oxide layer with an ellipsometer on the surface after the main step of the experiment for the present invention is completed. In other words, the thickness of the remaining oxide layer, the reflectance, and the absorptivity of the initial silicon wafer without the oxide layer formed were measured, and the main process steps thereafter, namely, dry etching the oxide layer, and the method for removing the polypolymer according to the present invention After the application step, the parameters (thickness, reflectance, and absorptivity of the remaining oxide layer) were respectively measured.
상기 표 2로부터 본 발명에 의한 다중합체 제거방법을 적용한 후의 상기 파라미터들은 초기의 실리콘 웨이퍼에 대하여 측정한 상기 파라미터들에 비하여 큰 차이를 보이지 않음을 알 수 있다. 이는 산화층을 건식 식각공정으로 식각한 후 생성된 다중합체가 거의 제거되었음을 보여주는 결과이다.It can be seen from Table 2 that the parameters after applying the polypolymer removal method according to the present invention do not show a significant difference compared to the parameters measured for the initial silicon wafer. This is a result showing that the polypolymer produced after etching the oxide layer by the dry etching process is almost removed.
이와 같이 상술한 본 발명에 의하면, 산화층을 건식 식각공정으로 식각한 후에 생성되는 다중합체를 효과적으로 제거할 수 있다. 이는, 반도체장치의 콘택흘 형성시 적용할 경우 콘택저항을 크게 감소시킬 수 있다. 또한, 트랜지스터의 게이트 전극 측벽에 CVD 산화층으로 스페이서를 형성한 후에 적용함으로써, 트랜지스터의 소오스/드레인영역에 가해지는 식각 손상 및 다중합체를 효과적으로 제거하여 트랜지스터의 특성을 개선시킬 수 있다.As described above, according to the present invention, it is possible to effectively remove the polypolymer generated after the oxide layer is etched by the dry etching process. This can greatly reduce the contact resistance when applied at the time of forming the contact flow of the semiconductor device. In addition, by applying the spacer after forming the CVD oxide layer on the sidewall of the gate electrode of the transistor, it is possible to improve the characteristics of the transistor by effectively removing the etch damage and the polypolymer applied to the source / drain regions of the transistor.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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