KR20010003451A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20010003451A
KR20010003451A KR1019990023748A KR19990023748A KR20010003451A KR 20010003451 A KR20010003451 A KR 20010003451A KR 1019990023748 A KR1019990023748 A KR 1019990023748A KR 19990023748 A KR19990023748 A KR 19990023748A KR 20010003451 A KR20010003451 A KR 20010003451A
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South Korea
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gas
etching
adjusted
stock
semiconductor device
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KR1019990023748A
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Korean (ko)
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KR100303357B1 (en
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김재영
안성환
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent damage to a gate oxide layer and to easily form a gate of a uniform vertical profile, by performing a buffer etching process for eliminating a remaining polysilicon layer between a main etching process and an over-etching process. CONSTITUTION: A gate oxide layer(31), a polysilicon layer(32) and a metal silicide layer(33) are sequentially formed on a semiconductor substrate(30). A hard mask(34) is formed on the metal silicide layer. The metal silicide layer, the polysilicon layer and the gate oxide layer are dry-etched using plasma by using the hard mask as an etching mask to form a gate(100) of a polysilicide structure. The dry etching process comprises a main etching process, a buffer etching process and an over-etching process. In the main etching process, all of the metal silicide layer is etched and a part of the polysilicon layer is etched. In the buffer etching process, the remaining polysilicon layer is eliminated. In the over-etching process, polysilicide remnants are eliminated.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device}Method of manufacturing semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리사이드 구조의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate of a polyside structure.

반도체 소자의 집적도가 증가되면서, 게이트의 저항(resistivity)이 중요한 요소로서 작용하기 때문에, 0.15㎛ 이하의 디자인 룰을 갖는 반도체 소자의 경우에는 게이트의 저항특성을 향상시키기 위하여, 폴리실리콘막 상부에 금속 실리사이드막이 적층된 폴리사이드 구조로 게이트를 형성한다. 또한, 폴리사이드 구조의 게이트 형성에 따라 게이트 산화막의 두께가 얇아지면서, 게이트 형성을 위한 식각시 게이트 산화막의 손상이 야기된다. 즉, 상기 식각은 플라즈마를 이용한 건식식각으로 진행하는데, 주식각(main etch) 단계에서 식각속도를 높이고 비교적 높은 바이어스 파워(bias power)를 가하여 금속 실리사이드막과 폴리실리콘막을 모두 식각하기 때문에, 웨이퍼에 입사되는 이온이 높은 에너지를 갖기 때문이다.As the degree of integration of semiconductor devices increases, the resistivity of the gate acts as an important factor. Therefore, in the case of a semiconductor device having a design rule of 0.15 µm or less, a metal on the polysilicon film may be used to improve the resistance of the gate. The gate is formed in a polyside structure in which silicide films are stacked. In addition, as the gate oxide film is thinned according to the gate formation of the polyside structure, damage to the gate oxide film is caused during etching for forming the gate. That is, the etching proceeds to dry etching using a plasma. In the main etch step, both the metal silicide layer and the polysilicon layer are etched by increasing the etching rate and applying a relatively high bias power. This is because the incident ions have high energy.

반면, 상기한 식각으로 인한 게이트 산화막의 손상을 방지하기 위하여, 주식각 단계에서 식각속도 및 바이어스 파워를 낮추게 되면, 도 1에 도시된 바와 같이, 게이트 측벽에 노칭(notching)이 발생되어 균일한 수직 프로파일을 얻는데 어려움이 있다.On the other hand, in order to prevent damage to the gate oxide film due to the etching, when the etching speed and the bias power is lowered in the stock angular step, as shown in Figure 1, notching occurs in the gate sidewall (uniform vertical) Difficulty getting a profile

따라서, 상기한 문제점을 해결하기 위하여, 높은 바이어스 파워를 사용하는 주식각 단계에서, 텅스텐 실리사이드막은 모두 식각하고 폴리실리콘막은 일부 식각하고, 비교적 낮은 바이어스 파워를 사용하는 과도식각(over etch) 단계에서 나머지의 폴리실리콘막 및 주식각에서 발생된 폴리사이드 잔류물(residue)을 제거하는 방법이 제시되었다. 이러한 방법은 주식각 단계에서 게이트의 수직프로파일이 결정되기 때문에, 도 2에 도시된 바와 같이 노칭이 없는 균일한 수직 프로파일의 게이트를 얻을 수 있고, 주식각 단계에서 남겨진 폴리실리콘막에 의해 게이트 산화막의 노출이 방지되므로 게이트 산화막의 손상이 방지된다.Therefore, in order to solve the above problem, in the stock angle step using high bias power, all of the tungsten silicide films are etched, the polysilicon film is partially etched, and the rest in the over etch step using relatively low bias power. A method of removing polyside residues generated in polysilicon films and stock angles of is proposed. In this method, since the vertical profile of the gate is determined at the stock angle step, a gate of uniform vertical profile without notching can be obtained as shown in FIG. 2, and the polysilicon film left at the stock angle step is used to Since exposure is prevented, damage to the gate oxide film is prevented.

그러나, 상기한 방법은 주식각 단계에서 게이트 산화막의 보호를 위하여 남겨진 폴리실리콘막을 과도식각 단계에서 제거할 때 급격한 압력 변화가 발생된다. 이러한 불안정한 압력에 의해, 도시되지는 않았지만, 폴리사이드 잔류물이 완전히 제거되어 않을 뿐만 아니라 게이트 산화막의 손상이 야기되고, 심한 경우 일시적인 플라즈마 오프 현상으로 식각이 중단되는 문제가 발생한다. 따라서, 챔버내의 압력을 일정하게 유지시키기 위하여 압력밸브를 조절하나, 상기한 과도식각 단계에서 압력을 안정화시키는데 요구되는 시간과 남겨진 폴리실리콘막 식각하는데 소요되는 시간이 거의 유사하기 때문에 압력을 유지하는 밸브를 안정화시켰다 하더라도 다시 불안정해진다.However, in the above method, a sudden pressure change occurs when the polysilicon film left for protecting the gate oxide film is removed in the transient etching step. This unstable pressure, although not shown, not only completely removes the polyside residue, but also causes damage to the gate oxide layer, and in severe cases, the etching is stopped due to a temporary plasma off phenomenon. Therefore, the pressure valve is adjusted to keep the pressure in the chamber constant, but the pressure maintaining valve is similar because the time required for stabilizing the pressure in the transient etching step and the time required for etching the remaining polysilicon film are almost similar. Even if stabilized, it becomes unstable again.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 게이트 형성시 주식각 단계와 과도식각 단계 사이에 완충식각 단계를 도입하여 불안정한 압력으로 인한 게이트 산화막의 손상을 방지하고 균일한 수직 프로파일의 게이트를 용이하게 얻을 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, to prevent the damage of the gate oxide film due to unstable pressure by introducing a buffer etching step between the stock etching step and the transient etching step when forming the gate and the uniform vertical profile It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a gate can be easily obtained.

도 1 및 도 2는 종래의 게이트 형성방법에 의해 형성된 게이트의 단면도.1 and 2 are cross-sectional views of a gate formed by a conventional gate forming method.

도 3은 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.3 is a cross-sectional view illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.

도 4 및 도 5는 본 발명의 실시예에 따라 형성된 게이트의 단면도.4 and 5 are cross-sectional views of gates formed in accordance with embodiments of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

30 : 반도체 기판 31 : 게이트 산화막30 semiconductor substrate 31 gate oxide film

32 : 폴리실리콘막 33 : 텅스텐 실리사이드막32 polysilicon film 33 tungsten silicide film

100 : 게이트 34 : 하드 마스크100: gate 34: hard mask

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라 반도체 기판 상에 게이트 산화막, 폴리실리콘막 및 금속 실리사이드막을 순차적으로 형성하고, 금속 실리사이드막 상에 하드 마스크를 형성한다. 그런 다음, 하드 마스크를 식각 마스크로 하여 상기 금속 실리사이드막, 폴리실리콘막 및 게이트 산화막을 플라즈마를 이용한 건식식각으로 식각하여 폴리사이드 구조의 게이트를 형성한다. 여기서, 식각은 상기 금속 실리사이드막은 모두 식각하고 상기 폴리실리콘막은 일부 식각하는 주식각 단계와, 주식각 단계에서 남겨진 폴리실리콘막을 제거하는 완충식각 단계와, 식각시 발생된 폴리사이드 잔류물을 제거하는 과도식각단계를 포함한다.In order to achieve the object of the present invention described above, according to the present invention, a gate oxide film, a polysilicon film and a metal silicide film are sequentially formed on a semiconductor substrate, and a hard mask is formed on the metal silicide film. Then, the metal silicide layer, the polysilicon layer, and the gate oxide layer are etched by dry etching using plasma to form a gate having a polyside structure using the hard mask as an etching mask. Here, the etching is a stock etch step of etching all of the metal silicide film and the polysilicon film is partially etched, a buffer etching step of removing the polysilicon film left in the stock angular step, and a transient removal of the polyside residue generated during etching. Etch step is included.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3을 참조하면, 반도체 기판(30) 상에 게이트 산화막(31)을 형성하고, 게이트 산화막(31) 상에 폴리실리콘막(32)과 금속 실리사이드막으로서 예컨대 텅스텐 실리사이드막(33)을 순차적으로 형성한다. 그런 다음, 텅스텐 실리사이드막(33) 상부에 산화막 또는 질화막과 같은 절연막을 증착하고 패터닝하여 하드 마스크 (34)를 형성한다. 그리고 나서, 하드 마스크(34)를 식각 마스크로하여 텅스텐 실리사이드막(33), 폴리실리콘막(32) 및 게이트 산화막(31)을 플라즈마를 이용한 건식식각을 주식각 단계, 완충식각 단계 및 과도식각 단계의 3단계로 진행하여, 게이트 산화막(31)의 손상을 방지하고 균일한 수직 프로파일을 갖는 폴리사이드 구조의 게이트(100)를 형성한다. 여기서, 완충식각 단계는 과도식각 단계에서 압력의 안정성을 높이기 위하여 진행한다.Referring to FIG. 3, a gate oxide film 31 is formed on a semiconductor substrate 30, and a tungsten silicide film 33 is sequentially formed as a polysilicon film 32 and a metal silicide film on the gate oxide film 31. Form. Then, an insulating film such as an oxide film or a nitride film is deposited and patterned on the tungsten silicide film 33 to form a hard mask 34. Then, the dry etching using plasma using the tungsten silicide layer 33, the polysilicon layer 32, and the gate oxide layer 31 using the hard mask 34 as an etching mask is performed by the stock etching step, the buffer etching step, and the transient etching step. Proceeding to step 3, the gate oxide film 31 is formed to prevent damage to the gate oxide layer 31 and to form a polyside structure gate 100 having a uniform vertical profile. Here, the buffer etching step proceeds to increase the stability of the pressure in the transient etching step.

즉, 주식각 단계에서는 텅스텐 실리사이드막(32)은 모두 식각하고 폴리실리콘막(32)을 일부 식각하여 게이트 산화막(31)의 노출을 방지하는데, 이때 균일한 수직 프로파일을 얻기 위하여 비교적 높게, 바람직하게 60 내지 500W로 바이어스 파워를 조절하고, 전기온도(electrode temperature)를 -20 내지 ＋60℃의 범위로 조절하고, 압력을 5 내지 100mTorr로 조절하고, 소오스 파워를 300 내지 1,00W로 조절하여 플라즈마를 발생시키고, 주식각개스로서 Cl2개스나 SF6개스를 이용하여 진행한다. 바람직하게, 상기 주식각개스의 유량은 20 내지 200sccm으로 조절하고, 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가한다. 이때, 첨가개스의 유량은 1 내지 100sccm으로 조절한다.That is, in each stock step, all of the tungsten silicide films 32 are etched and some of the polysilicon films 32 are etched to prevent the gate oxide film 31 from being exposed. Adjust the bias power to 60 to 500 W, adjust the electrode temperature in the range of -20 to + 60 ° C, adjust the pressure to 5 to 100 mTorr, and adjust the source power to 300 to 1,00 W to control the plasma. occurs and, as each of the stock gas proceeds by using a Cl 2 gae seuna SF 6 gas. Preferably, the flow rate of each stock gas is adjusted to 20 to 200 sccm, and O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to the stock gas. At this time, the flow rate of the added gas is adjusted to 1 to 100 sccm.

또한, 완충식각단계에서는 주식각 단계에서 남겨진 폴리실리콘막(32)을 제거하는데, 이때 게이트 산화막(31)의 노출에 따른 손상을 방지하기 위하여 비교적 낮게, 바람직하게 50 내지 300W로 바이어스 파워를 조절하고, 전기온도(electrode temperature)를 -20 내지 ＋60℃의 범위로 조절하고, 압력을 5 내지 100mTorr로 조절하고, 소오스 파워를 300 내지 1,000W로 조절하여 플라즈마를 발생시키고, 주식각개스로서 Cl2개스나 SF6개스를 이용하여 진행한다. 바람직하게, 상기 주식각개스의 유량은 20 내지 200sccm으로 조절하고, 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가한다. 이때, 첨가개스의 유량은 1 내지 100sccm으로 조절한다.In addition, in the buffer etching step, the polysilicon film 32 left in the stock angle step is removed. In this case, the bias power is controlled to be relatively low, preferably 50 to 300 W, in order to prevent damage due to exposure of the gate oxide film 31. Adjust the temperature of the electrode (electrode temperature) in the range of -20 to +60 ℃, the pressure to 5 to 100mTorr, the source power to 300 to 1,000W to generate a plasma, Cl 2 as each stock gas Proceed with 6 gas or 6 SF. Preferably, the flow rate of each stock gas is adjusted to 20 to 200 sccm, and O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to the stock gas. At this time, the flow rate of the added gas is adjusted to 1 to 100 sccm.

또한, 과도식각 단계에서는 주식각 단계에서 발생된 폴리사이드막의 잔류물을 완전히 제거하는데, 이때 바이어스 파워를 0 내지 200W로 낮게 조절하고, 전기온도(electrode temperature)를 -20 내지 ＋60℃의 범위로 조절하고, 소오스 파워를 100 내지 500W로 조절하여 플라즈마를 발생시키고, 주식각개스로서 Cl2개스나 SF6개스를 이용하여 진행한다. 바람직하게, 상기 주식각개스의 유량은 10 내지 100sccm으로 조절하고, 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가한다. 이때, 첨가개스의 유량은 1 내지 100sccm으로 조절한다. 또한, 플라즈마의 발생시, 소오스 파워와 바이어스 파워의 비율을 4 : 1 내지 1 : 1의 범위로 조절한다.In addition, in the transient etching step, the residue of the polyside film generated in the stock angle step is completely removed. At this time, the bias power is adjusted to 0 to 200 W, and the electrode temperature is controlled to be in the range of -20 to + 60 ° C. Then, the plasma power is generated by adjusting the source power to 100 to 500 W, and proceed using Cl 2 gas or SF 6 gas as the stock gas. Preferably, the flow rate of each stock gas is adjusted to 10 to 100 sccm, and O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to the stock gas. At this time, the flow rate of the added gas is adjusted to 1 to 100 sccm. In addition, when the plasma is generated, the ratio of the source power and the bias power is adjusted in the range of 4: 1 to 1: 1.

한편, 도 4 및 도 5는 상기한 본 발명에 의해 형성된 게이트의 단면도로서, 도 4는 산화막의 하드 마스크를 이용하여 식각을 진행한 후의 게이트의 단면도이고, 도 5는 질화막의 하드 마스크를 질화막으로 이용하여 식각을 진행한 후의 게이트의 단면도이다. 도 4 및 도 5에 나타낸 바와 같이, 본 발명에서는 게이트 산화막의 손상이 발생되지 않을 뿐만 아니라 측벽 노칭이 없는 균일한 수직 프로파일의 게이트를 얻을 수 있다.4 and 5 are cross-sectional views of the gate formed by the present invention described above. FIG. 4 is a cross-sectional view of the gate after etching using a hard mask of an oxide film, and FIG. 5 is a hard mask of a nitride film as a nitride film. It is sectional drawing of the gate after etching using it. As shown in Figs. 4 and 5, in the present invention, the gate oxide film is not damaged and a gate having a uniform vertical profile without sidewall notching can be obtained.

상기한 본 발명에 의하면, 게이트 형성을 위한 식각시 주식각단계와 과도식각 단계 사이에, 과도식각시 남은 폴리실리콘막의 식각으로 인한 압력의 불안정을 방지하기 위하여, 남은 폴리실리콘막을 제거하기 위한 완충식각 단계를 부가함으로써, 게이트 산화막의 손상을 방지하면서 균일한 수직 프로파일의 게이트를 용이하게 얻을 수 있다.According to the present invention described above, a buffer etching process for removing the remaining polysilicon film, in order to prevent instability of the pressure due to the etching of the remaining polysilicon film during the excessive etching between the stock etching step and the transient etching step for forming the gate By adding the step, a gate of uniform vertical profile can be easily obtained while preventing damage to the gate oxide film.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (18)

반도체 기판 상에 게이트 산화막, 폴리실리콘막 및 금속 실리사이드막을 순차적으로 형성하는 단계;Sequentially forming a gate oxide film, a polysilicon film, and a metal silicide film on the semiconductor substrate; 상기 금속 실리사이드막 상에 하드 마스크를 형성하는 단계;Forming a hard mask on the metal silicide layer; 상기 하드 마스크를 식각 마스크로 하여 상기 금속 실리사이드막, 폴리실리콘막 및 게이트 산화막을 플라즈마를 이용한 건식식각으로 식각하여 폴리사이드 구조의 게이트를 형성하는 단계를 포함하고,Etching the metal silicide layer, the polysilicon layer, and the gate oxide layer by dry etching using plasma to form a gate having a polyside structure using the hard mask as an etching mask, 상기 식각은 상기 금속 실리사이드막은 모두 식각하고 상기 폴리실리콘막은 일부 식각하는 주식각 단계와,The etching may be a stock etching step of etching all of the metal silicide layer and partially etching the polysilicon layer; 상기 주식각 단계에서 남겨진 폴리실리콘막을 제거하는 완충식각 단계와,A buffer etching step of removing the polysilicon film left in the stock step; 상기 식각시 발생된 폴리사이드 잔류물을 제거하는 과도식각단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device comprising the over-etching step of removing the polyside residue generated during the etching. 제 1 항에 있어서, 상기 주식각 단계에서는 바이어스 파워를 60 내지 500W로 조절하고, 전기온도를 -20 내지 ＋60℃의 범위로 조절하고, 압력을 5 내지 100mTorr로 조절하고, 소오스 파워를 300 내지 1,00W로 조절하여 플라즈마를 발생시키는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in each stock step, the bias power is adjusted to 60 to 500W, the electric temperature is adjusted to a range of -20 to + 60 ° C, the pressure is adjusted to 5 to 100 mTorr, and the source power is 300 to 1 The semiconductor device manufacturing method characterized in that to generate a plasma by adjusting to. 제 1 항 또는 제 2 항에 있어서, 상기 주식각 단계는 주식각 개스로서 Cl2개스나 SF6개스를 이용하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the stock angle step is performed using Cl 2 gas or SF 6 gas as the stock angle gas. 제 3 항에 있어서, 상기 주식각개스의 유량은 20 내지 200sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.4. The method of claim 3, wherein the flow rate of each stock gas is adjusted to 20 to 200 sccm. 제 4 항에 있어서, 상기 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to each stock gas. 제 5 항에 있어서, 상기 첨가개스의 유량은 1 내지 100sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 5, wherein the flow rate of the additive gas is adjusted to 1 to 100 sccm. 제 1 항에 있어서, 상기 완충식각 단계에서는 바이어스 파워를 50 내지 300W로 조절하고, 전기온도를 -20 내지 ＋60℃의 범위로 조절하고, 압력을 5 내지 100mTorr로 조절하고, 소오스 파워를 300 내지 1,000W로 조절하여 플라즈마를 발생시키는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in the buffer etching step, the bias power is adjusted to 50 to 300W, the electric temperature is adjusted to a range of -20 to +60 ℃, the pressure is adjusted to 5 to 100mTorr, the source power is 300 to 1,000 A method of manufacturing a semiconductor device, characterized in that to generate a plasma by adjusting to W. 제 1 항 또는 제 7 항에 있어서, 상기 완충식각 단계는 주식각개스로서 Cl2개스나 SF6개스를 이용하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the buffer etching process is performed using Cl 2 gas or SF 6 gas as staple gas. 제 8 항에 있어서, 상기 주식각개스의 유량은 20 내지 200sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 8, wherein the flow rate of each stock gas is adjusted to 20 to 200 sccm. 제 9 항에 있어서, 상기 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가하는 것을 특징으로 하는 반도체 소자의 제조방법.10. The method of manufacturing a semiconductor device according to claim 9, wherein O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to each stock gas. 제 10 항에 있어서, 상기 첨가개스의 유량은 1 내지 100sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 10, wherein the flow rate of the additive gas is adjusted to 1 to 100 sccm. 제 1 항에 있어서, 상기 과도식각 단계에서는 바이어스 파워를 0 내지 200W로 낮게 조절하고, 전기온도를 -20 내지 ＋60℃의 범위로 조절하고, 소오스 파워를 100 내지 500W로 조절하여 플라즈마를 발생시키는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in the transient etching step, the bias power is lowered to 0 to 200W, the electric temperature is adjusted to a range of -20 to + 60 ° C, and the source power is adjusted to 100 to 500W to generate plasma. A semiconductor device manufacturing method characterized by the above-mentioned. 제 1 항 또는 제 12 항에 있어서, 상기 과도식각 단계는 주식각개스로서 Cl2개스나 SF6개스를 이용하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1 or 12, wherein the transient etching is performed using Cl 2 gas or SF 6 gas as the stock gas. 제 13 항에 있어서, 상기 주식각개스의 유량은 10 내지 100sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 13, wherein the flow rate of each stock gas is adjusted to 10 to 100 sccm. 제 14 항에 있어서, 상기 주식각개스에 O2, N2, HBr 개스 또는 이들의 혼합개스를 선택적으로 첨가하는 것을 특징으로 하는 반도체 소자의 제조방법.15. The method of manufacturing a semiconductor device according to claim 14, wherein O 2 , N 2 , HBr gas or a mixed gas thereof is selectively added to each stock gas. 제 15 항에 있어서, 상기 첨가개스의 유량은 1 내지 100sccm으로 조절하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 15, wherein the flow rate of the additive gas is adjusted to 1 to 100 sccm. 제 12 항에 있어서, 상기 과도식각은 소오스 파워와 바이어스 파워의 비율은 4 : 1 내지 1 : 1의 범위로 조절하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 12, wherein the transient etching is performed by adjusting a ratio of the source power and the bias power to a range of 4: 1 to 1: 1. 제 1 항에 있어서, 상기 하드 마스크는 산화막 또는 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the hard mask is formed of an oxide film or a nitride film.
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Publication number Priority date Publication date Assignee Title
KR100701687B1 (en) * 2003-12-23 2007-03-29 주식회사 하이닉스반도체 Method for etching gate electrodes

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701687B1 (en) * 2003-12-23 2007-03-29 주식회사 하이닉스반도체 Method for etching gate electrodes

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