KR100688820B1 - Data Integrated Circuit and Light Emitting Display Using The Same - Google Patents

Abstract

The present invention relates to a data integrated circuit capable of displaying an image of desired luminance.

A data integrated circuit of the present invention comprises: a shift register section for sequentially generating sampling signals; A latch unit for storing data supplied from the outside in response to the sampling signal; A voltage digital-to-analog converter for generating a gray scale voltage corresponding to the data stored in the latch unit; A current digital-analog converter configured to generate a gradation current corresponding to the data stored in the latch unit; A buffer unit for supplying the gray voltage to the pixels as a data signal; Receiving a pixel current flowing in the pixels in response to the gray voltage, and comparing the pixel current with the gray current; And a voltage adjusting block for increasing or decreasing the voltage supplied to the pixels via the buffer unit in response to the comparison result.

Description

Data integrated circuit and light emitting display using the same             

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an embodiment of the data integrated circuit shown in FIG. 2.

4 is a block diagram illustrating another embodiment of the data integrated circuit shown in FIG. 2.

FIG. 5 is a detailed block diagram illustrating the voltage adjuster illustrated in FIGS. 3 and 4.

FIG. 6 is a diagram illustrating turn-on and turn-off timings of the switching device illustrated in FIG. 5.

FIG. 7 is a diagram illustrating a voltage range controlled by the voltage increase and decrease unit illustrated in FIG. 5.

8 is a diagram schematically illustrating a pixel according to a first embodiment of the present invention.

9 is a diagram illustrating a detailed structure of a pixel illustrated in FIG. 8.

FIG. 10 is a diagram illustrating a driving waveform supplied to the pixel illustrated in FIG. 9.

11 is a diagram schematically illustrating a pixel according to a second embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of the pixel structure illustrated in FIG. 11.

FIG. 13 is a diagram illustrating another example of the pixel structure illustrated in FIG. 11.

FIG. 14 is a diagram illustrating a driving waveform supplied to the pixel illustrated in FIG. 12.

15 to 16 are diagrams illustrating still another example of the pixel structure illustrated in FIG. 11.

17 is a pixel structure in which the transistors shown in FIG. 12 are converted to NMOS.

FIG. 18 is a diagram illustrating a driving waveform supplied to the pixel illustrated in FIG. 17.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: image display unit 40,140: pixel

50,150: timing controller 129: data integrated circuit

141, 142, 144, 145: switching block 143, 146: pixel circuit

200: shift register portion 210: sampling latch portion

220: holding latch portion 230: voltage digital to analog converter

240: current digital-analog converter 250: voltage regulator

252: comparator 254: voltage increase and decrease

256: control unit 260: buffer unit

270 level shifter

The present invention relates to a data integrated circuit and a light emitting display device using the same, and more particularly, to a data integrated circuit and a light emitting display device using the same to display an image of a desired brightness.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device emits light from a light emitting device by supplying a current corresponding to the data signal to the light emitting device using a transistor formed for each pixel.

1 illustrates a conventional light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed in an area partitioned by scan lines S1 to Sn and data lines D1 to Dm; Controlling the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20 The timing control part 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal.

The image display unit 30 receives the first power source VDD and the second power source VSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power source VDD and the second power source VSS receives a current flowing from the first power source VDD to the second power source VSS via the light emitting element in response to the data signal. The control generates light corresponding to the data signal.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, in the related art, light having a desired luminance may not be generated due to a nonuniform threshold voltage of a transistor included in each of the pixels 40. In the related art, there is no method of measuring and controlling the current flowing in each of the pixels 40 in response to the data signal.

Accordingly, an object of the present invention is to provide a data integrated circuit and a light emitting display device using the same, which are capable of displaying an image having a desired luminance.

In order to achieve the above object, the first aspect of the present invention is a shift register unit for sequentially generating a sampling signal, a latch unit for storing data supplied from the outside corresponding to the sampling signal, and the latch unit A voltage digital-analog converter for generating a gray scale voltage corresponding to the stored data, a current digital-analog converter for generating a gray current corresponding to the data stored in the latch unit, and using the gray voltage as a data signal as pixels. A buffer for supplying and receiving a pixel current flowing in the pixels in response to the gray voltage, comparing the pixel current with the gray current, and passing the pixel current to the pixels through the buffer in response to the comparison result. Providing a data integrated circuit having a voltage adjusting block for increasing or decreasing a supplied voltage .

Preferably, the voltage adjusting block compares the pixel current with the gradation current, and increases or decreases the voltage supplied to the pixels via the buffer unit in response to the comparison result. The latch unit corresponds to the sampling signal to sequentially store the data, and a sampling latch unit to store the data stored in the sampling latch unit and at the same time the stored data is converted into the voltage digital to analog converter and current digital to analog And a holding latch portion for supplying to the portion. And a level shifter for raising a voltage level of the data stored in the holding latch unit and supplying the voltage to the voltage digital-analog converter and the current digital-analog converter. The voltage adjusting block includes j voltage adjusting units for controlling j (j is a natural number) gray voltages. Each of the voltage adjusting units has its own switching device provided between the voltage digital-to-analog converter and the buffer unit, a comparison unit for comparing the pixel current and the gradation current, and a common terminal of the switching element and the buffer unit. A capacitor connected to one terminal of the capacitor, a voltage increase and decrease unit connected to the other terminal of the capacitor and increasing or decreasing a voltage supplied to the other terminal of the capacitor by the control of the comparing unit, and a control unit for controlling the switching element. Equipped.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIG. 2 to FIG. 18 to which a person skilled in the art may easily implement the present invention.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention includes pixels formed in regions partitioned by scan lines S1 to Sn, data lines D1 to Dm, and feedback lines F1 to Fm. An image display unit 130 including 140, a scan driver 110 for driving the scan lines S1 to Sn, a data driver 120 for driving the data lines D1 to Dm, and a scan. A timing controller 150 for controlling the driver 110 and the data driver 120 is provided.

The image display unit 130 includes pixels 140 connected to the scan lines S1 to Sn, the emission control lines E1 to En, the data lines D1 to Dm, and the feedback lines F1 to Fm. The scan lines S1 to Sn are formed in a horizontal direction to supply scan signals to the pixels 140. The emission control lines E1 to En are formed in the horizontal direction to supply the emission control signal to the pixels 140. The data lines D1 to Dm are formed in the vertical direction to supply data signals to the pixels 140. The feedback lines F1 to Fm supply the pixel current supplied from the pixels 140 to the data driver 120. To this end, the feedback lines F1 to Fm are formed in the same direction (that is, the vertical direction) with the data lines D1 to Dm. The feedback lines F1 to Fm receive current from the pixels 140 to which the current data signal is supplied. In other words, the pixel current generated in the pixels 140 currently receiving the scan signal is supplied to the data driver 120 via the feedback lines F1 to Fm.

Meanwhile, the pixels 140 receive a first power source VDD and a second power source VSS from the outside. Each of the pixels 140 supplied with the first power source VDD and the second power source VSS has a second power source via the light emitting element from the first power source VDD in response to a data signal from the data line D. FIG. Control the current flowing to (VSS). The pixels 140 supply a current (pixel current) corresponding to the data signal to the feedback line F when the data signal is supplied.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 110 receiving the scan driving control signal SCS generates an emission control signal and sequentially supplies the generated emission control signal to the emission control lines E1 to En.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal. Here, the data driver 120 supplies a predetermined gray scale voltage to the data lines D as a data signal.

The data driver 120 receives the pixel current from each of the pixels 140 via the feedback lines F1 to Fm. The data driver 120 receiving the pixel current checks whether the current value of the pixel current corresponds to the data. For example, when the pixel current to flow in the pixel 140 corresponding to the number of bits (or gradation value) of the data (Data) is 10 ㎂, the data driver 120 checks whether the pixel current supplied to it is 10 ㎂ do. Here, when the desired current is not supplied from each of the pixels 140, the data driver 120 changes the gray voltage so that a desired current flows from each of the pixels 140. To this end, the data driver 120 includes at least one data integrated circuit 129 including j channels (where j is a natural number).

3 is a view illustrating in detail the data integrated circuit shown in FIG. 2.

Referring to FIG. 3, the data integrated circuit 129 may include a shift register unit 200 for sequentially generating sampling signals, and a sampling latch unit 210 for sequentially storing data in response to the sampling signals. The data data of the sampling latch unit 210 may be temporarily stored, and the stored data may be stored in a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 230 and a current digital-to-analog converter. Holding latch 220 for supplying to the 240 (hereinafter referred to as " IDAC unit "), VDAC unit 230 for generating a gradation voltage Vdata corresponding to the gradation value of data Data, and data Changing the gray scale voltage Vdata in response to the IDAC unit 240 generating the gray scale current Idata corresponding to the gray scale value of Data and the pixel current Ipixel supplied from the feedback lines F1 to Fj. The voltage adjusting block 250 and the gray scale voltage Vdata supplied from the voltage adjusting block 250 A buffer unit 260 for supplying the data lines D1 to Dj is provided.

The shift register unit 200 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 200 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 200 includes j shift registers 2001 to 200j.

The sampling latch unit 210 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 200. Here, the sampling latch unit 210 includes j sampling latches 2101 to 210j to store j data. Each of the sampling latches 2101 to 210j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2101 to 210j is set to a size of k bits.

The holding latch unit 220 receives data from the sampling latch unit 210 and stores the data when the source output enable signal SOE is input. The holding latch unit 220 supplies data stored therein to the VDAC unit 230 and the IDAC unit 240 when the source output enable signal SOE is input. To this end, the holding latch unit 220 includes j holding latches 2201 to 220j set to k bits.

The VDAC unit 230 generates a gray voltage Vdata corresponding to a bit value (that is, a gray value) of the data Data, and supplies the generated gray voltage Vdata to the voltage adjusting block 250. Here, the VDAC unit 230 generates j gray voltages Vdata corresponding to j data Data supplied from the holding latch unit 220.

The IDAC unit 240 generates a gradation current Idata corresponding to the bit value of the data, and supplies the generated gradation current Idata to the voltage adjusting block 250. Here, the IDAC unit 240 generates j gradation currents Idata corresponding to j data Data supplied from the holding latch unit 220.

The voltage adjustment block 250 is supplied with a gray voltage Vdata, a gray current Idata, and a pixel current Ipixel. The voltage adjusting block 250 supplied with the gradation voltage Vdata, the gradation current Idata, and the pixel current Ipixel compares the current difference between the gradation current Idata and the pixel current Ipixel, and compares the current difference with each other. Correspondingly, the gradation voltage Vdata is adjusted. Ideally, the voltage adjusting block 250 adjusts the voltage value of the gray voltage Vdata so that the gray current Idata and the pixel current Ipixel can be set to the same value. To this end, the voltage adjusting block 250 includes j voltage adjusting units 2501 to 250j.

The buffer unit 260 supplies the gray voltage Vdata supplied from the voltage adjusting block 250 to the j data lines D1 to Dj. To this end, the buffer unit 260 includes j buffers 2601 to 260j.

Meanwhile, in the present invention, as shown in FIG. 4, the level shifter unit 270 may be further included between the holding latch unit 220, the VDAC unit 230, and the IDAC unit 240. The level shifter unit 270 increases the voltage level of the data Data supplied from the holding latch unit 220 and supplies it to the VDAC unit 230 and the IDAC unit 240. When data having a high voltage level is supplied to the data integrated circuit 129 from an external system, a manufacturing cost increases because circuit components corresponding to the voltage level need to be installed. Therefore, the data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level sheeter 270 to a high voltage level.

FIG. 5 is a view illustrating in detail the voltage adjusting unit illustrated in FIG. 4. In FIG. 5, the j th voltage adjustor 250j is illustrated for convenience of description.

Referring to FIG. 5, the voltage adjusting unit 250j includes a comparator 252, a voltage increase / decrease unit 254, a controller 256, a first capacitor C1, and a switching device M1.

The switching element M1 is provided between the VDAC unit 230 and the buffer 260j. The switching device M1 is turned on or turned off under the control of the controller 256. In practice, the switching element M1 is turned on only in the data signal supply period (first period) during one horizontal period as shown in Fig. 6, and is turned off in the other feedback period (second period).

The first capacitor C1 is provided between the first node N1, which is a common terminal of the switching element M1, and the buffer 260j, and the voltage increase / decrease unit 254. The first capacitor C1 provided between the first node N1 and the voltage increase / decrease unit 254 increases or decreases the voltage value of the first node N1 in response to the voltage supplied from the voltage increase / decrease unit 254. That is, when a high voltage is supplied from the voltage increase / decrease unit 254, the voltage value of the first node N1 is increased by the first capacitor C1, and when a low voltage is supplied from the voltage increase / decrease unit 254, the first capacitor is supplied. The voltage value of the first node N1 is decreased by C1.

The comparator 252 receives the gradation current Idata from the IDAC unit 240 and the pixel current Ipixel from the pixel 140. Here, the pixel current Ipixel is supplied from the pixel 140 to which the current data signal is supplied. The comparison unit 252 supplied with the pixel current Ipixel and the gradation current Idata compares the gradation current Idata and the pixel current Ipixel, and compares the first control signal or the second control signal corresponding to the result of the comparison. Is supplied to the voltage increase / decrease unit 254. For example, the comparator 252 generates the first control signal when the gradation current Idata is greater than the pixel current Ipixel, and the second control signal when the gradation current Idata is smaller than the pixel current Ipixel. Is generated and supplied to the voltage increase / decrease unit 254.

The voltage increase / decrease unit 254 supplies a voltage value corresponding to the first control signal or the second control signal to the first capacitor C1. For example, the voltage increase / decrease unit 254 supplies a predetermined voltage to the first capacitor C1 so that the voltage of the first node N1 is lowered when the first control signal is input. Here, when the voltage of the first node N1 (ie, the gray voltage Vdata) falls, the pixel current Ipixel flowing in the pixels 140 increases. The voltage increasing / decreasing unit 254 supplies a predetermined voltage to the first capacitor C1 so that the voltage of the first node N1 is increased when the second control signal is input. Herein, when the voltage of the first node N1 (ie, the gray voltage Vdata) increases, the pixel current Ipixel flowing in the pixels 140 decreases.

The controller 256 turns on the switching element M1 during the data signal supply period during one horizontal period 1H, and turns off the switching element M1 during the feedback period. The controller 256 supplies a counting signal gradually increasing during the feedback period to the voltage increase / decrease unit 254. For example, the controller 256 supplies a counting signal that increases from "1" to "j" (j is a natural number) to the voltage increase / decrease unit 254. To this end, a counter (not shown) is included in the control unit 256. The counting signal of the controller 256 is initialized when the reset signal Reset is supplied. Here, the reset signal Reset is set to a signal supplied in units of one horizontal period. For example, the reset signal Reset may be used as the horizontal synchronization signal H or the scan signal.

Referring to the operation process in detail, first, the control unit 256 turns on the switching element M1 during the data signal supply period during one horizontal period 1H. When the switching device M1 is turned on, the gray voltage Vdata supplied from the VDAC unit 230 is supplied to the data line Dj via the buffer 260j. The gray voltage Vdata supplied to the data line Dj is supplied to the pixel 140 selected by the scan signal as a data signal. The pixel 140 receiving the data signal supplies the pixel current Ipixel corresponding to the data signal to the feedback line Fj.

Thereafter, the control unit 256 turns off the switching element M1 during the feedback period of one horizontal period 1H. When the switching device M1 is turned off, the first node N1 is floated. At this time, the first node N1 maintains the voltage of the gray voltage Vdata by a parasitic capacitor (not shown).

During the feedback period, the comparator 252 receives the gradation current Idata and the pixel current Ipixel supplied from the IDAC unit 240. Here, the gradation current Idata is an ideal current value that should actually flow in the pixel 140 in response to the data, and the pixel current Ipixel is a current value that actually flows in the pixel 140. The comparator 252, which receives the pixel current Ipixel and the gradation current Idata, compares the pixel current Ipixel and the gradation current Idata, and compares the first control signal or the second control signal in response to the comparison result. It generates and supplies to the voltage increase and decrease unit 254.

During the feedback period, the controller 256 supplies a counting signal that is increased from "1" to "j" to the voltage increase / decrease unit 254. The voltage increasing / decreasing unit 254 receiving the counting signal supplies a predetermined voltage value to the first capacitor C1 in response to the first control signal or the second control signal supplied from the comparator 252. Here, the voltage increase / decrease unit 254 may supply a voltage value supplied to the first capacitor C1 so that the gray scale current Idata and the pixel current Ipixel may be the same or similar to the first control signal or the second control signal. To control. Then, the voltage value of the first node N1 is changed corresponding to the voltage value supplied to the first capacitor C1. That is, the gray voltage Vdata applied to the first node N1 is changed in response to the voltage value supplied to the first capacitor C1, and the changed voltage is transferred to the pixel 140 via the buffer 260j. Supplied.

Then, the pixel 140 generates the pixel current Ipixel corresponding to the changed gray voltage Vdata. In practice, the present invention controls the pixel current Ipixel flowing in the pixel 140 to be approximately equal to the gradation current Idata while repeating this process j times during the feedback period.

On the other hand, the voltage range which is increased or decreased in the voltage increase / decrease unit 254 is determined by the counting signal. For example, the voltage increase / decrease unit 254 increases or decreases the voltage within the range of the first voltage V1 as shown in FIG. 7 when the first counting signal (eg, “1”) is supplied. The voltage increasing unit 254 increases or decreases the voltage within the range of the second voltage V2 lower than the first voltage V1 when the second counting signal (eg, “2”) is supplied. Here, the second voltage V2 may be set to about 1/2 of the first voltage V1. The voltage increasing / decreasing unit 254 increases or decreases the voltage within the range of the third voltage V3 lower than the second voltage V2 when the third counting signal (eg, “3”) is supplied. That is, as the counting signal is increased, the voltage range increased or decreased by the voltage increase / decrease unit 254 is lowered. Here, the lowering voltage range may be set to 1/2 of the previous voltage range. In this manner, the voltage increase / decrease unit 254 controls the voltage supplied to the first capacitor C1 so that the gray voltage Idata and the pixel current Ipixel can be the same or similar.

8 is a diagram illustrating a pixel according to a first embodiment of the present invention. In FIG. 8, pixels connected to the m-th data line Dm and the n-th scan line Sn are illustrated for convenience of description.

Referring to FIG. 8, the pixel 140 according to the first embodiment of the present invention includes a first switching block 141 connected to the light emitting device OLED, the nth scan line Sn, and the mth data line Dm. ), A pixel circuit 143 for supplying a pixel current Ipixel corresponding to the grayscale voltage Vdata (data signal) supplied from the m-th data line Dm to the light emitting element OLED, and a pixel circuit 143. And a second switching block 142 for supplying the pixel current Ipixel from X) to the data driver 120 via the mth feedback line Fm.

The first switching block 141 supplies the data signal supplied from the mth data line Dm to the pixel circuit 143 in response to the scan signal supplied from the nth scan line Sn. To this end, the first switching block 141 includes at least one transistor.

The second switching block 142 supplies the pixel current Ipixel from the pixel circuit 143 to the mth feedback line Fm in response to the scan signal supplied from the nth scan line Sn. Here, the pixel current Ipixel supplied to the mth feedback line Fm is supplied to the data driver 120.

The pixel circuit 143 receives the gray voltage Vdata from the mth data line Dm via the first switching block 141. The pixel circuit 143 supplied with the gray voltage Vdata supplies the pixel current Ipixel corresponding to the gray voltage Vdata to the second switching block 142 or the light emitting device OLED. In the present invention, the configuration of the pixel circuit 143 may be used as any one of various circuits currently known.

FIG. 9 is a circuit diagram illustrating in detail a pixel according to the first embodiment of the present invention shown in FIG. 8.

Referring to FIG. 9, the first switching block 141 includes a first transistor M11. The first electrode of the first transistor M11 is connected to the mth data line Dm, and the gate electrode is connected to the nth scan line Sn. The second electrode of the first transistor M11 is connected to the pixel circuit 143. The first transistor M10 is turned on when the scan signal is supplied to the nth scan line Sn. Meanwhile, the first electrode means any one of the source electrode and the drain electrode, and the second electrode means an electrode different from the first electrode. For example, when the first electrode is set as the source electrode, the second electrode is set as the drain electrode.

The second switching block 142 has a second transistor M12. The first electrode of the second transistor M12 is connected to the pixel circuit 143, and the second electrode is connected to the mth feedback line Fm. The gate electrode of the second transistor M12 is connected to the nth scan line Sn. The second transistor M12 is turned on when the scan signal is supplied to the nth scan line Sn.

The pixel circuit 143 includes a third transistor M13, a fourth transistor M14, and a capacitor C. The gate electrode of the third transistor M13 is connected to the first switching block 141, and the first electrode is connected to the first power source VDD. The second electrode of the third transistor M13 is connected to the first electrode of the fourth transistor M14. The third transistor M13 controls the pixel current Ipixel flowing from the first power supply VDD to the light emitting device OLED in response to the gray voltage Vdata.

The capacitor C is connected between the gate electrode and the first electrode of the third transistor M13. The capacitor C charges a voltage corresponding to the gray voltage Vdata.

The gate electrode of the fourth transistor M14 is connected to the nth scan line Sn, and the second electrode is connected to the light emitting device OLED. The fourth transistor M14 controls the timing at which the pixel current Ipixel is supplied to the light emitting device OLED in response to the scan signal supplied from the nth scan line Sn. Herein, the fourth transistor M14 should be turned on or turned off at a different time from the second transistor M12 so that the stable pixel current Ipixel can be supplied to the data driver 120. For this purpose, the fourth transistor M14 is formed in a different conductivity type from the second transistor M12. For example, when the second transistor M12 is formed of PMOS, the fourth transistor M14 is formed of NMOS.

FIG. 10 is a diagram illustrating a scan signal supplied to the pixel illustrated in FIG. 9.

Referring to FIG. 10, first, a scan signal is supplied to an nth scan line Sn during a specific horizontal period H. When the scan signal is supplied to the nth scan line Sn, the first transistor M11 and the second transistor M12 are turned on, and the fourth transistor M14 is turned off. The switching element M1 shown in FIG. 5 is turned on during the data signal supply period during one horizontal period 1H. Then, the grayscale voltage Vdata is supplied to the gate terminal of the third transistor M13 via the data line D and the first transistor M11 during the data signal supply period.

At this time, the capacitor C is charged with a predetermined voltage corresponding to the difference voltage between the first power source VDD and the gray voltage Vdata. Thereafter, in the feedback period, the third transistor M13 supplies the pixel current Ipixel to the second transistor M12 and the fourth transistor M14 in response to the voltage charged in the capacitor C. FIG. Here, since the second transistor M12 is turned on and the fourth transistor M14 is turned off during the feedback period, the pixel current Ipixel is the mth feedback line Fm via the second transistor M12. Is supplied.

When the pixel current Ipixel is supplied to the feedback line Fm, the data driver 120 increases or decreases the voltage value supplied to the mth data line Dm so that the desired pixel current Ipixel can flow. In fact, the voltage value supplied to the m-th data line Dm during the feedback period is changed at least once so that the desired pixel current Ipixel can flow.

Thereafter, the supply of the scan signal to the nth scan line Sn is stopped in the next horizontal period. Then, the first transistor M11 and the second transistor M12 are turned off, and the fourth transistor M14 is turned on. In this case, the pixel current Ipixel supplied from the third transistor M13 is supplied to the light emitting device OLED via the fourth transistor M14, so that light having a predetermined luminance is emitted from the light emitting device OLED. Is generated. That is, in the present invention, since the voltage supplied to the data line Dm is changed to allow the desired pixel current Ipixel to flow, the light emitting device OLED may generate light having a desired luminance.

11 is a diagram illustrating a pixel according to a second exemplary embodiment of the present invention. In FIG. 11, pixels connected to the m-th data line Dm and the n-th scan line Sn are illustrated for convenience of description.

Referring to FIG. 11, the pixel 140 according to the second exemplary embodiment of the present invention includes a light emitting device OLED, an nth scan line Sn, an nth emission control line En, and an mth data line Dm. A pixel circuit 146 for supplying the first switching block 144 connected to the first switching block 144 and the pixel current Ipixel corresponding to the grayscale voltage Vdata supplied from the m-th data line Dm to the light emitting device OLED. And a second switching block 145 for supplying the pixel current Ipixel from the pixel circuit 146 to the mth feedback line Fm.

The pixel 140 according to the second embodiment of the present invention is further connected to the emission control line En as compared with the pixel according to the first embodiment of the present invention. Here, the emission control line En is used to control the supply time of the pixel current Ipixel supplied to the light emitting element OLED. To this end, the emission control signal supplied to the emission control line En is sequentially supplied to overlap the scan signal. For example, the emission control signal supplied to the nth emission control line En overlaps with the scan signal supplied to the nth scan line Sn. (Actually, the width of the emission control signal is equal to the width of the scan signal. The polarity of the light emission control signal is set opposite to that of the scan signal.

The first switching block 144 corresponds to a scan signal supplied from the nth scan line Sn and a light emission control signal supplied from the nth emission control line En to receive a data signal supplied from the mth data line Dm. Supply to the pixel circuit 143. To this end, the first switching block 141 includes at least one transistor.

The second switching block 145 supplies the pixel current Ipixel from the pixel circuit 146 to the mth feedback line Fm in response to the scan signal supplied from the nth scan line Sn. Here, the pixel current Ipixel supplied to the mth feedback line Fm is supplied to the data driver 120.

The pixel circuit 146 receives the grayscale voltage Vdata from the mth data line Dm via the first switching block 144. The pixel circuit 146 supplied with the gray voltage Vdata supplies the pixel current Ipixel corresponding to the gray voltage Vdata to the second switching block 145 or the light emitting device OLED. Here, when the pixel current Ipixel is supplied to the light emitting device OLED, the light emitting device OLED generates predetermined light corresponding to the pixel current Ipixel. On the other hand, the pixel circuit 146 of the present invention may use various circuits configured to be connected to the emission control line. (A variety of pixel circuits connected to the emission control line are now known).

FIG. 12 is a circuit diagram illustrating a pixel in detail in the second embodiment of the present invention shown in FIG.

Referring to FIG. 12, the first switching block 144 includes a first transistor M11 and a second transistor M12. The first electrode of the first transistor M11 is connected to the mth data line Dm, and the gate electrode is connected to the nth scan line Sn. The second electrode of the first transistor M11 is connected to the first electrode of the second transistor M12. The first transistor M11 is turned on when the scan signal is supplied to supply the gray voltage Vdata to the pixel circuit 146.

The first electrode of the second transistor M12 is connected to the second electrode of the first transistor M11, and the gate electrode is connected to the emission control line En. The second electrode of the second transistor M12 is connected to the pixel circuit 146. Here, the first electrode and the second electrode of the second transistor M12 are electrically connected. Therefore, when the first transistor M11 is turned on, the gray voltage Vdata is supplied to the pixel circuit 146 regardless of the turn-on or turn-off of the second transistor M12. In practice, the second transistor M12 is provided to reduce the switching error of the first transistor M11.

In practice, the first switching block 144 of the present invention may include only the first transistor M11 as shown in FIG. 13. However, when only the first transistor M11 is included in the first switching block 144, the reliability of driving is deteriorated due to a switching error. Therefore, in the present invention, the first switching block 144 further includes a second transistor M12 to minimize the switching error.

The second switching block 145 has a third transistor M13. The first electrode of the third transistor M13 is connected to the pixel circuit 146, and the second electrode is connected to the mth feedback line Fm. The gate electrode of the third transistor M13 is connected to the nth scan line Sn. The third transistor M13 is turned on when the scan signal is supplied to the nth scan line Sn.

The pixel circuit 146 includes a fourth transistor M14, a fifth transistor M15, and a capacitor C. The gate electrode of the fourth transistor M14 is connected to the first switching block 144, and the first electrode is connected to the first power source VDD. The second electrode of the fourth transistor M14 is connected to the first electrode of the fifth transistor M5. The fourth transistor M14 controls the pixel current Ipixel flowing from the first power source VDD to the light emitting device OLED in response to the gray voltage Vdata.

The capacitor C is connected between the gate electrode and the first electrode of the fourth transistor M14. The capacitor C charges a voltage corresponding to the gray voltage Vdata. In fact, the capacitor C is charged with a voltage corresponding to the difference voltage between the gray scale voltage Vdata and the first power supply VDD.

The gate electrode of the fifth transistor M15 is connected to the nth emission control line En, and the second electrode is connected to the light emitting device OLED. The fifth transistor M5 is turned off when the emission control signal is supplied to the nth emission control line En. Otherwise, the fifth transistor M5 is turned on. That is, the fifth transistor M15 controls the time point at which the pixel current Ipixel is supplied to the light emitting device OLED in response to the light emission control signal. In addition, since the fifth transistor M15 is turned on when the emission control signal is not supplied, the time when the fifth transistor M15 is turned on with the third transistor M13 that is turned on when the scan signal is supplied does not overlap.

FIG. 14 is a diagram illustrating a scan signal supplied to the pixel illustrated in FIG. 12.

Referring to FIG. 14, a scan signal is first supplied to an nth scan line Sn during a specific horizontal period. The light emission control signal is supplied to the nth light emission control line En during a specific horizontal period. When the scan signal is supplied to the nth scan line Sn, the first transistor M11 and the third transistor M13 are turned on. When the emission control signal is supplied to the nth emission control line En, the fifth transistor M15 is turned off.

When the first transistor M11 is turned on, the fourth transistor M14 is via the switching element M1, the data line Dm, the first transistor M11, and the second transistor M12 during the data signal supply period. The gradation voltage Vdata is supplied to the gate terminal of. At this time, the capacitor C is charged with a predetermined voltage corresponding to the difference voltage between the first power supply VDD and the gray voltage Vdata. Thereafter, in the feedback period, the fourth transistor M14 supplies the pixel current Ipixel to the third transistor M13 and the fifth transistor M15 in response to the voltage charged in the capacitor C. FIG.

In this case, since the third transistor M13 is turned on by the scan signal and the fifth transistor M15 is turned off by the emission control signal, the pixel current Ipixel passes through the third transistor M13. Is supplied to the feedback line Fm. The pixel current Ipixel supplied to the feedback line Fm is supplied to the data driver 120, and the data driver 120 receives a voltage value supplied to the mth data line Dm in response to the pixel current Ipixel. Increase or decrease Then, the voltage value charged in the capacitor C increases or decreases corresponding to the voltage value supplied to the m-th data line Dm, thereby changing the current value of the pixel current Ipixel. In practice, the voltage value supplied to the mth data line Dm during the feedback period is changed at least once so that the pixel current Ipixel can flow.

Thereafter, the supply of the scan signal to the nth scan line Sn and the emission control signal to the nth emission control line En is stopped. When the supply of the scan signal is stopped, the first transistor M11 and the third transistor M13 are turned off. When the supply of the emission control signal is stopped, the fifth transistor M15 is turned on. When the fifth transistor M15 is turned on, the pixel current Ipixel from the fourth transistor M14 is supplied to the light emitting device OLED via the fifth transistor M15. In this case, the light emitting device OLED generates light having a predetermined luminance corresponding to the pixel current Ipixel.

Meanwhile, in the present invention, the first switching block 144 may be configured in various ways. In fact, in the present invention, the first switching block 144 may be configured in various forms to minimize switching errors.

FIG. 15 is a circuit diagram illustrating another configuration of the pixel according to the second embodiment of the present invention shown in FIG. 11. In FIG. 15, the rest of the configuration except for the first switching block 144 is the same as the pixel illustrated in FIG. 12. Therefore, in FIG. 15, the first switching block 144 will be mainly described.

Referring to FIG. 15, the first switching block 144 includes a first transistor M11 and a second transistor M12 connected in the form of a transmission gate. The gate electrode of the first transistor M11 formed in the PMOS conductivity type is connected to the scan line Sn, and the first electrode is connected to the data line Dm. The first electrode of the first transistor M11 is connected to the pixel circuit 146.

The gate electrode of the second transistor M12 formed of the NMOS conductivity type is connected to the emission control line En, and the second electrode is connected to the data line Dm. The first electrode of the second transistor M12 is connected to the pixel circuit 146. The second transistor M2 is turned on when the emission control signal is supplied to supply the gray voltage Vdata to the pixel circuit 146.

That is, the first transistor M11 and the second transistor M12 are turned on at the same time to electrically connect the data line Dm and the pixel circuit 146. Here, when the first transistor M11 and the second transistor M12 are connected in the form of a transmission gate, switching errors can be minimized. In fact, when the first transistor M11 and the second transistor M12 are connected in the form of a transmission gate, the switching error can be minimized since the first transistor M11 and the second transistor M12 are set in a substantially straight shape of the voltage-current characteristic curve.

Meanwhile, in the present invention, the first switching block 144 may further include transistors M111, M112, M121, and M122 connected in the form of a transmission gate as shown in FIG. 16. In practice, the first switching block 144 includes at least one NMOS transistor and a PMOS transistor connected in the form of a transmission gate.

FIG. 17 is a diagram illustrating still another configuration of the pixel according to the second embodiment of the present invention shown in FIG. 11. Subsequently, in the pixel shown in FIG. 17, the transistor of the PMOS shown in FIG. 12 is changed to an NMOS.

Referring to FIG. 17, the first switching block 144 includes a first transistor M11 and a second transistor M12 of NMOS. The first transistor M11 is turned on when the scan signal is supplied to the scan line Sn. Here, the scan signal supplied to the scan line Sn has a positive potential as shown in FIG. 18 so that the first transistor M11 of the NMOS conductivity type can be turned on.

The second transistor M12 is turned off when the emission control signal is supplied to the emission control line En. For this purpose, the light emission control signal supplied to the light emission control line En has a negative potential. On the other hand, since the first electrode and the second electrode of the second transistor M12 are electrically connected to each other, the pixel circuit (if the first transistor M11 is turned on regardless of whether the second transistor M12 is turned on). 146 and data line D are electrically connected. The second transistor M12 is included in the first switching block 144 to reduce the switching error.

The second switching block 145 includes a third transistor M13 formed of NMOS. The third transistor M3 supplies the pixel current Ipixel supplied from the pixel circuit 146 to the feedback line Fm when the scan signal is supplied from the scan line Sn.

The pixel circuit 146 includes a fourth transistor M14, a fifth transistor M15, and a capacitor C. The fourth transistor M14 is turned off when the light emission control signal is supplied, and is turned on in other cases. The fifth transistor M15 controls the predetermined pixel current IPixel to flow corresponding to the gray voltage Vdata.

The capacitor C is connected between the gate electrode and the first electrode of the fourth transistor M14. The capacitor C charges a voltage corresponding to the gray voltage Vdata.

FIG. 18 is a diagram illustrating a scan signal supplied to the pixel illustrated in FIG. 17.

Referring to FIG. 18, a scan signal is first supplied to an nth scan line Sn during a specific horizontal period. The light emission control signal is supplied to the nth light emission control line En during a specific horizontal period. When the scan signal is supplied to the nth scan line Sn, the first transistor M11 and the third transistor M13 are turned on. When the emission control signal is supplied to the nth emission control line En, the fourth transistor M14 is turned off.

When the first transistor M11 is turned on, the fifth transistor M15 via the switching element M1, the data line Dm, the first transistor M11, and the second transistor M12 during the data signal supply period. The gradation voltage Vdata is supplied to the gate terminal of. At this time, the capacitor C is charged with a voltage corresponding to the gray scale voltage Vdata.

Thereafter, in the feedback period, the fifth transistor M15 sinks a predetermined pixel current in response to the voltage charged in the capacitor C. Then, the pixel current Ipixel is supplied to the second power source VSS from the comparison unit 252 shown in FIG. 5 via the feedback line Fm. At this time, the comparison unit 252 compares the pixel current Ipixel and the gradation current Idata, and supplies the comparison result to the voltage increase / decrease unit 254.

The voltage increase / decrease unit 254 increases or decreases the voltage of the data line Dm in response to the comparison result from the comparison unit. Then, the charging voltage of the capacitor C is also increased or decreased corresponding to the voltage supplied from the data line Dm, and thus the current value of the pixel current Ipixel is also converted. In practice, the voltage value supplied to the mth data line Dm during the feedback period is changed at least once so that the pixel current Ipixel can flow.

Thereafter, the supply of the scan signal to the nth scan line Sn and the emission control signal to the nth emission control line En is stopped. When the supply of the scan signal is stopped, the first transistor M11 and the third transistor M13 are turned off. When the supply of the emission control signal is stopped, the fourth transistor M14 is turned on. When the fourth transistor M14 is turned on, a current path leading to the first power source VDD, the light emitting device OLED, the fourth transistor M14, the fifth transistor M5, and the second power source VSS is generated. Is formed. Then, the pixel current Ipixel flows through the light emitting element OLED, and thus light of a predetermined luminance corresponding to the pixel current Ipixel is generated in the light emitting element OLED.

Meanwhile, in the present invention, transistors included in the pixel circuits 143 and 146 and the second switching block 145 of FIGS. 9 to 16 may be changed to NMOS transistors as shown in FIG. 17. In this case, the polarity of the driving signal is reversed to drive the NMOS transistors.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the data integrated circuit and the light emitting display device using the same according to the embodiment of the present invention, the gradation current corresponding to the data and the pixel current flowing in the pixel are compared, and the pixel current corresponds to the gradation current in response to the comparison result. By changing the gradation voltage (data signal) so as to change to a current value similar to, it is possible to display an image of desired luminance. In particular, in the present invention, since the gradation voltage is changed by feeding back pixel current from each pixel, an image having a desired luminance can be displayed regardless of non-uniformity of transistors included in each pixel. In the present invention, the pixel current can be stably supplied to the data driver by adding a switching block connected to the feedback line to each pixel.

Claims (18)

A shift register unit for sequentially generating sampling signals; A latch unit for storing data supplied from the outside in response to the sampling signal; A voltage digital-to-analog converter for generating a gray scale voltage corresponding to the data stored in the latch unit; A current digital-analog converter configured to generate a gradation current corresponding to the data stored in the latch unit; A buffer unit for supplying the gray voltage to the pixels as a data signal; The pixel current flowing through the pixels in response to the gray voltage is fed back, the pixel current is compared with the gray current, and the voltage supplied to the pixels through the buffer unit is increased or decreased in response to the comparison result. A data integrated circuit comprising a voltage adjusting block. delete The method of claim 1, The latch portion A sampling latch unit for sequentially storing the data corresponding to the sampling signal; And a holding latch unit for storing the data stored in the sampling latch unit and simultaneously supplying the stored data to the voltage digital-analog converter and the current digital-analog converter. The method of claim 3, And a level shifter unit for raising the voltage level of the data stored in the holding latch unit to supply the voltage digital-analog converter and the current digital-analog converter. The method of claim 1, The voltage adjusting block includes j voltage adjusting units for controlling j (j is a natural number) gray voltages. The method of claim 5, Each of the voltage adjustor A switching element disposed between the voltage digital-analog converter and the buffer unit; A comparator for comparing the pixel current with the gradation current; A capacitor having one side terminal connected to the common terminal of the switching element and the buffer unit; A voltage increasing / decreasing unit connected to the other terminal of the capacitor and increasing / decreasing a voltage supplied to the other terminal of the capacitor by the control of the comparing unit; And a control unit for controlling the switching element. The method of claim 6, And the control unit turns on the switching element for a first period of one horizontal period, and turns off the switching element for a second period except the first period. The method of claim 7, wherein And the gray voltage is supplied to the pixels during the first period, and the pixel current is supplied to the comparison unit during the second period. The method of claim 8, And the comparing unit generates a first control signal when the gradation current is greater than the pixel current, and generates a second control signal when the gradation current is smaller than the pixel current. The method of claim 9, And the voltage increasing / decreasing unit controls a voltage supplied to the capacitor so that the voltage of the common terminal is lowered when the first control signal is supplied. The method of claim 9, And the voltage increase and decrease unit controls a voltage supplied to the capacitor so that the voltage of the common terminal is increased when the second control signal is supplied. The method of claim 7, wherein And the control unit supplies a counting signal gradually increasing during the second period to the voltage increase / decrease unit. The method of claim 12, And a voltage range of the voltage increasing / decreasing part is determined in correspondence to the counting signal. The method of claim 13, And as the counting signal increases, the voltage range of the voltage increasing / decreasing unit decreases. The method of claim 14, And a voltage range of the voltage increasing / decreasing unit decreases by 1/2 every time the counting signal is increased. The method of claim 12, And the control unit receives a reset signal every one horizontal period and initializes the counting signal. The method of claim 16, And the reset signal is set to any one of a horizontal synchronization signal and a scanning signal supplied to the pixels every horizontal period. Scan lines; Data lines and feedback lines formed in a direction crossing the scan lines; An image display unit including a plurality of pixels connected to the scan lines, data lines, and feedback lines; A scan driver for sequentially supplying scan signals to the scan lines; A data driver connected to the data lines and feedback lines to supply a gray voltage to the data lines as a data signal; 18. A light emitting display device comprising: the data driver comprises the data integrated circuit according to any one of claims 1 and 3 to 17.

Images