KR100629577B1 - Buffer and light emitting display with integrated circuit using the same - Google Patents

Abstract

The present invention relates to a buffer capable of supplying an accurate output voltage regardless of the threshold voltage of a transistor.

The buffer of the present invention includes a first capacitor supplied with a gray voltage to one terminal, a first inverter connected with an input terminal to the other terminal of the first capacitor, and a first terminal connected with an output terminal of the first inverter. A second capacitor, a second inverter having an input terminal connected to the other terminal of the second capacitor, a third capacitor having one side connected to an output terminal of the second inverter, and a third terminal connected to the other terminal of the third capacitor. A first transistor for controlling a current supplied from the first power supply to the data line so that a predetermined voltage is supplied to the data line in response to the voltage supplied from the third capacitor, and between the data line and one terminal of the first capacitor. A second transistor connected to the third transistor; a third transistor connected between the first inverter and the first power source; and between the second inverter and the second power source. And a fourth transistor connected.

By such a configuration, the present invention can supply an accurate gray scale voltage regardless of the threshold voltages of the transistors.

Description

Buffer and Light Emitting Display With integrated Circuit Using the same}

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the data integrated circuit shown in FIG. 1.

3 is a block diagram illustrating another embodiment of the data integrated circuit shown in FIG. 1.

4 is a circuit diagram showing in detail the structure of a buffer according to an embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating control signals supplied to the buffer illustrated in FIG. 4.

6 is a diagram illustrating a voltage value applied to nodes of the buffer illustrated in FIG. 4.

7A to 7C are waveform diagrams illustrating another embodiment of control signals supplied to the buffer illustrated in FIG. 4.

<Explanation of symbols for the main parts of the drawings>

110: scan driver 120: data driver

121: shift register section 122: sampling latch section

123: holding latch portion 124: level shifter portion

125: DAC unit 126: buffer unit

127: buffer 127a, 127b: inverter

129: data integrated circuit 130: image display unit

140: pixel 150: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer, a data integrated circuit and a light emitting display device using the same, and more particularly, to a buffer and a data integrated circuit and a light emitting display device using the same, capable of supplying an accurate output voltage regardless of a threshold voltage of a transistor.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device uses a transistor formed for each pixel to supply a current corresponding to a data signal to the light emitting device to emit light from the light emitting device.

Such a light emitting display generates a data signal using data supplied from the outside and displays the image having a desired luminance by supplying the generated data signal to the pixels using the data lines. Here, at least one data integrated circuit is used to convert data supplied from the outside into a data signal.

The data integrated circuit converts data supplied from the outside into a voltage corresponding to the gray scale value, and supplies the converted voltage as data signals to the data lines via the buffer. Then, a predetermined image is displayed by supplying a current corresponding to the voltage value of the data signal from each of the pixels to the light emitting element.

In such a data integrated circuit, the buffer must supply the data signal supplied thereto to the data lines without voltage drop. However, the conventional buffer composed of a plurality of transistors supplies a data signal having a voltage drop by a voltage corresponding to the threshold voltage of the transistor to the data line. That is, in the conventional buffer, the voltage of the data signal is lowered by the threshold voltage of the transistor, thereby causing a problem in that an image of a desired luminance cannot be displayed in the pixels.

Accordingly, it is an object of the present invention to provide a buffer, a data integrated circuit and a light emitting display device using the same, which can supply an accurate output voltage regardless of a threshold voltage of a transistor.

In order to achieve the above object, the first side of the present invention is a first capacitor to receive a gradation voltage supplied to one side terminal, a first inverter to which the input terminal is connected to the other terminal of the first capacitor, one side of the first terminal A second capacitor connected to an output terminal of the one inverter, a second inverter connected to an input terminal of the other terminal of the second capacitor, a third capacitor connected to one output terminal of the output terminal of the second inverter, and A first transistor connected to the other terminal of the third capacitor and controlling a current supplied from the first power supply to the data line such that a predetermined voltage is supplied to the data line corresponding to the voltage supplied from the third capacitor; A second transistor connected between a line and one terminal of the first capacitor, a third transistor connected between the first inverter and the first power supply; And a fourth transistor connected between the second inverter and the second power source.

Preferably, the voltage value of the predetermined voltage is set to the same voltage value as the gradation voltage. When the voltage value of the predetermined voltage is supplied to the data line, the first transistor is turned off. The absolute value of the voltage supplied from the third capacitor to the first transistor is set higher than the gradation voltage.

Hereinafter, preferred embodiments of the present invention may be easily implemented by those skilled in the art with reference to FIGS. 1 to 7C as follows.

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes an image display unit 130 including pixels 140 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm. And the scan driver 110 for driving the scan lines S1 to Sn, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. A timing controller 150 for controlling is provided.

The scan driver 110 generates a scan signal in response to the scan drive control signal SCS from the timing controller 150, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 110 generates an emission control signal in response to the scan driving control signal SCS, and sequentially supplies the generated emission control signal to the emission control lines E1 to En.

The data driver 120 generates data signals in response to the data driving control signal DCS from the timing controller 150, and supplies the generated data signals to the data lines D1 to Dm. To this end, the data driver 120 includes at least one data integrated circuit 129.

The data integrated circuit 129 converts data supplied from the outside into a data signal and supplies the data to the data lines D1 to Dm. Here, the data integrated circuit 129 supplies a predetermined voltage to the data lines D1 to Dm as data signals. The detailed configuration of the data integrated circuit 129 will be described later.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 rearranges the data Data supplied from the outside and supplies the data to the data driver 120.

The image display unit 130 receives the first power source ELVDD and the second power source ELVSS from the outside. The first power source ELVDD and the second power source ELVSS supplied to the image display unit 130 are supplied to the respective pixels 140. The pixels 140 supplied with the first power source ELVDD and the second power source ELVSS display an image corresponding to the data signal supplied from the data integrated circuit 129.

FIG. 2 is a block diagram schematically illustrating the data integrated circuit shown in FIG. 1. Here, it is assumed that the data integrated circuit is composed of j channels so that the data integrated circuit can be connected to j (j is a natural number) data lines.

Referring to FIG. 2, the data integrated circuit 129 according to an exemplary embodiment of the present invention stores a shift register 121 for sequentially generating a sampling signal and sequentially stores data in response to the sampling signal. The sampling latch unit 122 and the data of the sampling latch unit 122 are temporarily stored, and the stored data are transferred to the digital-to-analog converter (hereinafter, referred to as a "DAC unit") 125. Supplying a holding latch unit 123 for supplying, a DAC unit 125 for generating a gradation voltage corresponding to a gradation value (or bit value) of data Data, and a gradation voltage to the data lines D. A buffer unit 126 is provided.

The shift register unit 121 receives the source shift clock SSC and the source start pulse SSP from the timing controller 150. The shift register unit 121 supplied with the source shift clock SSC and the source start pulse SSP sequentially generates j sampling signals while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 121 includes j shift registers.

The sampling latch unit 122 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 121. Here, the sampling latch unit 122 includes j sampling latches to store j data. Each of the sampling latches has a size corresponding to the number of bits of data. For example, when the data are k bits, each of the sampling latches is set to a size of k bits.

The holding latch unit 123 receives data from the sampling latch unit 122 and stores the data when the source output enable signal SOE is input from the timing controller 150. In addition, the holding latch unit 123 supplies the data Data stored therein to the DAC unit 125 when the source output enable signal SOE is input from the timing controller 150. To this end, the holding latch unit 123 includes j holding latches having a size of k bits.

The DAC unit 125 generates a gray voltage corresponding to the bit value (that is, the gray value) of the data Data, and supplies the generated gray voltage to the buffer unit 126.

The buffer unit 126 supplies data signals supplied from the DAC unit 125 to j data lines D1 to Dj. To this end, the buffer unit 126 includes j buffers 127. Each of the j buffers 127 supplies a data signal (ie, a gradation voltage) supplied thereto to the data lines D1 to Dj. Here, the buffers 127 supply a data signal without a voltage drop to the data lines D1 to Dj regardless of the threshold voltage of the transistor included therein.

Meanwhile, the present invention may further include a level shifter unit 124 between the holding latch unit 123 and the DAC unit 125 as shown in FIG. 3. The level shifter unit 124 increases the voltage level of data Data supplied from the holding latch unit 123 and supplies it to the DAC unit 125. Supplying data having a high voltage level from an external system to the data integrated circuit 129 increases manufacturing costs because circuit components having high breakdown voltages must be installed. Therefore, data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level shifter 124 to a high voltage level.

4 is a diagram illustrating a buffer according to an embodiment of the present invention. 5 is a waveform diagram showing a driving waveform supplied to the buffer shown in FIG. Hereinafter, for convenience of description, it is assumed that the buffer shown in FIG. 4 is a buffer 127 connected to the j-th data line Dj.

4 and 5, the buffer 127 of the present invention includes a first inverter 127a and a second inverter 127b, and a first connected between the data line Dj and the third power source VVdd. The fifth transistor M5 and the first capacitor C1, the first capacitor C1, and the fifth transistor M5 connected between the transistor M1, the DAC unit 125, and the first inverter 127a. The second transistor M2 connected between the first node N1 and the data line Dj, which are common terminals, and the second capacitor C2 connected between the first inverter 127a and the second inverter 127b. ), A third capacitor C3 connected between the second inverter 127b and the first transistor M1, and a third transistor M3 connected between the first inverter 127a and the third power supply VVDD. ) And a fourth transistor M4 connected between the second inverter 127b and the fourth power source VVSS.

The buffer 127 of the present invention is a sixth transistor M6 connected between the sixth node N6 and the third power source VVdd, which are common terminals of the third capacitor C3 and the first transistor M1. And the seventh transistor M7 connected between the seventh node N7 and the fourth power source VVss, which are common terminals of the first transistor M1 and the data line Dj, and the first inverter 127a. An eighth transistor M8 connected between the input terminal N2 and the output terminal N3, and a ninth transistor M9 connected between the input terminal N4 and the output terminal N5 of the second inverter 127b. ).

The first transistor M1 controls the current flowing from the third power source VVdd to the seventh node N7 in response to the voltage value applied to the sixth node N6. At this time, the first transistor M1 supplies current until the voltage value of the seventh node N7 is increased to the gray voltage Vga. The gray voltage Vga supplied to the seventh node N7 is supplied to the pixel 140 as a data signal.

The fifth transistor M5 supplies the gray voltage Vga supplied from the DAC unit 125 to the first node N1 when the first control signal CS1 is supplied.

The second transistor M2 is turned on when the third control signal CS3 is supplied. When the second transistor M2 is turned on, the seventh node N7 and the first node N1 are electrically connected to each other. In fact, when the second transistor M2 is turned on, the output terminal (ie, the seventh node) voltage of the buffer 127 is fed back to the input terminal (ie, the first node) of the buffer 127.

The third transistor M3 is turned on when the fourth control signal CS4 is supplied. When the third transistor M3 is turned on, the voltage of the third power source VVdd is supplied to the first inverter 127a to drive the first inverter 127a. Here, the fourth control signal CS4 is supplied only when the first inverter 127a is driven so that power consumption can be reduced.

The fourth transistor M4 is turned on when the fifth control signal CS5 is supplied. When the fourth transistor M4 is turned on, the voltage of the fourth power source VVss is supplied to the second inverter 127b to drive the second inverter 127b. Here, the fifth control signal CS5 is supplied only when the second inverter 127b is driven so that power consumption can be reduced.

On the other hand, the voltage value of the third power source VVdd is set higher than the voltage value of the fourth power source VVss. Therefore, the third transistor M3 connected to the third power source VVdd is composed of P-MOS, and the fourth transistor M3 connected to the fourth power source VVss is composed of N-MOS. In this case, as is widely known to those skilled in the art, the fourth control signal CS4 for turning on the third transistor M3 and the fifth control signal CS5 for turning on the fourth transistor M4 are turned on. Are set to opposite polarities.

The sixth transistor M6 is turned on when the first control signal CS1 is supplied to supply the voltage of the third power source VVdd to the sixth node N6. When the voltage of the third power source VVdd is supplied to the sixth node N6, the voltages of the gate electrode and the first electrode of the first transistor M1 are set to be the same, and the first transistor M1 is turned off. Here, the first electrode is set to any one of the source electrode and the drain electrode.

The seventh transistor M7 is turned on when the second control signal CS2 is supplied to supply the voltage of the fourth power source VVss to the seventh node N7 (that is, the data line Dj).

The first inverter 127a includes a tenth transistor M10 and an eleventh transistor M11 that are set to different conductivity types and are connected between the third power source VVdd and the fourth power source VVss. Here, the tenth transistor M10 is set to P-MOS, and the eleventh transistor M11 is set to N-MOS. The gate terminals of the tenth transistor M10 and the eleventh transistor M11 are connected to the first capacitor C1 (that is, the second node) and are driven in response to the voltage supplied from the first capacitor C1. .

The eighth transistor M8 is provided between the second node N2, which is an input terminal of the first inverter 127a, and the third node N3, which is an output terminal. The eighth transistor M8 is turned on when the first control signal CS1 is supplied to electrically connect the second node N2 and the third node N3.

The second inverter 127b includes a twelfth transistor M12 and a thirteenth transistor M13 that are set to different conductivity types and are connected between the third power source VVdd and the fourth power source VVss. Here, the twelfth transistor M12 is set to P-MOS, and the thirteenth transistor M13 is set to N-MOS. The gate terminals of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the second capacitor C2 (that is, the fourth node) and are driven in response to the voltage supplied from the second capacitor C2. .

The ninth transistor M9 is provided between the fourth node N4, which is an input terminal of the second inverter 127b, and the fifth node N5, which is an output terminal. The ninth transistor M9 is turned on when the first control signal CS1 is supplied to electrically connect the fourth node N4 and the fifth node N5.

The operation of the buffer 127 according to the first embodiment of the present invention will be described in detail with reference to FIG. 5. For convenience of explanation, it is assumed that the voltage value of the fourth power source VVss is a base potential, and the voltage value of the third power source VVdd is higher than the voltage value of the fourth power source VVss.

The first control signal CS1, the second control signal CS2, the fourth control signal CS4, and the fifth control signal CS5 are supplied during the first period T1. Here, the first control signal CS1 and the fourth control signal CS4 supplied to the PMOS transistor and the second control signal CS2 and the fifth control signal CS5 supplied to the NMOS transistor have opposite polarities. Is set.

When the fourth control signal CS4 is supplied, the third transistor M3 is turned on. When the third transistor M3 is turned on, the first inverter 127a and the third power source VVdd are electrically connected to each other. Then, the first inverter 127a is set to the driveable state.

When the fifth control signal CS5 is supplied, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the second inverter 127b and the fourth power source VVss are electrically connected to each other. Then, the second inverter 127b is set to the driveable state.

When the first control signal CS1 is supplied, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the sixth transistor M6 are turned on. When the second control signal CS2 is supplied, the seventh transistor M5 is turned on.

When the eighth transistor M8 is turned on, the input terminal and the output terminal of the second node N2 and the third node N3, that is, the first inverter 127a are electrically connected to each other. Then, a voltage VVdd / 2 corresponding to approximately half of the third power source VVdd is applied to the second node N2 and the third node N3. Similarly, when the ninth transistor M9 is turned on, the input terminal and the output terminal of the second inverter 127b are electrically connected to each other to the fourth node N4 and the fifth node N5. A voltage VVdd / 2 corresponding to about half is applied.

When the fifth transistor M5 is turned on, the gray voltage Vga supplied from the DAC unit 125 is applied to the first node N1. Then, the first capacitor C1 is charged with a voltage corresponding to the difference between the gray voltage Vga and the voltage applied to the second node N2 (about 1 / 2VVdd). Since the voltage applied to the second node N2 is always constant, the voltage value charged in the first capacitor C1 is determined by the gray voltage Vga.

When the sixth transistor M6 is turned on, the voltage of the third power source VVdd is supplied to the sixth node N6. When the voltage of the third power source VVdd is supplied to the sixth node N6, the first transistor M1 is turned off. The third capacitor C3 charges a voltage corresponding to the difference between the voltage applied to the fifth node N5 and the voltage applied to the sixth node N6.

In the second period T2 subsequent to the first period T1, the supply of the first control signal CS1 is stopped. Then, in the second period T2, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the sixth transistor M6 are turned off.

The third control signal CS3 is supplied in the third period T3 following the second period T2. When the third control signal CS3 is supplied, the second transistor M2 is turned on. When the second transistor M2 is turned on, the seventh node N7 and the first node N1 are electrically connected to each other. Here, the potential of the seventh node N7 is set to the ground potential because the seventh transistor M7 remains turned on for the third period T3. Therefore, the potential of the first node N1 drops to the voltage value of the fourth power source VVss during the third period T3.

When the potential of the first node N1 falls, the potential of the second node N2 connected to the first node N1 also drops by the first capacitor C1. For example, the voltage of the second node N2 is lowered by the absolute first voltage V1 as shown in FIG. 6. Here, the voltage drop width of the second node N2 is determined by the gray voltage Vga. In other words, if the voltage of the gray voltage Vga is set high, the voltage drop width of the second node N2 is set large, and if the voltage of the gray voltage Vga is set low, the voltage drop width of the second node N2 is set. Is set low.

The voltage of the second node N1 is supplied to the first inverter 127a. At this time, since the voltage of the second node N2 is decreased, the tenth transistor M10 included in the first inverter 127a is turned on. When the tenth transistor M10 is turned on, the voltage of the third node N3 is increased. When the voltage of the third node N3 is increased, the voltage of the fourth node N4 connected to the third node N3 by the second capacitor C2 is also increased. For example, the voltage of the fourth node N4 is increased by the absolute second voltage V2 as shown in FIG. 6. Here, the voltage value of the absolute second voltage V2 is set to a voltage higher than the voltage value of the absolute first voltage V1.

The voltage of the fourth node N4 is supplied to the second inverter 127b. At this time, since the voltage of the fourth node N4 is increased, the thirteenth transistor M13 included in the second inverter 127b is turned on. When the thirteenth transistor M13 is turned on, the voltage of the fifth node N5 is decreased. When the voltage of the fifth node N5 drops, the voltage of the sixth node N6 connected to the fifth node N5 also drops through the third capacitor C3. For example, the voltage of the sixth node N6 is lowered by the absolute third power supply V3 as shown in FIG. 6. Here, the voltage value of the absolute value third voltage V3 is set to a voltage higher than the voltage value of the absolute value second voltage V2.

When the voltage of the sixth node N6 drops, the first transistor M1 formed of the P-MOS type is turned on. When the first transistor M1 is turned on, a predetermined current is supplied from the third power source VVdd to the seventh node N7. Meanwhile, since the seventh transistor M7 is turned on by the second control signal CS2 during the third period T3, the voltage of the seventh node N7 maintains the voltage of the fourth power source VVss. do. Therefore, even when the third control signal CS3 is supplied during the third period T3 and the second transistor M2 is turned on, the first node N1 is set to the voltage of the fourth power source VVss.

Thereafter, the supply of the second control signal CS2 is interrupted during the fourth period T4 to turn off the seventh transistor M7. When the seventh transistor M7 is turned off, the voltage value of the seventh node N7 is increased by the current supplied from the first transistor M1. Here, since the absolute third voltage V3 higher than the gray voltage Vga is applied to the sixth node N6, a large amount of current is supplied to the seventh node N7, and accordingly, the seventh node N7. The potential of is raised to the gradation voltage Vga in a short time.

The gray voltage Vga applied to the seventh node N7 is supplied to the pixels 140 via the data line Dj. Then, the pixels 140 generate predetermined light corresponding to the gray voltage Vga. Meanwhile, when the gray voltage Vga is applied to the seventh node N7, the first transistor M1 is turned off. Accordingly, in the present invention, the accurate gray voltage Vga can be supplied to the data line Dj.

In detail, the gray voltage Vga applied to the seventh node N7 is supplied to the first node N1 via the second transistor M2. When the gray voltage Vga is supplied to the first node N1, the driving conditions of the first transistor M1 are set to be the same as the first period T1. In other words, the gradation voltage Vga is supplied to the first node N1 even during the first period T1, and the first transistor M1 is set to the turn-off state during the first period T1. . Therefore, when the gray voltage Vga is supplied to the first node N1 during the fourth period, the first transistor M1 is turned off.

In fact, when the voltage of the first node N1 rises to the gray voltage Vga, the voltage of the second node N2 also rises corresponding to the gray voltage Vga. When the voltage of the second node N2 is increased, the voltage of the third node N3 is decreased by the first inverter 127a. When the voltage of the third node N3 drops, the voltage of the fourth node N4 also decreases by the second capacitor C2. When the low voltage of the fourth node N4 drops, the voltage of the fifth node N5 is increased by the second inverter 127b. When the voltage of the fifth node N5 is increased, the voltage of the sixth node N6 is increased by the third capacitor C3. When the voltage of the sixth node N6 is increased, the first transistor M1 formed of the P-MOS type is turned off.

That is, in the present invention, when the gray voltage Vga is applied to the seventh node N7, that is, the data line Dj, the first transistor M1 is turned off. Therefore, in the present invention, an accurate gray scale voltage can be supplied to the data line Dj regardless of the threshold voltages of the transistors. In the present invention, since the absolute voltage higher than the gray voltage Vga is supplied to the gate terminal of the first transistor M1, the driving speed can be improved. In addition, since the buffer of the present invention can supply the gray scale voltage (Vga) irrespective of the threshold voltage, it can be implemented in a large area and high resolution panel.

In the present invention, the fourth control signal CS4 and the fifth control signal CS5 are supplied to overlap with the first control signal CS1 to the third control signal CS3. Then, since the power supply VVDD or VVss is supplied only when the first inverter 127a and the second inverter 127b are driven, power consumption can be reduced. In practice, the fourth control signal CS4 and the fifth control signal CS5 may be supplied in various forms so as to overlap the first control signal CS1 to the third control signal CS3 as shown in FIGS. 7A and 7B. .

In addition, in the present invention, the turn-on voltage V10 of the fourth control signal CS4 may be a full turn-on voltage and a voltage that may be turned on by the third transistor M3. It can be set to any one of (Weakly Turn-on Voltage). Here, the first inverter 127a is stably driven even if the turn-on voltage V10 of the fourth control signal CS4 is set to the weekly turn-on voltage. Similarly, in the present invention, the second inverter 127b is driven by supplying the turn-on voltage V10 of the fifth control signal CS5 to the full turn-on voltage or the weekly turn-on voltage.

In addition, when the fourth control signal CS4 and the fifth control signal CS5 are set to the weekly turn-on voltage in the present invention, the fourth control signal CS4 and the fifth control signal CS5 as shown in FIG. 7C. Maintains the weekly turn-on voltage without voltage fluctuations.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, the buffer, the data integrated circuit, and the light emitting display device using the same according to the embodiment of the present invention can supply an accurate gray scale voltage regardless of the threshold voltage of the transistors. In fact, the buffer of the present invention can supply a gray scale voltage irrespective of the threshold voltage, so that a large area and a high resolution panel can be easily driven. In the present invention, power consumption can be reduced because the driving voltage is selectively supplied so that the buffer can operate only when the gray voltage is generated in the buffer.

Claims (15)

A first capacitor supplied with a gray voltage at one terminal, A first inverter having an input terminal connected to the other terminal of the first capacitor, A second capacitor having one terminal connected to an output terminal of the first inverter; A second inverter having an input terminal connected to the other terminal of the second capacitor; A third capacitor having one terminal connected to an output terminal of the second inverter; A first transistor connected to the other terminal of the third capacitor to control a current supplied from the first power supply to the data line such that a predetermined voltage is supplied to the data line in response to the voltage supplied from the third capacitor; A second transistor connected between the data line and one terminal of the first capacitor; A third transistor connected between the first inverter and the first power source, And a fourth transistor connected between the second inverter and the second power supply. The method of claim 1, And a voltage value of the predetermined voltage is set to the same voltage value as the gradation voltage. The method of claim 2, And the first transistor is turned off when the voltage value of the predetermined voltage is supplied to the data line. The method of claim 1, And an absolute value of the voltage supplied from the third capacitor to the first transistor is set higher than the gray scale voltage. The method of claim 1, A fifth transistor connected to one terminal of the first capacitor to supply the gray voltage to the first capacitor when the first control signal is supplied; A sixth transistor connected between the other terminal of the third capacitor and the first power source and turned on when the first control signal is supplied; And a seventh transistor connected between the data line and the second power supply and turned on when a second control signal is supplied. The method of claim 5, And a voltage value of the first power supply is set higher than a voltage value of the second power supply. The method of claim 5, The second transistor is turned on when a third control signal overlapping the second control signal for a period of time is supplied. The method of claim 7, wherein The first control signal has a narrower width than the second control signal and is supplied in synchronization with the second control signal. The method of claim 8, And the first control signal and the third control signal do not overlap each other. The method of claim 9, The third transistor is turned on when the fourth control signal is supplied, and the fourth transistor is turned on when the fifth control signal is supplied, and the fourth control signal and the fifth control signal are controlled by the first control. And a buffer supplied to overlap the signal, the second control signal, and the third control signal. The method of claim 10, The fourth control signal and the fifth control signal include a full turn-on voltage at which the third transistor and the fourth transistor can be turned on completely, and a weekly turn-on of the third and fourth transistors. A buffer set to any one of the turn-on voltages. The method of claim 5, An eighth transistor connected between an input terminal and an output terminal of the first inverter and turned on when the first control signal is supplied; And a ninth transistor connected between an input terminal and an output terminal of the second inverter and turned on when the first control signal is supplied. A digital-analog converter for generating a gray scale voltage corresponding to a bit value of data supplied from the outside A data integrated circuit comprising the buffer according to any one of claims 1 to 12 for supplying the gradation voltage to a data line. The method of claim 13, A shift register section for sequentially generating sampling signals; And a latch unit configured to store the data in response to the sampling signal and to supply the stored data to the digital-analog converter. Data lines and scan lines, A plurality of pixels positioned to be connected to the data lines and the scan lines; A scan driver for supplying a scan signal to the scan lines; A data integrated circuit for supplying a data signal to the data lines; The data integrated circuit includes a buffer according to any one of claims 1 to 12.

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