KR100645696B1 - Pixel and Light Emitting Display Using The Same - Google Patents

Abstract

The present invention relates to a pixel capable of displaying an image of desired luminance.

The pixel of the present invention includes a first power source, a light emitting device that receives a predetermined current from the first power source, a plurality of transistors, and the first power source of the plurality of transistors when a scan signal is supplied to a previous scan line. A second capacitor for primary charging the voltage corresponding to the threshold voltage of the transistor for controlling the amount of current flowing from the light emitting element to the light emitting element and a voltage corresponding to the voltage drop of the first power supply; And a first capacitor for first charging a voltage corresponding to the first data signal, the predetermined voltage supplied to the data line, during the first period, wherein the first capacitor and the second capacitor are each other than the first period. Secondary charging is performed in response to a second data signal which is a predetermined current flowing to the data line for two periods.

Description

Pixel and Light Emitting Display Using The Same}

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating an example of the pixel illustrated in FIG. 2.

4 is a waveform diagram illustrating a method of driving the pixel illustrated in FIG. 3.

FIG. 5 is a block diagram illustrating an example of the data driving circuit shown in FIG. 2.

FIG. 6 is a block diagram illustrating another example of the data driving circuit illustrated in FIG. 2.

FIG. 7 is a diagram illustrating a connection structure of a voltage generator, a current generator, a selector, and pixels illustrated in FIGS. 5 and 6.

8 is a waveform diagram illustrating a selection signal supplied to the switching elements illustrated in FIG. 7.

9 is a diagram illustrating another example of the selection unit illustrated in FIG. 7.

FIG. 10 is a waveform diagram illustrating a selection signal supplied to the switching elements illustrated in FIG. 9.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: pixel portion 40,140: pixel

50,150: timing controller 142: pixel circuit

200: data driving circuit 210: shift register section

220: sampling latch portion 230: holding latch portion

240: voltage digital-analog converter 250: current digital-analog converter

260: buffer unit 270: selection block

280: level shifter

The present invention relates to a pixel and a light emitting display device using the same, and more particularly, to a pixel and a light emitting display device using the same to display an image of a desired brightness.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel displays, a light emitting display displays an image using a light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

1 illustrates a conventional light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes a pixel unit 30 including a plurality of pixels 40 connected to scan lines S1 to Sn and data lines D1 to Dm, and scan lines ( A timing controller for controlling the scan driver 10 for driving S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, and the scan driver 10 and the data driver 20. 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal (a predetermined voltage) and supplies the generated data signal to the data lines D1 to Dm so as to be synchronized with the scan signal.

The pixel unit 30 receives the first power source ELVDD and the second power source ELVSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power source ELVDD and the second power source ELVSS receives a current flowing from the first power source ELVDD to the second power source ELVSS via the light emitting device in response to the data signal. The control generates light corresponding to the data signal.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, conventionally, there is a problem in that an image cannot be generated at a desired luminance due to variations in threshold voltages and electron mobility of transistors included in each of the pixels 40. In order to overcome this problem, the current can be supplied as a data signal. In fact, when current is supplied as the data signal, even if the transistors have non-uniform voltage-current characteristics, a uniform image can be displayed.

However, since the current supplied as the data signal is a fine current, it takes a long time to charge the data line. For example, assuming that the load capacitance of the data line is 30 kW, a few ms time is required to charge the load of the data line with a data signal of several tens of nA to several hundred nA. This is a problem that the charging time is not enough when considering one horizontal period (1H) of several tens of ㎲.

In addition, in order to display a uniform image in a conventional pixel, the voltage of the first power supply ELVDD must be constant regardless of the positions of the pixels 40. In other words, the conventional pixel 40 charges the capacitor with a voltage corresponding to the difference between the data signal and the first power source ELVDD, and supplies a predetermined current to the light emitting device in response to the charged voltage. Therefore, in order to display an image of desired luminance in each of the pixels 40, the voltage value of the first power supply ELVDD must be kept constant. However, since the conventional first power supply ELVDD supplies a predetermined current to the plurality of pixels, a voltage drop occurs, and thus, an image having a desired brightness cannot be displayed. In particular, since the voltage drop voltage of the first power supply ELVDD is set differently according to the positions of the pixels 40, an image of uniform luminance cannot be displayed.

Accordingly, an object of the present invention is to provide a pixel and a light emitting display device using the same to display an image having a desired luminance.

In order to achieve the above object, the first aspect of the present invention provides a first power source, a light emitting device that receives a predetermined current from the first power source, a plurality of transistors, and a scan signal when a scan signal is supplied to a previous scan line. A second capacitor for first charging a voltage corresponding to a threshold voltage of a transistor for controlling an amount of current flowing from the first power source to the light emitting device among a plurality of transistors, and a voltage corresponding to a voltage drop of the first power source; And a first capacitor for first charging a voltage corresponding to the first data signal, which is a predetermined voltage supplied to the data line, during the first period during which the scan signal is currently supplied to the scan line, wherein the first capacitor and the second capacitor are provided. The capacitor is secondly charged in response to a second data signal which is a predetermined current flowing to the data line for a second period except the first period. Provide cattle.

Preferably, a first transistor and a second transistor connected to the data line and turned on when a scan signal is supplied to the current scan line, are connected between a reference power source and a second electrode of the first transistor, and are connected to the previous scan line. A third transistor that is turned on when a scan signal is supplied, a fourth transistor for controlling an amount of current flowing from the first power source to the light emitting element in response to a voltage charged in the first capacitor and the second capacitor; And a fifth transistor connected between the gate electrode and the second electrode of the fourth transistor and turned on when a scan signal is supplied to the previous scan line to connect the fourth transistor in the form of a diode.

A second aspect of the present invention includes a scan driver for sequentially supplying a scan signal to the scan line; At least one of supplying a first data signal of a predetermined voltage to the data lines during a first period of each horizontal period, and controlling a second data signal of a predetermined current to flow through the data lines for a second period except the first period; A data driver having a data driver circuit; A light emitting display device comprising a pixel portion including a plurality of pixels according to any one of claims 1 to 6.

Preferably, the data driving circuit includes a voltage digital-to-analog converter for generating the first data signal in response to a gray value of data supplied from the outside, and the second data signal in response to a gray value of the data. A current digital-to-analog converter for generation, connecting the voltage digital-to-analog converter and the data lines for the first period, and connecting the current digital-to-analog converter and the data lines for the second period It has a selection block for.

Hereinafter, preferred embodiments of the present invention may be easily implemented by those skilled in the art with reference to FIGS. 2 to 10 as follows.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

2, a light emitting display device according to an exemplary embodiment of the present invention includes a plurality of pixels 140 connected to scan lines S1 to Sn, light emission control lines E1 to En, and data lines D1 to Dm. ), A scan driver 110 for driving the scan lines S1 to Sn and emission control lines E1 to En, and data for driving the data lines D1 to Dm. The driver 120 and the timing controller 150 for controlling the scan driver 110 and the data driver 120 are provided.

The pixel unit 130 includes pixels 140 formed in regions partitioned by the scan lines S1 to Sn, the emission control lines E1 to En, and the data lines D1 to Dm. The pixels 140 receive a first power source ELVDD, a second power source ELVSS, and a reference power source Vref from the outside. Each of the pixels 140 supplied with the reference power supply Vref compensates for the voltage drop of the first power supply ELVDD by using a difference value between the reference power supply Vref and the first power supply ELVDD. Each of the pixels 140 supplies a predetermined current from the first power supply ELVDD to the second power supply ELVSS via a light emitting device (not shown) in response to the data signal. To this end, each of the pixels 140 is configured as shown in FIG. 3. The detailed structure of the pixel 140 shown in FIG. 3 will be described later.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives a scan driving control signal SCS. The scan driver 110 supplied with the scan driving control signal SCS sequentially supplies the scan signals to the scan lines S1 to Sn. The scan driver 110 supplied with the scan driving control signal SCS sequentially supplies the emission control signal to the emission control lines E1 to En. Here, the light emission control signal is supplied to overlap the two scanning signals. To this end, the width of the emission control signal is set equal to or wider than the width of the scan signal.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm. Here, the data driver 120 supplies a voltage (hereinafter referred to as a "voltage data signal") as a data signal (first data signal) for a predetermined period of one horizontal period (1H), and the data signal (for A current (hereinafter, referred to as a "current data signal") is supplied from the pixel 140 as a second data signal. (Current Sink) For this purpose, the data driver 120 includes at least one data driver circuit. 200. The detailed configuration of the data driving circuit 200 will be described later.

3 is a circuit diagram illustrating an example of the pixel illustrated in FIG. 2. In FIG. 3, pixels connected to the m-th data line Dm, the n-th and n-th scan lines Sn-1 and Sn, and the n-th emission control line En are shown for convenience of description.

Referring to FIG. 3, the pixel 140 of the present invention includes a light emitting device OLED and a pixel circuit 142 for supplying current to the light emitting device OLED.

The light emitting device OLED generates light of a predetermined color in response to a current supplied from the pixel circuit 142. To this end, the light emitting device OLED is formed of an organic material, a phosphor, and / or an inorganic material.

The pixel circuit 142 compensates the voltage drop of the first power supply ELVDD and the threshold voltage of the fourth transistor M4 when the scan signal is supplied to the n-1 scan line Sn-1 (previous scan line). When the scan signal is supplied to the n scan line Sn (the current scan line), the voltage corresponding to the data signal is charged. To this end, the pixel circuit 142 includes first to sixth transistors M6, a first capacitor C1, and a second capacitor C2.

The first electrode of the first transistor M1 is connected to the data line Dm, and the second electrode is connected to the first node N1. The gate electrode of the first transistor M1 is connected to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the first transistor M1 is turned on to electrically connect the data line Dm and the first node N1.

The first electrode of the second transistor M2 is connected to the data line Dm, and the second electrode is connected to the second electrode of the fourth transistor M4. The gate electrode of the second transistor M2 is connected to the nth scan line Sn. The second transistor M2 is turned on when a scan signal is supplied to the nth scan line Sn to electrically connect the data line Dm and the second electrode of the fourth transistor M4.

The first electrode of the third transistor M3 is connected to the reference power supply Vref, and the second electrode is connected to the first node N1. The gate electrode of the third transistor M3 is connected to the n-1 th scan line Sn-1. The third transistor M3 is turned on when the scan signal is supplied to the n-1 th scan line Sn-1 to electrically connect the reference power supply Vref and the first node N1.

The first electrode of the fourth transistor M4 is connected to the third node N3 (that is, the first power source ELVDD), and the second electrode is connected to the first electrode of the sixth transistor M6. The gate electrode of the fourth transistor M4 is connected to the second node N2. As such, the fourth transistor M4 receives a current corresponding to a voltage applied to the second node N2, that is, a voltage charged in the first capacitor C1 and the second capacitor C2, of the sixth transistor M6. Supply to the first electrode.

The second electrode of the fifth transistor M5 is connected to the second node N2, and the first electrode is connected to the second electrode of the fourth transistor M4. The gate electrode of the fifth transistor M5 is connected to the n-1 th scan line Sn-1. The fifth transistor M5 is turned on when the scan signal is supplied to the n-th scan line Sn-1 to connect the fourth transistor M4 in the form of a diode.

The first electrode of the sixth transistor M6 is connected to the second electrode of the fourth transistor M4, and the second electrode is connected to the anode electrode of the light emitting device OLED. The gate electrode of the sixth transistor M6 is connected to the nth emission control line En. The sixth transistor M6 is turned off when the emission control signal is supplied to the nth emission control line En, and is turned on when the emission control signal is not supplied. In this case, the emission control signal supplied to the nth emission control line En is supplied to overlap the scan signal supplied to the n−1 th scan line Sn−1 and the n th scan line Sn. Accordingly, the sixth transistor M6 is supplied with the scan signals to the n-1 th scan line Sn-1 and the n th scan line Sn so that a predetermined voltage is applied to the first capacitor C1 and the second capacitor C2. It is turned off when charged, and in other cases it is turned on to electrically connect the fourth transistor M4 and the light emitting element OLED. In FIG. 3, for convenience of description, the transistors M1 to M6 are illustrated in a PMOS type, but the present invention is not limited thereto.

In the pixel illustrated in FIG. 3, the reference power supply Vref does not supply current to the light emitting device OLED. That is, since the reference power supply Vref does not supply current to the pixels 140, no voltage drop occurs, and thus the same voltage value may be maintained regardless of the positions of the pixels 140. Here, the voltage value of the reference power source Vref may be set to be the same as or different from the first power source ELVDD.

4 is a waveform diagram illustrating a method of driving the pixel illustrated in FIG. 3. In FIG. 4, one horizontal period 1H is driven by dividing into a first period and a second period. The voltage data signal VD is supplied to the data lines D1 to Dm during the first period, and the current data signal ID is supplied (sinked) to the data lines D1 to Dm during the second period. Hereinafter, for convenience of description, it is assumed that the initial voltage values of the reference power supply Vref and the first power supply ELVDD are set equal.

3 and 4, the operation process is described in detail. First, a scan signal is supplied to the n−1 th scan line Sn−1. When the scan signal is supplied to the n-1 th scan line Sn-1, the third transistor M3 and the fifth transistor M5 are turned on. When the fifth transistor M5 is turned on, the fourth transistor M4 is connected in the form of a diode. When the fourth transistor M4 is connected in the form of a diode, a voltage value obtained by subtracting the threshold voltage of the fourth transistor M4 from the first power source ELVDD is applied to the second node N2.

When the third transistor M3 is turned on, the voltage of the reference power supply Vref is applied to the first node N1. In this case, the second capacitor C2 charges a voltage corresponding to the difference between the first node N1 and the second node N2. In this case, assuming that the voltage values of the reference power supply Vref and the first power supply ELVDD are the same, a voltage corresponding to the threshold voltage of the fourth transistor M4 is charged in the second capacitor C2. If a predetermined voltage drop occurs in the first power supply ELVDD, the threshold voltage of the fourth transistor M4 and the voltage drop voltage of the first power supply ELVDD are charged in the second capacitor C2. That is, in the present invention, the voltage drop voltage of the first power supply ELVDD and the threshold voltage of the fourth transistor M4 are equal to the second capacitor C2 during the period in which the scan signal is supplied to the n-1 th scan line Sn-1. It is charged to the, thereby compensating for the voltage drop of the first power source (ELVDD).

After the predetermined voltage is charged in the second capacitor C2, the scan signal is supplied to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the first transistor M1 and the second transistor M2 are turned on. When the first transistor M1 is turned on, the voltage data signal VD supplied to the data line Dm is supplied to the first node N1 during the first period. Then, the first capacitor C1 is charged with a voltage corresponding to the difference between the voltage data signal VD and the first power supply ELVDD. At this time, since the second node N2 is set to the floating state, the second capacitor C2 maintains the previously charged voltage.

After the voltage corresponding to the voltage data signal VD is charged in the first capacitor C1, the current corresponding to the current data signal ID is transferred from the pixel 140 via the data line Dm during the second period. It is supplied to the driving unit 120. In fact, the current corresponding to the current data signal ID is supplied to the data driver 120 via the first power source ELVDD, the fourth transistor M4 and the second transistor M2. At this time, the first capacitor C1 and the second capacitor C2 are charged with a voltage corresponding to the current data signal ID.

That is, in the present invention, the second capacitor C2 is charged with a voltage corresponding to the threshold voltage of the fourth transistor M4 and the voltage drop of the first power supply ELVDD during the period in which the scan signal is supplied to the previous scan line. . The voltage data signal VD is supplied during the first period during which the scan signal is supplied to the current scan line to charge the first capacitor C1 with a predetermined voltage first. Thereafter, the current data signal ID is supplied during the second period to control the voltages charged in the first capacitor C1 and the second capacitor C2 to a desired voltage. Here, since the load of the data line is charged during the first period, the charging voltage of the first capacitor C1 and the second capacitor C2 is controlled using the current data signal ID for a short time (ie, the second period). can do. Therefore, in the present invention, a uniform image can be displayed regardless of variation in threshold voltage and electron mobility of the transistor.

Such a process of compensating for the voltage drop of the first power source ELVDD in the present invention will be described in detail. First, the voltage charging process will be described in detail using a case in which the first power source ELVDD and the reference power source Vref are 8V and 4V is supplied as the voltage data signal VD in the first specific pixel. For convenience of description, it is assumed that the threshold voltage of the fourth transistor M4 is 1V.

First, when the scan signal is supplied to the n-th scan line Sn-1, the voltage value of the first node N1 is set to 8V, and the voltage value of the second node N2 is set to 7V. Then, the voltage of 1V is charged to the second capacitor C2. Thereafter, when the scan signal is supplied to the nth scan line Sn, the voltage data signal VD of 4V is supplied to the first node N1. Then, the voltage of 4V is charged in the first capacitor C1. That is, the voltage value charged in the first capacitor C1 and the second capacitor C2 when the voltage data signal VD of 4V is applied to the first specific pixel in which the voltage drop of the first power source ELVDD does not occur. The sum of is set to 5V.

When the first power source ELVDD is 6V due to the voltage drop in the second specific pixel, the voltage charging process will be described in detail. For convenience of description, it is assumed that the threshold voltage of the fourth transistor M4 is 1V.

First, when the scan signal is supplied to the n-th scan line Sn-1, the voltage value of the first node N1 is set to 8V, and the voltage value of the second node N2 is set to 5V. Then, the voltage of 3V is charged in the second capacitor C2. That is, the second capacitor C2 is charged with voltages corresponding to the voltage drop voltage (ie, 2V) of the first power supply ELVDD and the threshold voltage 1V of the fourth transistor M4. Thereafter, when the scan signal is supplied to the nth scan line Sn, the voltage data signal VD of 4V is supplied to the first node N1. Then, the first capacitor C1 is charged with a voltage of 2V. That is, when the voltage data signal VD of 4V is applied to the second specific pixel in which the voltage drop of the first power source ELVDD is generated, the voltage value charged in the first capacitor C1 and the second capacitor C2 is measured. The sum is set to 5V.

As described above, in the pixel 140 of the present invention, a desired voltage may be charged in the first capacitor C1 and the second capacitor C2 regardless of the voltage drop of the first power source ELVDD. Therefore, in the present invention, a uniform image can be displayed regardless of the voltage drop of the first power supply ELVDD.

FIG. 5 is a diagram illustrating the data driving circuit shown in FIG. 2 in detail. FIG. 5 assumes that the data driving circuit 200 has j (j is a natural number of 2 or more) channels for convenience of description.

Referring to FIG. 5, the data driving circuit 200 may include a shift register 210 for sequentially generating sampling signals and a sampling latch unit 220 for sequentially storing data in response to the sampling signals. In addition, the data Data of the sampling latch unit 220 is temporarily stored, and the stored data Data is converted into a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 240 and a current digital-to-analog converter. Holding latch 230 for supplying to 250 (hereinafter referred to as " IDAC unit ") and VDAC for generating voltage data signal VD (predetermined voltage) corresponding to the grayscale value of data Data The unit 240, an IDAC unit 250 for generating the current data signal ID (predetermined current) corresponding to the gray value of the data Data, and a buffer for supplying the voltage data signal VD The buffer unit 260 and the data lines D1 to Dj are in contact with the buffer unit 260 during the first period of one horizontal period. And a selection block 270 for connecting the data lines D1 to Dj with the IDAC unit 250 during the second period.

The shift register unit 210 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 210 supplied with the source shift clock SSC and the source start pulse SSP sequentially generates j sampling signals while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 210 includes j shift registers 2101 to 210j.

The sampling latch unit 220 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register unit 210. Here, the sampling latch unit 220 includes j sampling latches 2201 to 220j to store j data. Each of the sampling latches 2201 to 220j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2201 to 220i is set to a size of k bits.

The holding latch unit 230 receives data from the sampling latch unit 220 and stores the data when the source output enable signal SOE is input. The holding latch unit 230 supplies the data Data stored therein to the VDAC unit 240 and the IDAC unit 250 when the source output enable signal SOE is input. To this end, the holding latch unit 230 includes j holding latches 2301 to 230j set to k bits.

The VDAC unit 240 generates a voltage data signal VD corresponding to the bit value of the data Data, and supplies the generated voltage data signal VD to the selection block 270 via the buffer unit 260. do. To this end, the VDAC unit 240 includes j voltage generators 2401 to 240j. Meanwhile, the VDAC unit 240 may directly supply the voltage data signal VD to the selection block 270 without passing through the buffer unit 260.

The IDAC unit 250 generates the current data signal ID corresponding to the bit value of the data Data, and supplies the generated current data signal ID from the pixels 140 via the selection block 270. Receive. That is, the IDAC unit 250 sinks the current corresponding to the bit value of the data Data from the pixels 140 by the current data signal ID. To this end, the IDAC unit 250 includes j current generation units 2501 to 250j.

The buffer unit 260 supplies the voltage data signal VD supplied from the VDAC unit 240 to the selection block 270. To this end, the buffer unit 260 includes j buffers 2601 to 260j.

The selection block 270 connects the data lines D1 to Dj and the VDAC unit 260 via the buffer unit 260 during the first period of the horizontal period 1H, and the data lines (D) for the other second period. D1 to Dj) and the IDAC unit 250 are connected. Then, the voltage data signal VD is supplied to the pixels 140 selected by the scan signal via the data lines D1 to Dj during the first period. In the second period, the current data signal ID is supplied from the pixels 140 to the IDAC unit 250 via the data lines D1 to Dj. To this end, the selection block 270 is provided with j selection units 2701 to 270j.

Meanwhile, the data driving circuit 200 of the present invention may further include a level shifter 280 at the next stage of the holding latch 230 as shown in FIG. 6. The level shifter unit 280 increases the voltage level of the data supplied from the holding latch unit 230 and supplies it to the VDAC unit 240 and the IDAC unit 250. When data having a high voltage level is supplied from the external system to the data driving circuit 200, the manufacturing cost is increased because circuit components corresponding to the voltage level must be installed. Accordingly, data Data having a low voltage level is supplied from the outside of the data driving circuit 200, and the data Shift having the low voltage level is boosted by the level shifter 280 to a high voltage level.

7 is a diagram illustrating a pixel, a current generator, a voltage generator, and a selector connected to a data line. In FIG. 7, for convenience of description, the j th voltage generator 240j and the j th current generator 250j are illustrated.

Referring to FIG. 7, the selector 270j of the present invention includes a first switching device SW1 connected between the voltage generator 240j and the data line Dj, the current generator 250j and the data line A second switching device SW2 is connected between the Djs.

As illustrated in FIG. 8, the first switching device SW1 is turned on during the first period of the first horizontal period 1H by the first selection signal supplied from the first control line CL1. That is, the first switching device SW1 is turned on during the period in which the voltage data signal VD is supplied to the data line Dj.

The second switching device SW2 is turned on for the second period of the one horizontal period 1H by the second selection signal supplied from the second control line CL2. That is, the second switching device SW2 is turned on during the period in which the current data signal ID is supplied to the data line Dj.

The voltage generator 240j generates the voltage data signal VD in response to the gray value of the data Data supplied thereto. The voltage data signal VD generated by the voltage generator 240j is supplied to the data line Dj during the period in which the first switching device SW1 is turned on.

The current generator 250j is configured as a current sink type. In other words, the current generator 250j generates the current data signal ID corresponding to the gray value of the data Data supplied to the current generator 250j, and generates a current corresponding to the generated current data signal ID. 140). In practice, the current generator 250j receives the current data signal ID via the pixel 140 and the data line Dj during the period in which the second switching device SW2 is turned on.

4, 7 and 8, the operation process will be described in detail. First, the fourth transistor M4 is applied to the second capacitor C2 during the period in which the scan signal is supplied to the n-th scan line Sn-1. The voltage corresponding to the threshold voltage and the voltage drop of the first power supply ELVDD is first charged. Thereafter, the scan signal is supplied to the nth scan line Sn so that the first transistor M1 and the second transistor M2 are turned on.

The first switching device SW1 is turned on during the first period of the specific horizontal period in which the scan signal is supplied to the nth scan line Sn. When the first switching device SW1 is turned on, the voltage data signal VD generated by the voltage generator 240j passes through the buffer 260j, the first switching device SW1, and the first transistor M1. It is supplied to the first node N1. At this time, the first capacitor C1 is first charged with a voltage corresponding to the difference between the first power supply ELVDD and the voltage data signal VD.

The second switching device SW2 is turned on during the second period of the specific horizontal period. When the second switching device SW2 is turned on, a predetermined current (current data signal ID is passed through the first power source ELVDD, the fourth transistor M4, the second transistor M2, and the data line Dj). ) Is supplied to the current generating unit 250j. At this time, the first capacitor C1 and the second capacitor C2 are charged with a second voltage corresponding to the current data signal ID.

Thereafter, the sixth transistor M6, which has been turned off during the period in which the scan signal is supplied to the n−1 th scan line Sn−1 and the n th scan line Sn, is turned on. Then, the current supplied from the fourth transistor M4 is supplied to the light emitting device OLED through the sixth transistor M6 in response to the voltage charged in the first capacitor C1 and the second capacitor C2. Therefore, light of a predetermined luminance is generated in the light emitting device OLED.

On the other hand, the configuration of the switching device (SW) in the present invention can be variously set. For example, in the present invention, as shown in FIG. 9, the first switching device SW1 and the third switching device SW3 may be connected in the form of a transmission gate. Here, the first switching device SW1 formed of the NMOS type is connected to the first control line CL1, and the third switching device SW3 formed of the PMOS type is connected to the third control line CL3. In this case, as shown in FIG. 10, the first selection signal supplied to the first control line CL1 and the third selection signal supplied to the third control line CL3 have opposite polarities. Thus, the first and third switching elements SW1 and SW3 are turned on and off at the same time.

On the other hand, when the first switching device SW1 and the third switching device SW3 are connected in the form of a transmission gate, the switching error can be minimized because the voltage-current characteristic curve is set in a substantially straight line shape.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the pixel and the light emitting display device using the same according to the embodiment of the present invention, the voltage drop voltage and the light emission of the first power supply to the second capacitor included in each pixel during the period in which the scanning signal is supplied to the previous scanning line The voltage corresponding to the threshold voltage of the transistor for supplying current to the device is charged. As such, when the voltage drop voltage of the first power source is charged in the second capacitor, an image having uniform brightness may be displayed regardless of the voltage drop of the first power source.

In the present invention, the voltage is supplied to the data lines during the first period of the period during which the scan signal is supplied to the scan line, and the current is supplied to the data lines during the second period. That is, in the present invention, since the final voltage of the capacitors included in each of the pixels is controlled by using the current, a uniform image can be displayed. In addition, since the pixels are primarily charged using the voltage during the first period, the charging time due to the current can be sufficiently secured.

Claims (13)

The first power source, A light emitting device receiving a predetermined current from the first power supply; A plurality of transistors, When a scan signal is supplied to a previous scan line, a voltage corresponding to a threshold voltage of a transistor that controls an amount of current flowing from the first power source to the light emitting device among the plurality of transistors and a voltage corresponding to a voltage drop of the first power source are determined. A second capacitor for primary charging, And a first capacitor for first charging a voltage corresponding to the first data signal, which is a predetermined voltage supplied to the data line during the first period of the period in which the scan signal is currently supplied to the scan line. And the first capacitor and the second capacitor are secondary charged in response to a second data signal which is a predetermined current flowing to the data line for a second period except the first period. The method of claim 1, A first transistor and a second transistor connected to the data line and turned on when a scan signal is supplied to the current scan line; A third transistor connected between a reference power supply and a second electrode of the first transistor and turned on when a scan signal is supplied to the previous main line; A fourth transistor for controlling an amount of current flowing from the first power source to the light emitting element in response to a voltage charged in the first capacitor and the second capacitor; And a fifth transistor connected between the gate electrode and the second electrode of the fourth transistor and turned on when a scan signal is supplied to the previous scan line to connect the fourth transistor in the form of a diode. The method of claim 2, And the second capacitor is connected between the second electrode of the first transistor and the gate electrode of the fourth transistor, and the first capacitor is connected between the second electrode of the first transistor and the first power source. The method of claim 2, And the second capacitor charges a voltage corresponding to a difference value between the voltage applied to the gate electrode of the fourth transistor and the reference power supply when the scan signal is supplied to the previous scan line. The method of claim 2, The first transistor provides a path for the first data signal to be supplied to the first capacitor and the second capacitor, and the second transistor is connected to the data line from the first power supply via the fourth transistor. And providing a path to allow a current corresponding to the second data signal to flow. The method of claim 2, And a sixth transistor connected between the fourth transistor and the light emitting element and turned off when a scan signal is supplied to the previous scan line and the current scan line, and turned on for another period. A scan driver for sequentially supplying scan signals to scan lines; At least one of supplying a first data signal of a predetermined voltage to the data lines during a first period of each horizontal period, and controlling a second data signal of a predetermined current to flow through the data lines for a second period except the first period; A data driver having a data driver circuit; A light emitting display device comprising a pixel portion including a plurality of pixels according to any one of claims 1 to 6. The method of claim 7, wherein The data driving circuit A voltage digital-to-analog converter for generating the first data signal in response to a gray value of data supplied from the outside; A current digital-analog converter for generating the second data signal in response to the grayscale value of the data; And a selection block for connecting the voltage digital-analog converter and the data lines during the first period, and connecting the current digital-analog converter and the data lines during the second period. The method of claim 8, The selection block has a plurality of selection sections, each of the selection sections A first switching element connected between the voltage digital-analog converter and the data line to be turned on for the first period and to be turned off for a second period; And a second switching element connected between the current digital-analog converter and the data line to be turned on for the second period and to be turned off for the first period. The method of claim 9, And a third switching device connected to the first switching device in the form of a transmission gate. The method of claim 8, And a buffer unit connected between the voltage digital-analog converter and the selection block. The method of claim 8, A shift register section for sequentially generating sampling signals; And a latch unit configured to store the data in response to the sampling signal and to supply the stored data to the voltage digital-analog converter and the current digital-analog converter. The method of claim 12, And a level shifter unit for raising a voltage level of data stored in the latch unit to supply the voltage digital-analog converter and the current digital-analog converter.

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