KR100613087B1 - Pixel and Light Emitting Display Using The Same - Google Patents

Abstract

The present invention relates to a pixel capable of displaying an image of desired luminance.

The pixel of the present invention includes a light emitting element, a driver for supplying a pixel current corresponding to a data signal supplied from a data line to the light emitting element, and between the driver and the data line for a first period of one horizontal period. A first switching block turned on, and a second switching block disposed between the driving unit and the common terminal of the light emitting device and the data line and turned off during the first period, wherein the second switching block is turned off during the first horizontal period. During the second period except the one period, the first switching block and the second switching block are alternately turned on and off at least once.

By such a configuration, the pixels of the present invention can display an image of desired luminance in response to a data signal.

Description

Pixel and Light Emitting Display Using The Same}             

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a first embodiment of the pixel illustrated in FIG. 2.

4 is a waveform diagram illustrating a method of driving the pixel illustrated in FIG. 3.

FIG. 5 is a block diagram illustrating an embodiment of the data integrated circuit shown in FIG. 2.

FIG. 6 is a block diagram illustrating another embodiment of the data integrated circuit shown in FIG. 2.

FIG. 7 is a block diagram illustrating a voltage adjuster and a selector illustrated in FIGS. 3 and 4.

FIG. 8 is a diagram illustrating a selection signal supplied to the selection unit illustrated in FIG. 7.

FIG. 9 is a diagram illustrating a voltage range controlled by the voltage increase and decrease unit illustrated in FIG. 7.

FIG. 10 is a circuit diagram illustrating a second embodiment of the pixel illustrated in FIG. 2.

11 and 12 are circuit diagrams illustrating another embodiment of the first switching block illustrated in FIG. 10.

FIG. 13 is a circuit diagram illustrating another example of the pixel illustrated in FIG. 10.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: image display unit 40,140: pixel

50,150: timing controller 129: data integrated circuit

141, 142: switching block, 143: drive unit

200: shift register portion 210: sampling latch portion

220: holding latch portion 230: voltage digital to analog converter

240: current digital-analog converter 250: voltage regulator

252: comparator 254: voltage increase and decrease

256: control unit 260: buffer unit

270: level shifter 280: selection block

The present invention relates to a pixel and a light emitting display device using the same, and more particularly, to a pixel and a light emitting display device using the same to display an image of a desired brightness.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device emits light from a light emitting device by supplying a current corresponding to the data signal to the light emitting device using a transistor formed for each pixel.

1 illustrates a conventional light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed in an area partitioned by scan lines S1 to Sn and data lines D1 to Dm; Controlling the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20 The timing control part 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal.

The image display unit 30 receives the first power source VDD and the second power source VSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power source VDD and the second power source VSS receives a current flowing from the first power source VDD to the second power source VSS via the light emitting element in response to the data signal. The control generates light corresponding to the data signal.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, in the related art, light having a desired luminance may not be generated due to a nonuniform threshold voltage of a transistor included in each of the pixels 40. In the related art, there is no method of measuring and controlling the current flowing in each of the pixels 40 in response to the data signal.

Accordingly, an object of the present invention is to provide a pixel and a light emitting display device using the same to display an image having a desired luminance.

In order to achieve the above object, the first aspect of the present invention provides a light emitting element, a driver for supplying a pixel current corresponding to a data signal supplied from a data line to the light emitting element, and is provided between the driver and the data line. A first switching block turned on for a first period of one horizontal period, and a second switching block disposed between the driving unit and the common terminal of the light emitting element and the data line, and turned off for the first period. The first switching block and the second switching block provide a pixel that is alternately turned on and off at least once during a second period except the first period of the first horizontal period.

Preferably, the data signal is supplied to the driving unit when the first switching block is turned on, and the pixel current is supplied to the data line when the second switching block is turned on. A first scanning signal connected to the first switching block, the first scanning block being turned on during the first period and supplied with a first scanning signal to the first switching block such that the first switching block is turned on and off at least once during the second period; A first scanning line for performing; A second scanning device connected to the second switching block, the second switching block being turned off for the first period, and being turned on and off alternately with the first switching block for the second period; And a second scan line for supplying the arc to the second switching block.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 13 to which a person skilled in the art may easily implement the present invention.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention may include first scan lines S11 to S1n, second scan lines S21 to S2n, emission control lines E1 to En, and data lines D1. Through the image display unit 130 including the pixels 140 formed in the area partitioned by Dm, the first scan lines S11 to S1n, the second scan lines S21 to S2n, and the emission control lines A timing controller for controlling the scan driver 110 for driving E1 to En, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. 150.

The image display unit 130 is formed in an area partitioned by the first scan lines S11 to S1n, the second scan lines S21 to S2n, the emission control lines E1 to En, and the data lines D1 to Dm. Pixels 140 are provided. The pixels 140 receive a first power source VDD and a second power source VSS from an external source. Each of the pixels 140 supplied with the first power source VDD and the second power source VSS has a second power source from the first power source VDD via a light emitting element in response to a data signal supplied from the data line D. The pixel current flowing to the power supply VSS is controlled. The pixels 140 supply the pixel current to the data driver 120 through the data line D during a part of one horizontal period. To this end, each of the pixels 140 may be configured as shown in FIG. 3. The detailed structure of the pixel 140 shown in FIG. 3 will be described later.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS sequentially supplies the first scan signal to the first scan lines S11 to S1n, and at the same time, the second scan signal to the second scan lines S21 to S2n. Supply sequentially.

In the scan driver 110, as shown in FIG. 4, the first transistor M1 of the pixel 140 is turned on during the first period of one horizontal period, and the first transistor M1 is turned on for the second period. Supplies a first scan signal to repeat turn-on and turn-off. The scan driver 110 turns off the second transistor M2 of the pixel 140 during the first period of one horizontal period, and alternately turns on the first transistor M1 during the second period. And a second scan signal to repeat the turn-off. In addition, the scan driver 110 supplies the emission control signal so that the third transistor M3 is turned off during the period in which the first scan signal and the second scan signal are supplied, and turned on for the other period. That is, the light emission control signal is supplied to overlap with the first scan signal and the second scan signal, and the width thereof is set equal to or wider than the width of the first scan signal.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm. Here, the data driver 120 supplies a predetermined gray scale voltage to the data lines D1 to Dm as a data signal.

In addition, the data driver 120 receives the pixel current from the pixels 140 during a part of the second period, and checks whether the supplied pixel current has a current value corresponding to the data. For example, when the pixel current to flow in the pixel 140 corresponding to the number of bits (or gradation value) of the data (Data) is 10 ㎂, the data driver 120 checks whether the pixel current supplied to it is 10 ㎂ do. Here, when the desired current is not supplied from each of the pixels 140, the data driver 120 changes the gray voltage so that a desired current flows from each of the pixels 140. To this end, the data driver 120 includes at least one data integrated circuit 129 including j channels (where j is a natural number). The detailed configuration of the data integrated circuit 129 will be described later.

FIG. 3 is a diagram illustrating a first embodiment of the pixel illustrated in FIG. 2. In FIG. 3, pixels connected to the m-th data line Dm, the n-th first scan line S1n, the n-th second scan line S2n, and the n-th emission control line En are illustrated in FIG. 3. do. In addition, although the transistors M1 to M4 are illustrated in the PMOS conductivity type in FIG. 3, the present invention is not limited thereto.

Referring to FIG. 3, the pixel 140 according to the first exemplary embodiment of the present invention includes a light emitting device OLED, a first switching block 141, a second switching block 142, a driver 143, and a third transistor. (M3) is provided.

The first switching block 141 is connected between the data line Dm and the driver 143 to supply the gray voltage supplied from the data line Dm to the driver 143. To this end, the first switching block 141 includes at least one transistor. For example, the first switching block 141 may include one first transistor M1. The first transistor M1 is controlled by the first scan signal supplied from the nth first scan line S1n.

The second switching block 142 is connected between the data line Dm and the driver 143 to supply the pixel current supplied from the driver 143 to the data line Dm. To this end, the second switching block 142 includes at least one transistor. For example, the second switching block 142 may include one second transistor M2. The second transistor M2 is controlled by the second scan signal supplied from the nth second scan line S2n.

The third transistor M3 is connected between the driving unit 143 and the light emitting device OLED. The third transistor M3 is controlled by the emission control signal supplied from the nth emission control line En. In practice, the third transistor M3 is turned off when the light emission control signal is supplied and is turned on for the rest of the period.

The driver 143 supplies the pixel current corresponding to the gray voltage supplied from the first transistor M1 to the second transistor M2 and the third transistor M3. To this end, the driver 143 may include a fourth transistor M4 connected between the first power source VDD and the third transistor M3, and a gate electrode and a first power source VDD of the fourth transistor M4. And a capacitor C connected to it. The capacitor C charges a predetermined voltage corresponding to the gray voltage. The fourth transistor M4 supplies the pixel current corresponding to the voltage charged in the capacitor C.

Referring to FIGS. 3 and 4, the operation of the pixel 140 will be described in detail. First, the first scan signal is supplied to the nth first scan line S1n during a specific horizontal period of one frame and the nth second scan line at the same time. The second scan signal is supplied to S2n.

The first transistor M1 supplied with the first scan signal is turned on for the first period of one horizontal period. When the first transistor M1 is turned on, the data signal (gradation voltage) supplied to the data line Dm is supplied to the capacitor C during the first period. At this time, the capacitor C is charged with a predetermined voltage corresponding to the data signal. Meanwhile, the second transistor M2 supplied with the second scan signal maintains the turn-off state for the first period.

Thereafter, the first transistor M1 is turned off and the second transistor M2 is turned on for a part of the second period. When the second transistor M2 is turned on, the pixel current supplied from the fourth transistor M4 is supplied to the data line Dm in response to a predetermined voltage charged in the capacitor C. The pixel current supplied to the data line Dm is supplied to the data driver 120, and the data driver 120 receiving the pixel current increases or decreases the voltage value of the gray scale voltage so that a desired pixel current flows in the pixel 140. Let's do it. Thereafter, the second transistor M2 is turned off and the first transistor M1 is turned on. When the first transistor M1 is turned on, the gray voltage increased or decreased by the data driver 120 is supplied to the capacitor C to change the charging voltage value of the capacitor C. In practice, during the second period, the first transistor M1 and the second transistor M2 alternately turn on and off at least one time, thereby changing the charging voltage value of the capacitor C so that a desired pixel current can flow. Change.

FIG. 5 is a diagram illustrating in detail the data integrated circuit shown in FIG. 2. FIG. 5 assumes that the data integrated circuit 129 has j channels for convenience of description.

Referring to FIG. 5, the data integrated circuit 129 may include a shift register unit 200 for sequentially generating a sampling signal and a sampling latch unit 210 for sequentially storing data in response to the sampling signal. The data data of the sampling latch unit 210 may be temporarily stored, and the stored data may be stored in a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 230 and a current digital-to-analog converter. Holding latch 220 for supplying to the 240 (hereinafter referred to as " IDAC unit "), VDAC unit 230 for generating a gradation voltage Vdata corresponding to the gradation value of data Data, and data Changing the gradation voltage Vdata in response to the IDAC unit 240 generating the gradation current Idata corresponding to the gradation value of Data and the pixel current Ipixel supplied from the data lines D1 to Dj. The voltage adjusting block 250 and the gray scale voltage Vdata supplied from the voltage adjusting block 250. A buffer unit 260 for supplying the data lines D1 to Dj, and a selection block for selectively connecting the data lines D1 to Dj with any one of the buffer unit 260 and the voltage adjusting block 250. 280).

The shift register unit 200 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 200 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 200 includes j shift registers 2001 to 200j.

The sampling latch unit 210 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 200. Here, the sampling latch unit 210 includes j sampling latches 2101 to 210j to store j data. Each of the sampling latches 2101 to 210j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2101 to 210j is set to a size of k bits.

The holding latch unit 220 receives data from the sampling latch unit 210 and stores the data when the source output enable signal SOE is input. The holding latch unit 220 supplies data stored therein to the VDAC unit 230 and the IDAC unit 240 when the source output enable signal SOE is input. To this end, the holding latch unit 220 includes j holding latches 2201 to 220j set to k bits.

The VDAC unit 230 generates a gray voltage Vdata corresponding to a bit value (that is, a gray value) of the data Data, and supplies the generated gray voltage Vdata to the voltage adjusting block 250. Here, the VDAC unit 230 generates j gray voltages Vdata corresponding to j data Data supplied from the holding latch unit 220. To this end, the VDAC unit 230 includes j voltage generators 2301 to 230j. Hereinafter, for convenience of description, the gray voltage Vdata generated by the VDAC unit 230 will be referred to as a first gray voltage Vdata.

The IDAC unit 240 generates a gradation current Idata corresponding to the bit value of the data, and supplies the generated gradation current Idata to the voltage adjusting block 250. Here, the IDAC unit 240 generates j gradation currents Idata corresponding to j data Data supplied from the holding latch unit 220. To this end, the IDAC unit 240 includes j current generation units 2401 to 240j.

The voltage adjusting block 250 receives a first gray voltage Vdata, a gray current Idata, and a pixel current Ipixel. The voltage adjusting block 250 supplied with the first gradation voltage Vdata, the gradation current Idata, and the pixel current Ipixel compares the current difference between the gradation current Idata and the pixel current Ipixel, and compares the currents. In response to the difference, the voltage value of the first gradation voltage Vdata is readjusted. Hereinafter, for convenience of description, the first gray voltage Vdata readjusted by the voltage adjusting block 250 will be referred to as a second gray voltage. Ideally, the voltage adjusting block 250 controls the voltage value of the second gradation voltage so that the gradation current Idata and the pixel current Ipixel can be set to the same value. To this end, the voltage adjusting block 250 includes j voltage adjusting units 2501 to 250j.

The buffer unit 260 supplies the first gray voltage Vdata or the second gray voltage supplied from the voltage adjusting block 250 to the j data lines D1 to Dj. To this end, the buffer unit 260 includes j buffers 2601 to 260j.

The selection block 280 selectively connects the data lines D1 to Dj with the buffer unit 260 or the voltage adjusting block 250. To this end, the selection block 280 is provided with j selection units 2801 to 280j.

Meanwhile, the data integrated circuit of the present invention may further include a level shifter unit 270 between the holding latch unit 220, the VDAC unit 230, and the IDAC unit 240 as shown in FIG. 6. The level shifter unit 270 increases the voltage level of the data Data supplied from the holding latch unit 220 and supplies it to the VDAC unit 230 and the IDAC unit 240. When data having a high voltage level is supplied to the data integrated circuit 129 from an external system, a manufacturing cost increases because circuit components corresponding to the voltage level need to be installed. Therefore, the data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level sheeter 270 to a high voltage level.

FIG. 7 is a detailed diagram illustrating the voltage adjusting unit and the selecting unit illustrated in FIG. 4. In FIG. 7, for convenience of description, the j-th voltage adjuster 250j and the selector 280j are illustrated.

Referring to FIG. 7, the selector 280j of the present invention includes a fifth transistor M5 connected between the buffer 260j and the data line Dj, and between the voltage adjuster 250j and the data line Dj. The sixth transistor M6 is connected. The fifth transistor M5 and the sixth transistor M6 are alternately turned on to connect the data line Dj to one of the buffer 260j and the voltage adjuster 250j. To this end, the fifth transistor M5 and the sixth transistor M6 are set to different conductivity types. The fifth transistor M5 and the sixth transistor M6 are controlled by the selection signal supplied from the control line CL.

As shown in FIG. 8, the selection signal is supplied such that the fifth transistor M5 can be turned on during the first period of one horizontal period. The selection signal is supplied to alternately turn on the fifth transistor M5 and the sixth transistor M6 during the second period. In practice, the selection signal is turned on and turned off in the fifth transistor M5 in the same manner as the first transistor M1 during the second period, and the sixth transistor M6 in the same manner as the second transistor M2. Supplied to be turned on and off.

The voltage adjustor 250j includes a comparator 252, a voltage increase and decrease unit 254, a controller 256, a first capacitor C1, and a switching device SW1. The switching element SW1 is provided between the VDAC unit 230 and the buffer 260j. The switching device SW1 is turned on during the first period and is turned off during the second period under the control of the controller 256.

The first capacitor C1 is provided between the first node N1, which is a common terminal of the switching element SW1, and the buffer 260j, and the voltage increase / decrease unit 254. The first capacitor C1 provided between the first node N1 and the voltage increase / decrease unit 254 increases or decreases the voltage value of the first node N1 in response to a voltage supplied from the voltage increase / decrease unit 254. That is, when a high voltage is supplied from the voltage increase / decrease unit 254, the voltage value of the first node N1 is increased by the first capacitor C1, and when a low voltage is supplied from the voltage increase / decrease unit 254, the first capacitor is supplied. The voltage value of the first node N1 is decreased by C1.

The comparator 252 receives the gradation current Idata from the IDAC unit 240, and receives the pixel current Ipixel from the pixel 140 via the data line Dj and the selector 280j. Here, the pixel current Ipixel is supplied from the pixel 140 to which the first and second scan signals are currently supplied. The comparison unit 252 supplied with the pixel current Ipixel and the gradation current Idata compares the gradation current Idata and the pixel current Ipixel, and compares the first control signal or the second control signal corresponding to the result of the comparison. Is supplied to the voltage increase / decrease unit 254. For example, the comparator 252 generates the first control signal when the gradation current Idata is greater than the pixel current Ipixel, and the second control signal when the gradation current Idata is smaller than the pixel current Ipixel. Is generated and supplied to the voltage increase / decrease unit 254.

The voltage increase / decrease unit 254 supplies a predetermined voltage value to the first capacitor C1 in response to the first control signal or the second control signal supplied from the comparator 252. Here, the voltage increasing / decreasing unit 254 supplies a predetermined voltage to the first capacitor C1 so that the pixel current Ipixel and the gradation current Idata may be similar. Then, the voltage value of the first node N1 is increased or decreased corresponding to the voltage supplied to the first capacitor C1. Here, the increased or decreased voltage of the first node N1 is used as the second gray voltage.

The control unit 256 turns on the switching device SW1 for the first period of one horizontal period 1H, and turns off the switching device SW1 for the second period of time. The controller 256 supplies a counting signal gradually increasing during the second period to the voltage increase / decrease unit 254. For example, the control unit 256 supplies a counting signal that increases from "1" to "l" (l is a natural number) to the voltage increase / decrease unit 254. To this end, a counter (not shown) is included in the control unit 256. The counting signal of the controller 256 is initialized when the reset signal Reset is supplied. Here, the reset signal Reset is set to a signal supplied in units of one horizontal period. For example, the reset signal Reset may be used as the horizontal synchronization signal H or the scan signal.

In detail, the switching device SW1, the fifth transistor M5, and the first transistor M1 are turned on during the first period of one horizontal period. When the switching device SW1 is turned on, the first gray voltage Vdata supplied from the VDAC unit 230 is supplied to the data line Dj through the buffer 260j and the fifth transistor M5. The first gray voltage Vdata supplied to the data line Dj is supplied to the pixel 140 selected by the scan signal. That is, the first gray voltage Vdata supplied to the data line Dj is supplied to the driver 142 via the first transistor M1 turned on by the first scan signal. Then, a voltage corresponding to the first gray voltage Vdata is charged in the capacitor C included in the driver 142. In fact, the first period is set so that the capacitor C included in the pixel 140 is charged with a predetermined voltage corresponding to the first gradation voltage Vdata.

After the predetermined voltage is charged in the capacitor C included in the pixel 140, the sixth transistor M6 and the second transistor M2 are turned on at the start of the second period, and the switching element SW1 is turned on. The fifth transistor M5 and the first transistor M1 are turned off. When the switching device SW1 is turned off, the first node N1 is floated. At this time, the first node N1 maintains the voltage of the first gray voltage Vdata by a parasitic capacitor (not shown). When the second transistor M2 is turned on, the pixel current Ipixel generated by the driver 142 of the pixel 140 passes through the second transistor M2, the data line Dj, and the sixth transistor M6. To the comparator 252.

The comparison unit 252 supplied with the pixel current Ipixel compares the gradation current Idata supplied from the IDAC unit 240 with the pixel current Ipixel, and responds to the first control signal or the second control in response to the comparison result. The signal is generated and supplied to the voltage increase / decrease unit 254. Here, the gradation current Idata is an ideal current value that should actually flow in the pixel 140 in response to the data, and the pixel current Ipixel is a current value that actually flows in the pixel 140.

During the second period, the controller 256 supplies a counting signal that is increased from "1" to "l" to the voltage increase / decrease unit 254. The voltage increasing / decreasing unit 254 receiving the counting signal supplies a predetermined voltage value to the first capacitor C1 in response to the first control signal or the second control signal supplied from the comparator 252. Here, the voltage increase / decrease unit 254 may supply a voltage value supplied to the first capacitor C1 so that the gray scale current Idata and the pixel current Ipixel may be the same or similar to the first control signal or the second control signal. To control. Then, the voltage value of the first node N1 is changed corresponding to the voltage value supplied to the first capacitor C1, thereby generating the second gray voltage.

After the second gray voltage is generated, the sixth transistor M6 and the second transistor M2 are turned off, and the fifth transistor M5 and the first transistor M1 are turned on. When the fifth transistor M5 and the first transistor M1 are turned on, the second gray voltage applied to the first node N1 is supplied to the pixel 140. Then, the pixel 140 generates a pixel current Ipixel corresponding to the second gray voltage. In fact, in the present invention, the sixth and second transistors M2 and M6 and the fifth and first transistors M1 and M5 so that the gradation current Idata and the pixel current Ipixel become similar or the same during the second period. Are alternately turned on and off at least once.

On the other hand, the voltage range which is increased or decreased in the voltage increase / decrease unit 254 is determined by the counting signal. For example, the voltage increase / decrease unit 254 increases or decreases the voltage within the range of the first voltage V1 as shown in FIG. 9 when the first counting signal (eg, “1”) is supplied. In other words, when the first counting signal is supplied, the voltage of V1 / 2 is increased or decreased. The voltage increasing / decreasing unit 254 increases or decreases the voltage within the range of the second voltage V2 lower than the first voltage V1 when the second counting signal (eg, “2”) is supplied. In other words, when the second counting signal is supplied, the voltage of V2 / 2 is increased or decreased. On the other hand, the second voltage V2 is set to approximately 1/2 of the first voltage V1. The voltage increasing / decreasing unit 254 increases or decreases the voltage within the range of the third voltage V3 lower than the second voltage V2 when the third counting signal (eg, “3”) is supplied. That is, as the counting signal is increased, the voltage range increased or decreased by the voltage increase / decrease unit 254 is lowered. Here, the lowering voltage range may be set to 1/2 of the previous voltage range. In this manner, the voltage increase / decrease unit 254 controls the voltage supplied to the first capacitor C1 so that the gray voltage Idata and the pixel current Ipixel can be the same or similar.

10 is a diagram illustrating a pixel according to a second exemplary embodiment of the present invention. In fact, only the configuration of the first switching block 141 is changed in the pixel illustrated in FIG. 10, and other configurations and driving processes are the same as the pixel according to the first exemplary embodiment of the present disclosure illustrated in FIG. 3. Therefore, when describing FIG. 10, detailed description of parts described in FIG. 3 will be omitted.

Referring to FIG. 10, the pixel 140 according to the second embodiment of the present invention includes a light emitting device OLED, a first switching block 141, a second switching block 142, a driver 143, and a fourth transistor. (M14) is provided.

The first switching block 141 is connected between the data line Dm and the driver 143 to supply a data signal (first gradation voltage or second gradation voltage) supplied from the data line Dm to the driver 143. do. To this end, the first switching block 141 includes a first transistor M11 and a second transistor M12.

The first transistor M11 is connected between the data line Dm and the driver 143. The first transistor M11 is controlled by the first scan signal supplied to the n-th first scan line S1n. That is, the first transistor M11 is turned on during the first period of one horizontal period and is turned on and off at least once during the second period. The second transistor M12 is connected between the first transistor M11 and the driver 143. The second transistor M12 is controlled by the second scan signal supplied to the n-th second scan line S2n. Here, the drain electrode and the source electrode of the second transistor M12 are electrically connected. Therefore, when the first transistor M11 is turned on, the data signal is supplied to the driver 143 regardless of whether the second transistor M12 is turned on or turned off. The second transistor M12 is used to reduce the switching error of the first transistor M11. In fact, when the second transistor M12 is installed in the first switching block 141, switching errors can be reduced, thereby improving driving reliability.

The second switching block 142 is connected between the data line Dm and the driver 143 to supply the pixel current supplied from the driver 143 to the data line Dm. To this end, the second switching block 142 has a third transistor M13. The third transistor M13 is controlled by the second scan signal supplied from the nth second scan line S2n. That is, the third transistor M13 is turned off during the first period of one horizontal period, and is alternately turned on and off with the first transistor M11 during the second period.

The fourth transistor M14 is connected between the driving unit 143 and the light emitting element OLED. The fourth transistor M14 is controlled by the emission control signal supplied from the nth emission control line En. Here, the fourth transistor M14 is turned off when the light emission control signal is supplied, and is turned on for the other period.

The driver 143 supplies the pixel current corresponding to the data signal supplied from the first switching block 141 to the second switching block 142 and the fourth transistor M14. To this end, the driver 143 may include a fifth transistor M15 connected between the first power source VDD and the fourth transistor M14, and a gate electrode of the fifth transistor M15 and the first power source VDD. Capacitor C is connected to. The capacitor C charges a predetermined voltage corresponding to the data signal. The fifth transistor M15 supplies the pixel current corresponding to the voltage charged in the capacitor C to the second switching block 142 and the fourth transistor M14.

11 is a diagram illustrating a pixel according to a third exemplary embodiment of the present invention. In fact, the pixel shown in FIG. 11 is changed only in the configuration of the first switching block 141, and the other configuration and driving process are the same as the pixel shown in FIG. Therefore, detailed description of the configuration except for the first switching block 141 will be omitted.

Referring to FIG. 11, the first switching block 141 of the pixel according to the third embodiment of the present invention includes a first transistor M11 and a second transistor M12 connected in the form of a transmission gate. do.

The gate electrode of the first transistor M11 formed of the PMOS conductivity type is connected to the nth first scan line S1n. The gate electrode of the second transistor M12 formed of the NMOS conductivity type is connected to the nth second scan line S2n. Here, since the first scan signal and the second scan signal have opposite polarities, the first transistor M11 and the second transistor M12 have the same time (that is, when the first scan signal and the second scan signal are supplied). ) Is turned on to electrically connect the data line Dm and the driver 143.

On the other hand, when the first transistor M11 and the second transistor M12 are connected in the form of a transmission gate, the switching error can be minimized because the voltage-current characteristic curve is set in a substantially straight shape. In addition, in the present invention, the first switching block 141 may further include transistors M111, M112, M121, and M122 connected in the form of a transmission gate as shown in FIG. 12. In practice, the first switching block 141 includes at least one NMOS transistor and a PMOS transistor connected in the form of a transmission gate.

In addition, the pixels described in the present invention may be changed to NMOS transistors as shown in FIG. 13. In fact, the pixel of FIG. 13 is configured by changing the PMOS transistors M11 to M15 shown in the pixel of FIG. 10 to the NMOS transistors M11 to M15. As shown in FIG. 13, when the pixels are formed of NMOS transistors, polarities of signals (first scan signal, second scan signal, light emission control signal, etc.) are reversed as is well known to those skilled in the art.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the pixel and the light emitting display device using the same according to the embodiment of the present invention, the gradation current corresponding to the data and the pixel current flowing in the pixel are compared, and the pixel current is similar to the gradation current in response to the comparison result. By changing the gradation voltage to change to the current value, an image of desired luminance can be displayed in the pixel. In the present invention, the pixel current from the pixel is supplied to the data integrated circuit via the data line, and the gradation voltage from the data integrated circuit is supplied to the pixel via the data line. That is, according to the present invention, since the data lines are driven while sharing the data lines, additional lines are not formed in the image display unit, and thus additional effects such as improvement of the aperture ratio and simplification of the process are generated.

Claims (10)

A light emitting element, A driver for supplying a pixel current corresponding to a data signal supplied from a data line to the light emitting device; A first switching block disposed between the driving unit and the data line and turned on for a first period of one horizontal period; A second switching block disposed between the driving unit and the common terminal of the light emitting device and the data line and turned off during the first period, And the first switching block and the second switching block are alternately turned on and off at least once during a second period except the first period of the first horizontal period. The method of claim 1, And the data signal is supplied to the driver when the first switching block is turned on, and the pixel current is supplied to the data line when the second switching block is turned on. The method of claim 2, A first scanning signal connected to the first switching block, wherein the first scanning block is turned on during the first period and turned on and off at least once during the second period, to the first switching block; A first scanning line for supplying; A second scan signal connected to the second switching block so that the second switching block is turned off for the first period and alternately turned on and off with the first switching block for the second period; And a second scan line for supplying to the second switching block. The method of claim 3, wherein And the first switching block includes at least one transistor. The method of claim 4, wherein The first switching block is A first transistor controlled by the first scan line and connected between the data line and the driver; A second transistor controlled by the second scan line and connected between the first transistor and the driving unit, And a drain electrode and a source electrode of the second transistor are electrically connected to each other. The method of claim 4, wherein The first switching block is At least one PMOS conductive type transistor controlled by the first scan line, And at least one NMOS conductive second transistor connected to the first transistor in the form of a transmission gate and controlled by the second scan line. The method of claim 3, wherein And the second switching block includes at least one transistor. The method of claim 1, The driving unit A capacitor for charging a voltage corresponding to the data signal; And a transistor for supplying a pixel current corresponding to the voltage charged in the capacitor to the light emitting device. The method of claim 3, wherein Connected between the driving unit and the light emitting element and turned off during a period in which a first scan signal is supplied to the first switching block in response to a light emission control signal supplied from a light emission control line, and turned on for another period of time. A pixel further comprising a transistor. A plurality of first scan lines and second scan lines; A plurality of data lines formed in a direction crossing the first scan line and the second scan line; An image display unit including a plurality of pixels connected to the first scan line, the second scan line, and the data line; A scan driver which sequentially supplies a first scan signal to the first scan line and sequentially supplies a second scan signal to the second scan line; It is connected to the data lines to supply a first gray voltage to the data lines as data signals, and a pixel current flowing in each of the pixels is fed back through the data lines to increase or decrease the voltage value of the first gray voltage. A data driver configured to supply a second gray level voltage to the pixels via the data line, The light emitting display device of claim 1, wherein the pixel is a pixel according to claim 1.

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