CN113936586B - Pixel driving circuit and display panel - Google Patents

Pixel driving circuit and display panel Download PDF

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Publication number
CN113936586B
CN113936586B CN201910816892.5A CN201910816892A CN113936586B CN 113936586 B CN113936586 B CN 113936586B CN 201910816892 A CN201910816892 A CN 201910816892A CN 113936586 B CN113936586 B CN 113936586B
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transistor
terminal
module
signal
control
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CN113936586A (en
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黄飞
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Chengdu Vistar Optoelectronics Co Ltd
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Chengdu Vistar Optoelectronics Co Ltd
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Priority to CN201910816892.5A priority Critical patent/CN113936586B/en
Priority to KR1020227003268A priority patent/KR102593643B1/en
Priority to PCT/CN2020/086034 priority patent/WO2021036299A1/en
Publication of CN113936586A publication Critical patent/CN113936586A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Abstract

The embodiment of the invention discloses a pixel driving circuit and a display panel. The pixel driving circuit includes: the driving module is used for driving the light-emitting device to emit light; the data writing module is used for writing a data signal into the storage module, and the storage module is used for adjusting the time for writing a first power supply signal and a second power supply signal into the control end of the driving module according to the data signal and maintaining the potential of the control end of the driving module; and the interference filtering module is used for filtering interference signals in the electric signals transmitted to the control end of the driving module. Compared with the prior art, the embodiment of the invention is beneficial to avoiding the problem that the light emitting device cannot stably emit light or the light emitting device is weakened after an effective data signal is interfered, and is beneficial to ensuring the continuous and stable light emitting of the light emitting device, thereby improving the stability of the pixel driving circuit.

Description

Pixel driving circuit and display panel
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a pixel driving circuit and a display panel.
Background
With the continuous development of display technologies, the application range of display panels is wider and wider, and people have higher and higher requirements on the display panels.
The pixel driving circuit in the display panel plays a very important role in driving the light emitting device to stably emit light. However, the performance of the conventional pixel driving circuit is not ideal enough, and the stability is poor.
Disclosure of Invention
The embodiment of the invention provides a pixel driving circuit and a display panel, which are used for improving the stability of the pixel driving circuit.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a pixel driving circuit comprising:
the driving module is used for driving the light-emitting device to emit light;
the data writing module is used for writing a data signal into the storage module, and the storage module is used for adjusting the time for writing a first power signal and a second power signal into the control end of the driving module according to the data signal and maintaining the potential of the control end of the driving module;
and the interference filtering module is used for filtering interference signals in the electric signals transmitted to the control end of the driving module.
According to the technical scheme, the interference filtering module is arranged in the pixel driving circuit and is used for filtering interference signals in the electric signals transmitted to the control end of the driving module, so that the transmission quality and stability of the electric signals transmitted to the control end of the driving module are improved, the potential of the control end of the driving module is not easily influenced by the interference signals, the stability is good, the problem that the light emitting device is unstable or weak in light emitting after effective data signals are interfered is solved, the stability of the pixel driving circuit is improved, and the continuous and stable light emitting of the light emitting device is ensured. In addition, when the display panel is subjected to factory tests such as reliability tests and the like, the pixel driving circuit can keep stable working performance under the influence of more interference, so that the yield and the competitiveness of the display panel are improved.
Furthermore, the signal input end of the interference filtering module is electrically connected with the driving signal output end of the storage module, and the signal output end of the interference filtering module is electrically connected with the control end of the driving module.
Further, the interference filtering module includes: the input end of the first signal path and the input end of the second signal path are short-circuited and then serve as the signal input end of the interference filtering module, the output end of the first signal path and the output end of the second signal path are short-circuited and then serve as the signal output end of the interference filtering module, and the first signal path and the second signal path are alternately conducted.
In order to maintain the light emitting device to emit light, the electrical signal output by the storage module and transmitted to the control terminal of the driving module is kept constant for a certain period of time, and the frequency of the interference signal is higher than that of the effective signal. The first signal path and the second signal path are alternately conducted, namely the first signal path and the second signal path form a chopper circuit, the electric signal output by the storage module and transmitted to the control end of the driving module is alternately output to the control end of the driving module through the first signal path and the second signal path, and interference signals can be coupled and filtered in the alternating process.
Further, the first signal path includes a first transistor and a second transistor, a first terminal of the first transistor is used as an input terminal of the first signal path, a second terminal of the first transistor is electrically connected with a first terminal of the second transistor, and a second terminal of the second transistor is used as an output terminal of the first signal path; the second signal path includes a third transistor and a fourth transistor, a first terminal of the third transistor is used as an input terminal of the second signal path, a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a second terminal of the first transistor, and a second terminal of the fourth transistor is used as an output terminal of the second signal path.
The embodiment of the invention can realize the following beneficial effects by setting as follows: on the first hand, due to the capacitance filtering effect of the first transistor, the second transistor, the third transistor and the fourth transistor, noise interference in the electric signal transmitted to the control end of the driving module is filtered, and the transmission quality of the electric signal transmitted to the control end of the driving module is improved; in a second aspect, because more pixels need to be arranged in the display area of the display panel, the space reserved for the pixel driving circuit is limited, and the interference filtering module has a simple structure and is beneficial to improving the aperture opening ratio of the display panel; in a third aspect, each transistor can be prepared in the same preparation process with other transistors in the pixel driving circuit, which is beneficial to reducing the preparation difficulty and thus is beneficial to reducing the cost of the pixel driving circuit; in the fourth aspect, the control method for alternately conducting the transistors is simple, and the control cost is favorably reduced.
Furthermore, at least one of the control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor is connected to a first clock signal, at least one of the control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor is connected to a second clock signal, and the first clock signal and the second clock signal have the same frequency and opposite potentials; or the control end of the first transistor, the control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor are connected to a first clock signal after being short-circuited. Because the first clock signal and the second clock signal are both high and low potential changing signals and have higher changing frequency, the first signal path and the second signal path have higher alternating conducting frequency, which is more favorable for filtering out high-frequency interference signals in the electric signals transmitted to the control end of the driving module, and interference signals in the electric signals transmitted to the control end of the driving module are mainly high-frequency interference signals.
Further, the pixel driving circuit further includes: the first reset module is used for resetting the control end of the driving module;
preferably, the control end of the first reset module is connected to a reset signal, the first end of the first reset module is connected to a first power signal, and the second end of the first reset module is electrically connected to the driving signal output end of the memory module.
The embodiment of the invention avoids the phenomenon that the electric signal potential transmitted to the control end of the driving module is influenced by the previous frame to cause abnormal light emitting of the light emitting device when two frames of pictures of the display panel are switched, and further improves the stability of the pixel driving circuit and the display effect of the display panel.
Further, the pixel driving circuit further includes: the second reset module is used for resetting the first end of the light-emitting device;
preferably, the control terminal of the second reset module is connected to a reset signal, the first terminal of the second reset module is electrically connected to the first terminal of the light emitting device, and the second terminal of the second reset module is electrically connected to the second terminal of the light emitting device.
The embodiment of the invention avoids the phenomenon that the light emitting device emits light abnormally due to the influence of the previous frame on the electric potential of the first end of the light emitting device when the two frames of pictures of the display panel are switched, and further improves the stability of the pixel driving circuit and the display effect of the display panel.
Furthermore, a control end of the data writing module is connected to a scanning signal, a first end of the data writing module is connected to the data signal, a second end of the data writing module is electrically connected to a data signal input end of the storage module, a first power signal input end of the storage module is connected to the first power signal, and a second power signal input end of the storage module is connected to the second power signal.
Further, the memory module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the first end of the fifth transistor and the first end of the sixth transistor are short-circuited and then serve as a first power signal input end of the storage module, the control end of the fifth transistor, the second end of the sixth transistor, the control end of the seventh transistor and the first end of the eighth transistor are short-circuited and then serve as a data signal input end of the storage module, the second end of the fifth transistor, the control end of the sixth transistor, the first end of the seventh transistor and the control end of the eighth transistor are short-circuited and then serve as a driving signal output end of the storage module, and the second end of the seventh transistor and the second end of the eighth transistor are short-circuited and then serve as a second power signal input end of the storage module.
Accordingly, the present invention also provides a display panel comprising: the display panel further comprises a plurality of scanning lines and a plurality of data lines, the pixel driving circuits are arranged in spaces formed by the scanning lines and the data lines in a crossed mode, the control ends of the data writing modules are electrically connected with the corresponding scanning lines, and the first ends of the data writing modules are electrically connected with the data lines.
According to the embodiment of the invention, the interference filtering module is arranged in the pixel driving circuit and is used for filtering the interference signal in the electric signal transmitted to the control end of the driving module, so that the transmission quality and stability of the electric signal transmitted to the control end of the driving module are improved, the electric potential of the control end of the driving module is not easily influenced by the interference signal, the stability is better, the problem that the light emitting device is unstable or weakened to emit light after an effective data signal is interfered is solved, the stability of the pixel driving circuit is favorably improved, and the continuous and stable light emitting of the light emitting device is further ensured. In addition, when the display panel is subjected to factory tests such as reliability tests and the like, the pixel driving circuit can keep stable working performance under more interference, so that the yield and the competitiveness of the display panel are improved.
Drawings
Fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a driving timing sequence of a pixel driving circuit according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It is to be further noted that, for the convenience of description, only a part of the structure relating to the present invention is shown in the drawings, not the whole structure.
As described in the background art, the conventional pixel driving circuit has a problem of poor stability, and the inventors have found that the problem is caused by the fact that a plurality of parasitic resistance capacitors exist in a signal transmission path, so that an effective data signal is easily interfered, and a light emitting device has a phenomenon of unstable light emission or reduced light emission, so that the conventional pixel driving circuit has a problem of poor stability.
In view of the above, embodiments of the present invention provide a pixel driving circuit. The pixel driving circuit can be used for driving Light Emitting devices such as Micro Light Emitting diodes (Micro-LED/mu LED) or Organic Light Emitting Diodes (OLED). And the pixel driving circuit can adopt a digital driving method to control the brightness of the light-emitting device.
Fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention. Referring to fig. 1, the pixel driving circuit includes: the device comprises a driving module 10, a data writing module 20, a storage module 30 and an interference filtering module 40. The driving module 10 is used for driving the light emitting device LED to emit light; the DATA writing module 20 is configured to write the DATA signal DATA into the storage module 30, and the storage module 30 is configured to adjust a time for writing the first power signal VDD and the second power signal VSS into the control terminal A1 of the driving module 10 according to the DATA signal DATA, and maintain a potential of the control terminal A1 of the driving module 10; the interference filtering module 40 is configured to filter an interference signal from the electrical signal transmitted to the control terminal A1 of the driving module 10.
The driving module 10 refers to a circuit module for driving the light emitting device LED to emit light, for example, the driving module 10 is controlled by the output signal of the storage module 30 to transmit a driving signal to the light emitting device LED, where the driving signal may be a current driving signal or a voltage driving signal. Illustratively, in the digital driving method, the magnitude of the driving signal is constant, the gray scale displayed by the light emitting device LED depends on the sustain time of the driving signal, and the longer the sustain time of the driving signal, the higher the gray scale displayed by the light emitting device LED; conversely, the shorter the sustain time of the driving signal is, the lower the gray scale displayed by the light emitting device LED is, thereby realizing control of different gray scales.
The DATA writing block 20 refers to a circuit block for writing the DATA signal DATA to the pixel driving circuit. Illustratively, the DATA writing module 20 is controlled by the SCAN signal SCAN to transmit the DATA signal DATA to the memory module 30, and the pulse width of the DATA signal DATA determines the width of the signal output by the memory module 30, i.e., the sustain time of the first power signal VDD and the second power signal VSS, and further determines the sustain time of the driving signal.
The memory module 30 maintaining the potential of the control terminal A1 of the driving module 10 means that the memory module 30 can maintain the potentials of the output signals, i.e. the potentials of the first power signal VDD and the second power signal VSS, and further maintain the potential of the control terminal A1 of the driving module 10 until the potential of the DATA signal DATA written by the DATA writing module 20 changes.
The interference filtering module 40 is a circuit module for filtering an interference signal in an electrical signal transmitted to the control terminal A1 of the driving module 10, that is, the interference filtering module can filter an interference signal in the first power signal VDD or the second power signal VSS, and because the time for writing the first power signal VDD and the second power signal VSS into the control terminal A1 of the driving module 10 depends on the data signal written by the data writing module 20, the interference filtering module 40 can also eliminate interference of the interference signal in the data signal written by the data writing module 20 on the first power signal VDD or the second power signal VSS output from the storage module 30 to the control terminal A1 of the driving module 10, so as to improve the potential stability of the control terminal A1 of the driving module 10, and further improve the working stability of the pixel driving circuit.
According to the embodiment of the invention, the interference filtering module 40 is arranged in the pixel driving circuit, and the interference filtering module 40 is used for filtering the interference signal in the electric signal transmitted to the control end A1 of the driving module 10, so that the transmission quality and stability of the electric signal transmitted to the control end A1 of the driving module 10 are improved, the potential of the control end A1 of the driving module 10 is not easily influenced by the interference signal, the stability is better, the problem that the light emitting of the light emitting device LED is unstable or weakened after the effective DATA signal DATA is interfered is solved, the stability of the pixel driving circuit is favorably improved, and the continuous and stable light emitting of the light emitting device LED is further ensured. In addition, when the display panel is subjected to factory tests such as reliability tests and the like, the DATA signal DATA can keep stable working performance even if being interfered by a lot, so that the yield and the competitiveness of the display panel are improved.
With reference to fig. 1, optionally, the signal input end D1 of the interference filtering module 40 is electrically connected to the driving signal output end C3 of the storage module 30, and the signal output end D2 of the interference filtering module 40 is electrically connected to the control end A1 of the driving module 10, that is, the interference filtering module 40 is connected in series between the storage module 30 and the driving module 10, so that before the control end A1 of the driving module 10 inputs an electrical signal, an interference signal in the electrical signal is filtered, and the potential stability of the control end A1 input to the driving module 10 is improved.
Fig. 2 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention. Referring to fig. 2, on the basis of the foregoing embodiments, optionally, the interference filtering module 40 includes: the signal input end D1-1 of the first signal path 401 and the input end D2-1 of the second signal path 402 are short-circuited and then serve as the signal input end D1 of the interference filtering module 40, the output end D1-2 of the first signal path 401 and the output end D2-2 of the second signal path 402 are short-circuited and then serve as the signal output end D2 of the interference filtering module 40, and the first signal path 401 and the second signal path 402 are alternately conducted.
In order to maintain the light emitting device LED to emit light, the effective signal of the electrical signal output by the storage module 30 and transmitted to the control terminal A1 of the driving module 10 is kept constant for a certain period of time, and the frequency of the interference signal is higher than that of the effective signal. The first signal path 401 and the second signal path 402 are alternately turned on, that is, the first signal path 401 and the second signal path 402 form a chopper circuit, the electric signal output by the storage module 30 and transmitted to the control terminal A1 of the driving module 10 is alternately output to the control terminal A1 of the driving module 10 through the first signal path 401 and the second signal path 402, and the interference signal can be coupled and filtered out in the alternating process.
The first signal path 401 and the second signal path 402 may be arranged in various ways, and some of them will be described below, but the present invention is not limited thereto.
With continued reference to fig. 2, based on the above embodiments, optionally, the first signal path 401 includes a thirteenth transistor M13, a first terminal of the thirteenth transistor M13 is used as the input terminal D1-1 of the first signal path 401, and a second terminal of the thirteenth transistor M13 is used as the output terminal D1-2 of the first signal path 401. The second signal path 402 includes a fourteenth transistor M14, a first terminal of the fourteenth transistor M14 is an input terminal D2-1 of the second signal path 402, and a second terminal of the fourteenth transistor M14 is an output terminal D2-2 of the second signal path 402.
The embodiment of the invention can realize the following beneficial effects by setting as follows: on the first hand, the thirteenth transistor M13 and the fourteenth transistor M14 respectively form a single-tube transmission gate, and due to the capacitance filtering function of the single-tube transmission gate, noise interference in the electrical signal transmitted to the control end A1 of the driving module 10 is filtered out, so that the transmission quality of the electrical signal transmitted to the control end A1 of the driving module 10 is improved; in the second aspect, because more pixels need to be arranged in the display area of the display panel, the space reserved for the pixel driving circuit is limited, and the interference filtering module has a simple structure and is beneficial to improving the aperture opening ratio of the display panel; in a third aspect, the thirteenth transistor M13 and the fourteenth transistor M14 can be fabricated in the same fabrication process as other transistors in the pixel driving circuit, which is beneficial to reducing the fabrication difficulty, thereby being beneficial to reducing the cost of the pixel driving circuit; in the fourth aspect, the control method for controlling the thirteenth transistor M13 and the fourteenth transistor M14 to be turned on alternately is simple, which is beneficial to reducing the control cost.
Alternatively, the channel types of the thirteenth transistor M13 and the fourteenth transistor M14 are different, and the control terminal of the thirteenth transistor M13 and the control terminal of the fourteenth transistor M14 are connected to the first clock signal CK. The first clock signal CK is a signal with alternating high and low potentials, and the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on alternately under the control of the first clock signal CK. The thirteenth transistor M13 is an N-type transistor, and the fourteenth transistor M14 is a P-type transistor; alternatively, the thirteenth transistor M13 is an N-type transistor and the fourteenth transistor M14 is a P-type transistor. Fig. 2 exemplarily shows a case where the tenth transistor M13 is an N-type transistor and the fourteenth transistor M14 is a P-type transistor. Under the potential control of the first clock signal CK which is alternately changed, the thirteenth transistor M13 and the fourteenth transistor M14 are alternately turned on to transmit an electrical signal to the control terminal A1 of the driving module 10.
Fig. 3 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention. Referring to fig. 3, on the basis of the foregoing embodiments, optionally, the first signal path 401 includes a first transistor M1 and a second transistor M2, a first terminal of the first transistor M1 is used as the input terminal D1-1 of the first signal path 401, a second terminal of the first transistor M1 is electrically connected to a first terminal of the second transistor M2, and a second terminal of the second transistor M2 is used as the output terminal D1-2 of the first signal path 401. The second signal path 402 includes a third transistor M3 and a fourth transistor M4, a first terminal of the third transistor M3 is used as an input terminal D2-1 of the second signal path 402, a second terminal of the third transistor M3 is electrically connected to a first terminal of the fourth transistor M4 and a second terminal of the first transistor M1, and a second terminal of the fourth transistor M4 is used as an output terminal D2-2 of the second signal path 402.
The embodiment of the invention can realize the following beneficial effects by the arrangement: on the first hand, due to the capacitance filtering effect of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, noise interference in the electrical signal transmitted to the control end A1 of the driving module 10 is filtered out, and the transmission quality of the electrical signal transmitted to the control end A1 of the driving module 10 is improved; in a second aspect, because more pixels need to be arranged in the display area of the display panel, the space reserved for the pixel driving circuit is limited, and the interference filtering module has a simple structure and is beneficial to improving the aperture opening ratio of the display panel; in a third aspect, each transistor can be prepared in the same preparation process with other transistors in the pixel driving circuit, which is beneficial to reducing the preparation difficulty and thus the cost of the pixel driving circuit; in the fourth aspect, the control method for alternately turning on each transistor is simple, and is beneficial to reducing the control cost.
In the above embodiments, there are various control methods for the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, and several of them will be described below, but the present invention is not limited thereto.
With reference to fig. 3, optionally, the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, and the control end of the fourth transistor M4 are shorted and then the first clock signal CK is connected. Specifically, the first clock signal CK controls the first transistor M1 and the second transistor M2 to be turned on simultaneously, and controls the third transistor M3 and the fourth transistor M4 to be turned off simultaneously; alternatively, the first clock signal CK controls the first transistor M1 and the second transistor M2 to be turned off at the same time, and controls the third transistor M3 and the fourth transistor M4 to be turned on at the same time. Therefore, it is necessary to set the channel types of the first transistor M1 and the second transistor M2 to be the same, the channel types of the third transistor M3 and the fourth transistor M4 to be the same, and the channel types of the third transistor M3 and the first transistor M1 to be different.
Illustratively, the first transistor M1 and the second transistor M2 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors; alternatively, the first transistor M1 and the second transistor M2 are both P-type transistors, and the third transistor M3 and the fourth transistor M4 are both N-type transistors.
Fig. 3 exemplarily shows that the first transistor M1 and the second transistor M2 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors. The first clock signal CK is a signal with alternating high and low electrical potentials, so as to control the first signal path 401 and the second signal path 402 formed by the first transistor M1 and the second transistor M2 to be alternately turned on, the first signal path 401 and the second signal path 402 alternately transmit electrical signals to the control terminal A1 of the driving module 10, that is, the first signal path 401 and the second signal path 402 form a chopper circuit, the electrical signals output by the memory module 30 and transmitted to the control terminal A1 of the driving module 10 are alternately output to the control terminal A1 of the driving module 10 through the first signal path 401 and the second signal path 402, and interference signals can be coupled and filtered in an alternating process. Further, since the frequency of the potential change of the first clock signal CK is higher, the frequency of the alternate conduction of the first signal path 401 and the second signal path 402 is higher, which is more favorable for filtering the high-frequency interference signal in the electrical signal transmitted to the control terminal A1 of the driving module 10, and the interference signal in the electrical signal transmitted to the control terminal A1 of the driving module 10 is mainly the high-frequency interference signal, so that the filtering effect of the interference signal in the electrical signal transmitted to the control terminal A1 of the driving module 10 is further improved in the embodiment of the present invention. In addition, the on and off states of the plurality of transistors are controlled by the first clock signal line, which is beneficial to reducing the number of the clock signal lines.
Optionally, at least one of the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, and the control end of the fourth transistor M4 is connected to the first clock signal CK, at least one of the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, and the control end of the fourth transistor M4 is connected to the second clock signal CKB, and the first clock signal CK and the second clock signal CKB have the same frequency and opposite potentials.
Fig. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the invention. Referring to fig. 4, the first transistor M1 and the third transistor M3 are both N-type transistors, and the second transistor M2 and the fourth transistor M4 are both P-type transistors, for example. Illustratively, when the first clock signal CK is at a high level and the second clock signal CKB is at a low level, the first clock signal is transmitted to the control terminal A1 of the driving module 10 through the first signal path 401 formed by the first transistor M1 and the second transistor M2; when the first clock signal CK is at a low level and the second clock signal CKB is at a high level, the electrical signal is transmitted to the control terminal A1 of the driving module 10 through the second signal path 402 formed by the third transistor M3 and the fourth transistor M4. Because the channel types of the first transistor M1 and the second transistor M2 in the first signal path 401 are different, and the channel types of the third transistor M3 and the fourth transistor M4 in the second signal path 402 are different, in the process of turning on and off the first signal path 401, the characteristics of the first transistor M1 and the second transistor M2 are complementary, and the characteristic curves of the first transistor M1 and the second transistor M2 have cross points (operating balance points), which is beneficial for the first transistor M1 and the second transistor M2 to operate at the balance points, thereby being beneficial for reducing the leakage current of the transistors and further improving the stability of the pixel driving circuit. Similarly, during the on and off processes of the second signal path 402, the characteristics of the third transistor M3 and the fourth transistor M4 are complementary, so as to improve the stability of the pixel driving circuit.
Referring to fig. 2 to 4, on the basis of the foregoing embodiments, optionally, the pixel driving circuit further includes: the first reset module 50, the first reset module 50 is used for resetting the control terminal A1 of the driving module 10, so as to avoid the phenomenon that the electric potential transmitted to the control terminal A1 of the driving module 10 is influenced by the previous frame to cause abnormal light emission of the light emitting device LED when the two frames of pictures of the display panel are switched, and to facilitate the improvement of the stability of the pixel driving circuit and the display effect of the display panel.
With continued reference to fig. 2 to fig. 4, optionally, the control terminal E1 of the first Reset module 50 is connected to the Reset signal Reset, the first terminal E2 of the first Reset module 50 is connected to the first power signal VDD, and the second terminal E3 of the first Reset module 50 is electrically connected to the driving signal output terminal C3 of the memory module 30. Since the first power signal VDD is relatively stable, the control terminal A1 of the driving module 10 is reset by the first power signal VDD, which is beneficial to further improving the stability of the pixel driving circuit.
With continued reference to fig. 2-4, optionally, the first reset module 50 includes an eleventh transistor MA1, a control terminal of the eleventh transistor MA1 serves as the control terminal E1 of the first reset module 50, a first terminal of the eleventh transistor MA1 serves as the first terminal E2 of the first reset module 50, and a second terminal of the eleventh transistor MA1 serves as the second terminal E3 of the first reset module 50. The first reset module 50 is arranged in such a way, so that the tenth transistor MA1 and other transistors in the pixel driving circuit can be conveniently prepared in the same preparation process, thereby being beneficial to reducing the preparation difficulty and further being beneficial to reducing the cost of the pixel driving circuit; in addition, the control method of the eleventh transistor MA1 is simple, which is beneficial to reducing the control cost.
With reference to fig. 2 to 4, on the basis of the foregoing embodiments, optionally, the pixel driving circuit further includes a second reset module 60, where the second reset module 60 is configured to reset the first end of the light emitting device LED, so as to avoid a phenomenon that the light emitting device LED emits light abnormally due to the influence of the potential of the first end of the light emitting device LED from the previous frame when two frames of the display panel are switched, and further improve the stability of the pixel driving circuit and the display effect of the display panel.
With continued reference to fig. 2 to fig. 4, optionally, the control terminal F1 of the second Reset module 60 is connected to the Reset signal Reset, the first terminal F2 of the second Reset module 60 is electrically connected to the first terminal G1 of the light emitting device LED, and the second terminal F3 of the second Reset module 60 is electrically connected to the second terminal G2 of the light emitting device LED, that is, the second Reset module 60 is connected to the light emitting device LED in parallel. Because the second reset module 60 is connected in parallel with the light emitting device LED, when the second reset module 60 is turned on, the first end G1 and the second end G2 of the light emitting device LED are short-circuited, so that the phenomenon that the light emitting device LED emits light abnormally due to the influence of the previous frame on the electric potential of the first end of the light emitting device LED when two frames of pictures of the display panel are switched is avoided, and the stability of the pixel driving circuit is further improved.
With continued reference to fig. 2-4, optionally, the second reset module 60 includes a twelfth transistor MA2, a control terminal of the twelfth transistor MA2 is used as the control terminal F1 of the second reset module 60, a first terminal of the twelfth transistor MA2 is used as the first terminal F2 of the second reset module 60, and a second terminal of the twelfth transistor MA2 is used as the second terminal F3 of the second reset module 60. The second reset module 60 is arranged in this way, so that the tenth transistor MA2 and other transistors in the pixel driving circuit can be prepared in the same preparation process, thereby being beneficial to reducing the preparation difficulty and reducing the cost of the pixel driving circuit; in addition, the control method of the twelfth transistor MA2 is simple, which is beneficial to reducing the control cost.
Referring to fig. 1 to 4, on the basis of the foregoing embodiments, optionally, the control terminal B1 of the DATA writing module 20 is connected to the SCAN signal SCAN, the first terminal B2 of the DATA writing module 20 is connected to the DATA signal DATA, the second terminal B3 of the DATA writing module 20 is electrically connected to the DATA signal input terminal C2 of the memory module 30, the first power signal input terminal C1 of the memory module 30 is connected to the first power signal VDD, and the second power signal input terminal C4 of the memory module 30 is connected to the second power signal VSS.
Referring to fig. 2-4, on the basis of the above embodiments, optionally, the memory module 30 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; a first end of the fifth transistor M5 and a first end of the sixth transistor M6 are shorted to serve as a first power signal input end C1 of the memory module 30, a control end of the fifth transistor M5, a second end of the sixth transistor M6, a control end of the seventh transistor M7, and a first end of the eighth transistor M8 are shorted to serve as a data signal input end C2 of the memory module 30, a second end of the fifth transistor M5, a control end of the sixth transistor M6, a first end of the seventh transistor M7, and a control end of the eighth transistor M8 are shorted to serve as a driving signal output end C3 of the memory module 30, and a second end of the seventh transistor M7 and a second end of the eighth transistor M8 are shorted to serve as a second power signal input end C4 of the memory module 30.
Among them, the fifth transistor M5 and the seventh transistor M7 are different in type, and the sixth transistor M6 and the eighth transistor M8 are different in type. The fifth transistor M5 and the seventh transistor M7 constitute the first inverter 38, the control terminals of the fifth transistor M5 and the seventh transistor M7 are the inverting input terminal H1 of the first inverter 38, and the second terminal of the fifth transistor M5 and the first terminal of the seventh transistor M7 are the inverting output terminal H2 of the first inverter 38. Similarly, the sixth transistor M6 and the eighth transistor M8 form the second inverter 39, the control terminals of the sixth transistor M6 and the eighth transistor M8 are the inverting input terminal J1 of the second inverter 39, and the second terminal of the sixth transistor M6 and the first terminal of the eighth transistor M8 are the inverting output terminal J2 of the second inverter 39. The inverting input terminal H1 of the first inverter 38 is electrically connected to the inverting output terminal J2 of the second inverter 39, and the inverting output terminal H2 of the first inverter 38 is electrically connected to the inverting input terminal J1 of the second inverter 39, that is, the first inverter 38 and the second inverter 39 form an anti-parallel connection relationship, thereby forming the storage module 30.
With continued reference to fig. 2-4, optionally, the data writing module 20 includes a ninth transistor M9, a control terminal of the ninth transistor M9 is used as the control terminal B1 of the data writing module 20, a first terminal of the ninth transistor M9 is used as the first terminal B2 of the data writing module 20, and a second terminal of the ninth transistor M9 is used as the second terminal B3 of the data writing module 20. The driving module 10 includes a tenth transistor M10, a control terminal of the tenth transistor M10 is used as the control terminal A1 of the driving module 10, a first terminal of the tenth transistor M10 is used as the first terminal A2 of the driving module 10, and a second terminal of the tenth transistor M10 is used as the second terminal A3 of the driving module 10.
Fig. 5 is a schematic diagram of a driving timing sequence of a pixel driving circuit according to an embodiment of the invention. Referring to fig. 5, the driving timing of the pixel driving circuit illustratively includes: a first stage T1, a second stage T2 and a third stage T3. The second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the eleventh transistor MA1, and the twelfth transistor MA2 are P-type transistors, the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 are N-type transistors, the first power signal VDD is high, and the second power signal VSS is low.
In the first stage T1, the Reset signal Reset is at a low voltage level, the first clock signal CK is at a low voltage level, the second clock signal CKB is at a high voltage level, the DATA signal DATA is at a low voltage level, and the SCAN signal SCAN is at a high voltage level. The eleventh transistor MA1 is turned on in response to a low level of the Reset signal Reset, and the first power signal VDD is input to the control terminal of the tenth transistor M10 and the driving signal output terminal C3 of the memory module 30. The eleventh transistor MA1 performs reset initialization on the control terminal of the tenth transistor M10, and since the memory module has a bidirectional transmission function, the eleventh transistor MA1 performs reset initialization on the memory module 30, the sixth transistor M6 is turned off in response to a high level of the first power signal VDD, the eighth transistor M8 is turned on in response to a high level of the first power signal VDD, the second power signal VSS is output to the control terminals of the fifth transistor M5 and the seventh transistor M7, and the driving signal output terminal C3 of the memory module 30 maintains the high level output of the first power signal VDD. The tenth transistor M10 is turned off in response to a high potential of the electrical signal transmitted to the control terminal A1 of the driving module 10. The twelfth transistor MA2 is turned on in response to a low potential of the Reset signal Reset, and inputs the second power signal VSS to the first terminal of the light emitting device LED, and the first terminal and the second terminal of the light emitting device LED have the same potential, so that the first terminal of the light emitting device LED is initialized and the light emitting device LED maintains a non-light emitting state.
In the second stage T2, the Reset signal Reset is at a high level, the first clock signal CK is at a high level, the second clock signal CKB is at a low level, the DATA signal DATA is at a high level, and the SCAN signal SCAN is at a low level. The eleventh transistor MA1 and the twelfth transistor MA2 are turned off in response to the high potential of the Reset signal Reset. The ninth transistor M9 is turned on in response to the low level of the SCAN signal SCAN, and transmits the high level of the DATA signal DATA to the driving signal output terminal C3 of the memory module 30, the memory module 30 latches the DATA signal DATA and outputs the low level of the second power signal VSS, the first transistor M1 is turned on in response to the high level of the first clock signal CK, the second transistor M2 is turned on in response to the low level of the second clock signal CKB, the third transistor M3 is turned off in response to the low level of the second clock signal CKB, the fourth transistor M4 is turned off in response to the high level of the first clock signal CK, the low level of the second power signal VSS is transmitted to the control terminal of the tenth transistor M10 through the first transistor M1 and the second transistor M2, and the tenth transistor M10 is turned on in response to the low level of the second power signal VSS, and outputs the driving current to drive the light emitting device LED to emit light.
In the third stage T3, the Reset signal Reset is at a high level, the first clock signal CK is at a high level and the second clock signal CKB is at a low level alternately, the first clock signal CK and the second clock signal CKB are at opposite levels, the DATA signal DATA is at a low level, and the SCAN signal SCAN is at a high level. The eleventh transistor MA1 and the twelfth transistor MA2 are turned off in response to a high potential of the Reset signal Reset. The ninth transistor M9 is turned off in response to the high level of the SCAN signal SCAN, and the memory module 30 latches the DATA signal DATA of the second stage T2 and continues to output the low level of the second power signal VSS. The first signal path 401 and the second signal path 402 are alternately turned on, the second power signal VSS is alternately transmitted to the control terminal of the tenth transistor M10 through the first signal path 401 and the second signal path 402, and the tenth transistor M10 is turned on in response to a low potential of the second power signal VSS to output a driving current to drive the light emitting device LED to emit light.
The embodiment of the invention also provides a display panel. Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 6, the display panel includes a plurality of pixel driving circuits 1 according to any embodiment of the present invention, so that the display panel according to the embodiment of the present invention also has the advantages described in the above embodiments, and further description thereof is omitted here.
The display panel further includes: a plurality of scanning lines 2 and a plurality of data lines 3; a pixel driving circuit 1 is arranged in a space 4 formed by the intersection of the scanning line 2 and the data line 3; the control end of the data writing module is electrically connected with the corresponding scanning line 2, and the first end of the data writing module is electrically connected with the data line 3. The pixel driving circuit receives the scanning signal sent by the gate driving module 5 through the corresponding scanning line 2, and receives the data signal of the source driving circuit 6 through the corresponding data line 3, so that the display panel accordingly achieves the display function. Illustratively, the display panel may be an organic light emitting display panel.
Embodiments of the present invention further provide a display device, which includes a display panel provided in any embodiment of the present invention, where the display panel includes a plurality of pixel driving circuits 1 provided in any embodiment of the present invention. The display device may be a mobile phone, or may be an electronic device such as a computer or a wearable device, and the specific form of the display device is not limited in the embodiment of the present invention. The display device provided by the embodiment of the invention also has the beneficial effects described in the embodiments, and details are not repeated herein.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (12)

1. A pixel driving circuit, comprising:
the driving module is used for driving the light-emitting device to emit light;
the data writing module is used for writing a data signal into the storage module, and the storage module is used for adjusting the time for writing a first power signal and a second power signal into the control end of the driving module according to the data signal and maintaining the potential of the control end of the driving module;
and the interference filtering module is used for filtering interference signals in the electric signals transmitted to the control end of the driving module.
2. The pixel driving circuit according to claim 1, wherein a signal input terminal of the interference filtering module is electrically connected to a driving signal output terminal of the storage module, and a signal output terminal of the interference filtering module is electrically connected to a control terminal of the driving module.
3. The pixel driving circuit according to claim 2, wherein the interference filtering module comprises:
the input end of the first signal path and the input end of the second signal path are short-circuited and then serve as the signal input end of the interference filtering module, the output end of the first signal path and the output end of the second signal path are short-circuited and then serve as the signal output end of the interference filtering module, and the first signal path and the second signal path are alternately conducted.
4. The pixel driving circuit according to claim 3, wherein the first signal path comprises a first transistor and a second transistor, a first terminal of the first transistor is used as an input terminal of the first signal path, a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, and a second terminal of the second transistor is used as an output terminal of the first signal path;
the second signal path includes a third transistor and a fourth transistor, a first terminal of the third transistor is used as an input terminal of the second signal path, a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a second terminal of the first transistor, and a second terminal of the fourth transistor is used as an output terminal of the second signal path.
5. The pixel driving circuit according to claim 4, wherein at least one of the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor is connected to a first clock signal, at least one of the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor is connected to a second clock signal, and the first clock signal and the second clock signal have the same frequency and opposite potentials; alternatively, the first and second electrodes may be,
and the control end of the first transistor, the control end of the second transistor, the control end of the third transistor and the control end of the fourth transistor are connected with a first clock signal after being short-circuited.
6. The pixel driving circuit according to any one of claims 1-5, further comprising:
the first reset module is used for resetting the control end of the driving module.
7. The pixel driving circuit according to claim 6, wherein a control terminal of the first reset module is connected to a reset signal, a first terminal of the first reset module is connected to a first power signal, and a second terminal of the first reset module is electrically connected to the driving signal output terminal of the memory module.
8. The pixel driving circuit according to any one of claims 1-5, further comprising:
a second reset module for resetting the first end of the light emitting device.
9. The pixel driving circuit according to claim 8, wherein a control terminal of the second reset module is connected to a reset signal, a first terminal of the second reset module is electrically connected to a first terminal of the light emitting device, and a second terminal of the second reset module is electrically connected to a second terminal of the light emitting device.
10. The pixel driving circuit according to any of claims 1 to 5, wherein a control terminal of the data writing module is connected to a scan signal, a first terminal of the data writing module is connected to the data signal, a second terminal of the data writing module is electrically connected to a data signal input terminal of the memory module, a first power signal input terminal of the memory module is connected to the first power signal, and a second power signal input terminal of the memory module is connected to the second power signal.
11. The pixel driving circuit according to claim 10, wherein the memory block comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the first end of the fifth transistor and the first end of the sixth transistor are short-circuited and then serve as a first power signal input end of the storage module, the control end of the fifth transistor, the second end of the sixth transistor, the control end of the seventh transistor and the first end of the eighth transistor are short-circuited and then serve as a data signal input end of the storage module, the second end of the fifth transistor, the control end of the sixth transistor, the first end of the seventh transistor and the control end of the eighth transistor are short-circuited and then serve as a driving signal output end of the storage module, and the second end of the seventh transistor and the second end of the eighth transistor are short-circuited and then serve as a second power signal input end of the storage module.
12. A display panel, comprising a plurality of pixel driving circuits according to any one of claims 1 to 11, wherein the display panel further comprises a plurality of scanning lines and a plurality of data lines, the pixel driving circuits are disposed in spaces formed by crossing the scanning lines and the data lines, the control ends of the data writing modules are electrically connected to the corresponding scanning lines, and the first ends of the data writing modules are electrically connected to the data lines.
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