KR101935437B1 - Output driving circuit capable of decreasing noise, and semiconductor memory device including the same - Google Patents

Abstract

An output driver circuit capable of reducing noise of an output signal is disclosed. The output driver circuit includes a first buffer, a second buffer, a pull-up NMOS transistor, a pull-down NMOS transistor, and a noise remover. The first buffer buffers the first input signal to generate the first voltage signal, and the second buffer buffers the second input signal to generate the second voltage signal. The pull-up NMOS transistor couples the power supply voltage to the output node in response to the first voltage signal. The pull-down NMOS transistor couples the ground voltage to the output node in response to the second voltage signal. The noise eliminator reduces the noise of the output signal by forming a current path between the output node and the ground voltage when the pull-up NMOS transistor is on and the pull-down NMOS transistor is off. Therefore, the semiconductor memory device including the output driver circuit is insensitive to noise and has little data transmission error.

Description

TECHNICAL FIELD [0001] The present invention relates to an output driving circuit capable of reducing noise, and a semiconductor memory device including the output driving circuit. [0002]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including an output driving circuit capable of reducing noise.

In the semiconductor memory device, noise may be included in the output signal during data transfer. Research is underway to accurately transmit data without transmission errors.

An object of the present invention is to provide an output driver circuit capable of reducing noise of an output signal.

Another object of the present invention is to provide a semiconductor memory device including the output driving circuit.

According to an aspect of the present invention, there is provided an output driver circuit including a first buffer, a second buffer, a pull-up NMOS transistor, a pull-down NMOS transistor, and a noise eliminator.

The first buffer buffers the first input signal to generate a first voltage signal and outputs the first voltage signal to the first node. The second buffer buffers a second input signal having a phase opposite to the first input signal to generate a second voltage signal and outputs the second voltage signal to a second node. The pull-up NMOS transistor couples the power supply voltage to the output node in response to the first voltage signal. A pull-down NMOS transistor couples a ground voltage to the output node in response to the second voltage signal. The NMOS transistor is electrically connected to the first node, the second node, and the output node, and when the pull-up NMOS transistor is on and the pull-down NMOS transistor is off, Thereby reducing the noise of the output signal by forming a current path between the ground voltage.

According to one embodiment of the present invention, the noise eliminator may include a supplementary pull-up NMOS transistor, a supplementary pull-down NMOS transistor, a first drive control section, and a second drive control section.

The auxiliary pull-up NMOS transistor has a drain coupled to the supply voltage, and a source coupled to the output node. The auxiliary pull-down NMOS transistor has a source connected to a ground voltage, and a drain connected to the output node. A first drive control unit is electrically coupled to the first node and the second node and controls the auxiliary pull-up NMOS transistor. A second drive control section is electrically connected to the first node and the second node, and controls the auxiliary pull-down NMOS transistor.

According to an embodiment of the present invention, the magnitude of the current flowing through the auxiliary pull-down NMOS transistor when the pull-up NMOS transistor is in the ON state is the pull-down May be less than the magnitude of the current flowing through the NMOS transistor.

According to one embodiment of the present invention, in the semiconductor integrated circuit, the size of the auxiliary pull-down NMOS transistor may be smaller than the size of the pull-down NMOS transistor.

According to an embodiment of the present invention, the first drive control unit may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor.

The first PMOS transistor has a source and a gate connected in common to the first node, and a drain connected to the gate of the auxiliary pull-up NMOS transistor. The first NMOS transistor has a gate coupled to the first node, a drain coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor. The second PMOS transistor has a source and a gate connected in common to the second node, and a drain connected to the gate of the auxiliary pull-up NMOS transistor. The second NMOS transistor has a drain coupled to the first node, a gate coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor.

According to an embodiment of the present invention, the second drive control unit may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor.

The first PMOS transistor has a source coupled to the first node, a gate coupled to the second node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The first NMOS transistor has a gate and a drain commonly connected to the second node, and a source coupled to the gate of the auxiliary pull-down NMOS transistor. The second PMOS transistor has a source coupled to the second node, a gate coupled to the first node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The second NMOS transistor has a drain and a gate connected in common to the first node, and a source coupled to a gate of the auxiliary pull-down NMOS transistor.

According to one embodiment of the present invention, the noise canceller may include an auxiliary pull-down NMOS transistor and a drive control unit.

The auxiliary pull-down NMOS transistor has a source connected to a ground voltage, and a drain connected to the output node. A drive control unit is electrically connected to the first node and the second node, and controls the auxiliary pull-down NMOS transistor.

According to an embodiment of the present invention, the driving control unit may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor. The first PMOS transistor has a source coupled to the first node, a gate coupled to the second node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The first NMOS transistor has a gate and a drain commonly connected to the second node, and a source coupled to the gate of the auxiliary pull-down NMOS transistor. The second PMOS transistor has a source coupled to the second node, a gate coupled to the first node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The second NMOS transistor has a drain and a gate connected in common to the first node, and a source coupled to a gate of the auxiliary pull-down NMOS transistor.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array that operates in response to a word line enable signal and a column select signal, an address input buffer, a row decoder, a column decoder, an input / output sense amplifier, Circuits, and output circuits.

The address input buffer generates a row address signal and a column address signal based on the external address. The row decoder decodes the row address signal to generate a word line enable signal. The column decoder decodes the column address signal to generate a column select signal. An input / output sense amplifier amplifies data output from the memory cell array to generate first data, and transmits data input from the outside to the memory cell array. The output circuit includes a pull-up NMOS transistor and a pull-down NMOS transistor, and when the pull-up NMOS transistor is on and the pull-down NMOS transistor is off, a current path between the output node and the ground voltage Thereby reducing the noise of the output signal and generating output data based on the first data.

According to one embodiment of the present invention, the semiconductor memory device may be a stacked memory device in which a plurality of chips for transmitting and receiving data and control signals through a through-silicon-via (TSV) are stacked.

The output driver circuit according to another embodiment of the present invention includes a first buffer, a second buffer, a pull-up PMOS transistor, a pull-down NMOS transistor, and a noise remover.

The first buffer buffers the first input signal to generate a first voltage signal and outputs the first voltage signal to the first node. The second buffer buffers the first input signal to generate the first voltage signal and outputs the first voltage signal to the second node. A pull-up PMOS transistor couples the power supply voltage to the output node in response to the first voltage signal of the first node. A pull-down NMOS transistor couples a ground voltage to the output node in response to the first voltage signal of the second node. The PMOS transistor is electrically connected to the first node, the second node, and the output node, and when the pull-down NMOS transistor is in an off state, Thereby reducing the noise of the output signal by forming a current path between the ground voltage.

The output driver circuit according to another embodiment of the present invention includes a first buffer, a second buffer, a pull-up PMOS transistor, a pull-down NMOS transistor, and a noise remover.

The first buffer buffers the first input signal to generate a first voltage signal and outputs the first voltage signal to the first node. The second buffer buffers the first input signal to generate the first voltage signal and outputs the first voltage signal to the second node. A pull-up PMOS transistor couples the power supply voltage to the output node in response to the first voltage signal of the first node. A pull-down NMOS transistor couples a ground voltage to the output node in response to the first voltage signal of the second node. The PMOS transistor is in an on state and the pull-down NMOS transistor is in an off state. The pull-down PMOS transistor is electrically connected to the first node, the second node, the input terminal of the second buffer, , It reduces the noise of the output signal by forming a current path between the output node and the ground voltage.

According to one embodiment of the present invention, the noise eliminator may include a supplementary pull-up PMOS transistor, a supplementary pull-down NMOS transistor, a first drive control section, and a second drive control section.

The auxiliary pull-up PMOS transistor has a source connected to the supply voltage, and a drain connected to the output node. The auxiliary pull-down NMOS transistor has a source connected to a ground voltage, and a drain connected to the output node. A first drive control unit is electrically connected to the input terminal of the first node and the second buffer, and controls the auxiliary pull-up PMOS transistor. A second drive control section is electrically connected to the first node and the second node, and controls the auxiliary pull-down NMOS transistor.

According to an embodiment of the present invention, the first drive control unit may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor.

The first PMOS transistor has a source connected to the input terminal of the second buffer, a gate connected to the first node, and a drain connected to the gate of the auxiliary pull-up PMOS transistor. The first NMOS transistor has a gate and a source commonly connected to the first node, and a drain coupled to a gate of the auxiliary pull-up PMOS transistor. The second PMOS transistor has a source coupled to the first node, a gate coupled to an input terminal of the second buffer, and a drain coupled to a gate of the auxiliary pull-up PMOS transistor. The second NMOS transistor has a gate and a drain commonly connected to the input terminal of the second buffer, and a source connected to the gate of the auxiliary pull-up PMOS transistor.

According to an embodiment of the present invention, the second drive control unit may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor.

The first PMOS transistor has a source coupled to the first node, a gate coupled to the second node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The first NMOS transistor has a gate and a drain commonly connected to the second node, and a source coupled to the gate of the auxiliary pull-down NMOS transistor. The second PMOS transistor has a source coupled to the second node, a gate coupled to the first node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor. The second NMOS transistor has a drain and a gate connected in common to the first node, and a source coupled to a gate of the auxiliary pull-down NMOS transistor.

The output driver circuit according to another embodiment of the present invention includes a first buffer, a second buffer, a pull-up NMOS transistor, and a pull-down NMOS transistor.

The first buffer buffers the first input signal to generate a first voltage signal and outputs the first voltage signal to the first node. The second buffer buffers a second input signal having a phase opposite to the first input signal to generate a second voltage signal and outputs the second voltage signal to a second node. The pull-up NMOS transistor has a low threshold voltage and couples the power supply voltage to the output node in response to the first voltage signal. A pull-down NMOS transistor couples a ground voltage to the output node in response to the second voltage signal.

The output driver circuit according to embodiments of the present invention reduces the power noise by forming a current path between the output node and the ground voltage when the pull-up transistor is on and the pull-down transistor is off, It is possible to improve the degree of fidelity. Therefore, the semiconductor memory device including the output driver circuit is insensitive to noise and has little data transmission error.

1 is a circuit diagram showing an output driving circuit capable of reducing noise according to an embodiment of the present invention.
2 is a circuit diagram showing an example of a noise eliminator included in the output drive circuit of FIG.
3 is a circuit diagram showing another example of the noise eliminator included in the output drive circuit of Fig.
Figs. 4 and 5 are simulation diagrams showing waveforms of main signals of the output driver circuit of Fig. 1. Fig.
6 is a circuit diagram showing an output driving circuit capable of reducing noise according to another embodiment of the present invention.
7 is a circuit diagram showing one example of a noise eliminator included in the output drive circuit of Fig.
8 is a circuit diagram showing another example of the noise eliminator included in the output drive circuit of Fig.
FIG. 9 is a circuit diagram showing an output driving circuit capable of reducing noise according to another embodiment of the present invention.
10 is a circuit diagram showing an output driving circuit capable of reducing noise according to another embodiment of the present invention.
11 to 14 are simulation diagrams for comparing the performance of the output driver circuit according to the prior art and the embodiment of the present invention.
15 is a block diagram showing an example of a semiconductor memory device including an output driver circuit according to embodiments of the present invention.
16 is a circuit diagram showing one example of an output circuit included in the semiconductor memory device of Fig.
17 is a diagram showing an example of a memory system including a semiconductor memory device according to an embodiment of the present invention.
18 is a simplified perspective view showing one of the laminated semiconductor devices including the semiconductor memory device according to the embodiment of the present invention.
19 is a block diagram showing another example of a memory system including a semiconductor memory device according to an embodiment of the present invention.
20 is a block diagram showing an example of an electronic system including a semiconductor memory device according to an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprising ", or" having ", and the like, are intended to specify the presence of stated features, integers, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram showing an output driving circuit 100 capable of reducing noise according to an embodiment of the present invention.

1, the output driving circuit 100 includes a first buffer 110, a second buffer 120, a pull-up NMOS transistor MN1, a pull-down NMOS transistor MN2, and a noise remover 130, .

The first buffer 110 receives the first input signal INN through the input line 101 and buffers the first input signal INN to generate the first voltage signal INNB and the first voltage signal INNB, INNB to the first node N1. The second buffer 120 receives a second input signal INP having an opposite phase to the first input signal INN through the input line 102 and buffers the second input signal INP to generate a second Generates the voltage signal INPB and outputs the second voltage signal INPB to the second node N2. In the example of FIG. 1, the first buffer 110 includes an inverter, and may generate a first voltage signal INNB by inverting the phase of the first input signal INN. The second buffer 120 includes an inverter and can generate a second voltage signal INPB by inverting the phase of the second input signal INP.

The pull-up NMOS transistor MN1 connects the power supply voltage VDDQ to the output node N3 in response to the first voltage signal INNB. The pull-down NMOS transistor MN2 connects the ground voltage VSSQ to the output node N3 in response to the second voltage signal INPB. The noise eliminator 130 is electrically connected to the first node N1, the second node N2 and the output node N3 so that the pull-up NMOS transistor MN1 is on and the pull- MN2 is in the OFF state, it reduces the noise of the output signal DQ by forming a current path between the output node N3 and the ground voltage VSSQ. The output signal DQ may be output to the outside through the output line 103. [

According to one embodiment of the present invention, the pull-up NMOS transistor MN1 may have a low threshold voltage.

According to one embodiment of the present invention, the magnitude of the current flowing through the current path when the pull-up NMOS transistor MN1 is in the ON state is the magnitude of the current flowing through the pull-down NMOS transistor MN2 when the pull- May be smaller than the current flowing through the transistor MN2.

According to one embodiment of the present invention, when the pull-down NMOS transistor MN2 is on, the current flowing through the pull-down NMOS transistor MN2 and the current flowing through the pull- The ratio of the magnitude of the current flowing through the current path may be 97: 3.

2 is a circuit diagram showing one example of the noise eliminator 130 included in the output drive circuit 100 of FIG.

Referring to FIG. 2, the noise remover 130a may include an auxiliary pull-up NMOS transistor MN3, an auxiliary pull-down NMOS transistor MN4, and a drive control circuit 131. The driving control circuit 131 may include a first driving control unit 132 and a second driving control unit 133. [

The auxiliary pull-up NMOS transistor MN3 has a drain connected to the power supply voltage VDDQ and a source connected to the output node N3. The auxiliary pull-down NMOS transistor MN4 has a source connected to the ground voltage VSSQ and a drain connected to the output node N3. The first driving control unit 132 is electrically connected to the first node N1 and the second node N2 and controls the auxiliary pull-up NMOS transistor MN3. The second drive control section 133 is electrically connected to the first node N1 and the second node N2 and controls the auxiliary pull-down NMOS transistor MN4.

According to one embodiment of the present invention, the auxiliary pull-up NMOS transistor MN3 may have a low threshold voltage.

According to one embodiment of the present invention, the magnitude of the current flowing through the auxiliary pull-down NMOS transistor MN4 when the pull-up NMOS transistor MN1 is in the on state is the same as the magnitude of the current flowing through the pull- The magnitude of the current flowing through the pull-down NMOS transistor MN2 may be smaller than the magnitude of the current flowing through the pull-down NMOS transistor MN2.

According to one embodiment of the present invention, the current flowing through the pull-down NMOS transistor MN2 when the pull-down NMOS transistor MN2 is on and the current flowing through the pull-down NMOS transistor MN2 when the pull- The ratio of the magnitude of the current flowing through the pull-down NMOS transistor MN4 may be 97: 3.

According to one embodiment of the present invention, in the semiconductor integrated circuit, the size of the auxiliary pull-down NMOS transistor MN4 may be smaller than the size of the pull-down NMOS transistor MN2.

The first drive control unit 132 may include a first PMOS transistor MP1, a first NMOS transistor MN6, a second PMOS transistor MP2, and a second NMOS transistor MN5.

The first PMOS transistor MP1 has a source and a gate connected in common to the first node N1 and a drain connected to the gate of the auxiliary pull-up NMOS transistor MN3. The first NMOS transistor MN6 has a gate connected to the first node N1, a drain connected to the second node N2, and a source connected to the gate of the auxiliary pull-up NMOS transistor MN3. The second PMOS transistor MP2 has a source and a gate connected in common to the second node N2, and a drain connected to the gate of the auxiliary pull-up NMOS transistor MN3. The second NMOS transistor MN5 has a drain connected to the first node N1, a gate connected to the second node N2, and a source connected to the gate of the auxiliary pull-up NMOS transistor MN3. The first PMOS transistor MP1, the first NMOS transistor MN6, the second PMOS transistor MP2, the second NMOS transistor MN5 and the auxiliary pull-up NMOS transistor MN3 are connected to the fourth node N4 do.

The second drive control unit 133 may include a third PMOS transistor MP3, a third NMOS transistor MN8, a fourth PMOS transistor MP4, and a fourth NMOS transistor MN7.

The third PMOS transistor MP3 has a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN4. The third NMOS transistor MN8 has a gate and a drain connected in common to the second node N2, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN4. The fourth PMOS transistor MP4 has a source connected to the second node N2, a gate connected to the first node N1, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN4. The fourth NMOS transistor MN7 has a drain and a gate connected in common to the first node N1 and a source connected to the gate of the auxiliary pull-down NMOS transistor MN4. The third PMOS transistor MP3, the third NMOS transistor MN8, the fourth PMOS transistor MP4, the fourth NMOS transistor MN7 and the auxiliary pull-down NMOS transistor MN4 are connected to the fifth node N5 do.

3 is a circuit diagram showing another example of the noise eliminator 130 included in the output drive circuit 100 of FIG.

Referring to FIG. 3, the noise remover 130b may include an auxiliary pull-down NMOS transistor MN4, and a drive controller 131a.

The auxiliary pull-down NMOS transistor MN4 has a source connected to the ground voltage VSSQ and a drain connected to the output node N3. The driving control section 131a is electrically connected to the first node N1 and the second node N2 and controls the auxiliary pull-down NMOS transistor MN4.

The driving control unit 131a may include a third PMOS transistor MP3, a third NMOS transistor MN8, a fourth PMOS transistor MP4, and a fourth NMOS transistor MN7.

The third PMOS transistor MP3 has a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN4. The third NMOS transistor MN8 has a gate and a drain connected in common to the second node N2, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN4. The fourth PMOS transistor MP4 has a source connected to the second node N2, a gate connected to the first node N1, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN4. The fourth NMOS transistor MN7 has a drain and a gate connected in common to the first node N1 and a source connected to the gate of the auxiliary pull-down NMOS transistor MN4.

Hereinafter, the operation of the output drive circuit 100 will be described with reference to Figs.

When the first input signal INN is in a logic low state and the second input signal INP is in a logic high state, the voltage of the first node N1, that is, the first voltage signal INNB, becomes a logic high state , The voltage of the second node N2, that is, the second voltage signal INPB becomes a logic low state. Thus, the pull-up NMOS transistor MN1 is turned on, the pull-down NMOS transistor MN2 is turned off, and the power supply voltage VDDQ is connected to the output node N3. At this time, the output signal DQ becomes a logic high state.

2, when the voltage of the first node N1 becomes a logic high state and the voltage of the second node N2 is a logic low state, the first PMOS transistor MP1 of the first drive control section 132 And the second NMOS transistor MN5 are in the off state and the second and fourth PMOS transistors MP2 and MN6 are in the on state. At this time, the auxiliary pull-up NMOS transistor MN3 is turned off DC in response to the voltage signal of the second node N2 which is in a logic low state. When the voltage of the first node N1 becomes a logic high state and the voltage of the second node N2 is a logic low state, the fourth PMOS transistor MP4 and the third PMOS transistor MP4 of the second drive control section 133, The NMOS transistor MN8 is in the OFF state, and the third PMOS transistor MP3 and the fourth NMOS transistor MN7 are in the ON state. At this time, the first node N1 in the logic high state is transferred to the fifth node N5, and the auxiliary pull-down NMOS transistor MN4 is turned on in response to the voltage signal of the fifth node N5 .

When the first input signal INN is in a logic high state and the second input signal INP is in a logic low state, the voltage of the first node N1, i.e., the first voltage signal INNB, becomes a logic low state , The voltage of the second node N2, that is, the second voltage signal INPB becomes a logic high state. Thus, the pull-up NMOS transistor MN1 is turned off, the pull-down NMOS transistor MN2 is turned on, and the ground voltage VSSQ is connected to the output node N3. At this time, the output signal DQ becomes a logic low state.

When the voltage of the first node N1 becomes a logic low state and the voltage of the second node N2 is in a logic high state, the first PMOS transistor MP1 and the second NMOS transistor N2 of the first drive control section 132 are turned on, The transistor MN5 is turned on and the second PMOS transistor MP2 and the first NMOS transistor MN6 are turned off. At this time, the auxiliary pull-up NMOS transistor MN3 is turned off DC in response to the voltage signal of the first node N1 in the logic low state. Also, when the voltage of the first node N1 becomes a logic low state and the voltage of the second node N2 is in a logic high state, the fourth PMOS transistor MP4 and the third PMOS transistor MP4 of the second drive control section 133, The NMOS transistor MN8 is turned on and the third PMOS transistor MP3 and the fourth NMOS transistor MN7 are turned off. At this time, the second node N2 in the logic high state is transferred to the fifth node N5, and the auxiliary pull-down NMOS transistor MN4 is turned on in response to the voltage signal of the fifth node N5 .

As described above, when the pull-up NMOS transistor MN1 is in the ON state and the pull-down NMOS transistor MN2 is in the OFF state, the auxiliary pull-up NMOS transistor MN3 is in the DC OFF state and the auxiliary pull- The NMOS transistor MN4 is turned on. Therefore, when the pull-up NMOS transistor MN1 is turned on and the power supply voltage VDDQ is connected to the output node N3, the auxiliary pull-down NMOS transistor MN1 connected between the output node N3 and the ground voltage VSSQ The transistor MN4 is turned on and a current path can be formed between the output node N3 and the ground voltage VSSQ. Therefore, the noise of the output signal DQ is reduced and the signal fidelity is increased.

The auxiliary pull-up NMOS transistor MN3 is in the DC off state and the auxiliary pull-down NMOS transistor MN4 is in the off state even when the pull-up NMOS transistor MN1 is off and the pull-down NMOS transistor MN2 is on. Is turned on.

As described below, since the size of the auxiliary pull-down NMOS transistor MN4 is much smaller than the size of the pull-down NMOS transistor MN2, the output signal DQ is generated by the state of the auxiliary pull- Is not changed.

4 and 5 are simulation diagrams showing waveforms of main signals of the output driver circuit 100 of FIG.

4, the first voltage signal INNB, which is an output signal of the first buffer 110, has a phase opposite to the first input signal INN, and the output signal DQ has a phase opposite to that of the first voltage signal INNB ). The fourth node N4 to which the first PMOS transistor MP1, the first NMOS transistor MN6, the second PMOS transistor MP2, the second NMOS transistor MN5, and the auxiliary pull-up NMOS transistor MN3 are connected, (V (N4)) has a small value close to 0 V DC, but contains noise-like ripples. As described above, the size of the auxiliary pull-up NMOS transistor MN3 can be designed much smaller than the size of the pull-up NMOS transistor MN1. For example, the ratio of the size of the pull-up NMOS transistor MN1 to the size of the auxiliary pull-up NMOS transistor MN3 may be 97: 3. Therefore, a minute current can flow through the auxiliary pull-up NMOS transistor MN3 having a small size by the ripple included in the voltage signal V (N4) of the fourth node N4. Therefore, the noise of the output signal DQ can be reduced by the noise eliminator 130 shown in FIG.

5, the second voltage signal INPB, which is the output signal of the second buffer 120, has a phase opposite to the second input signal INP, and the output signal DQ has a phase opposite to that of the second voltage signal INNB ). The fifth node N5 to which the third PMOS transistor MP3, the third NMOS transistor MN8, the fourth PMOS transistor MP4, the fourth NMOS transistor MN7, and the auxiliary pull-down NMOS transistor MN4 are connected, The voltage signal V (N5) of the DC voltage has a magnitude of DC 1V and includes noise-like ripples. As described above, the size of the auxiliary pull-down NMOS transistor MN4 can be designed much smaller than the size of the pull-down NMOS transistor MN2. For example, the ratio of the size of the pull-down NMOS transistor MN2 to the size of the auxiliary pull-down NMOS transistor MN4 may be 97: 3.

When the pull-down NMOS transistor MN1 is in the ON state and the pull-down NMOS transistor MN2 is in the OFF state, the potential difference between the output node N3 and the ground voltage VSSQ A current path can be formed. The auxiliary pull-down NMOS transistor MN4 can also operate when the pull-down NMOS transistor MN2 is on to form a current path. Therefore, the noise of the output signal DQ can be reduced by the noise eliminator 130 shown in FIG.

6 is a circuit diagram showing an output driver circuit 200 capable of reducing noise according to another embodiment of the present invention.

6, the output driving circuit 200 includes a first buffer 210, a second buffer 220, a pull-up PMOS transistor MP5, a pull-down NMOS transistor MN8, and a noise remover 230, .

The first buffer 210 receives the input signal IN through the input line 201 and generates the first voltage signal INB by buffering the input signal IN and outputs the first voltage signal INB 1 node N6. The second buffer 220 receives the input signal IN through the input line 201 and generates the first voltage signal INB by buffering the input signal IN and outputs the first voltage signal INB 2 node N7. In the example of FIG. 6, the first buffer 210 includes an inverter, and may generate the first voltage signal INB by inverting the phase of the input signal IN. The second buffer 220 includes an inverter and can generate the first voltage signal INB by inverting the phase of the input signal IN.

The pull-up PMOS transistor MP5 couples the power supply voltage VDDQ to the output node N8 in response to the first voltage signal INB. The pull-down NMOS transistor MN8 connects the ground voltage VSSQ to the output node N8 in response to the first voltage signal INB. The noise eliminator 230 is electrically connected to the first node N6, the second node N7 and the output node N8, and the pull-up PMOS transistor MP5 is on and the pull-down NMOS transistor MN8 is in the OFF state, the current path is formed between the output node N8 and the ground voltage VSSQ to reduce the noise of the output signal DQ. The output signal DQ may be output to the outside through the output line 203.

7 is a circuit diagram showing an example of the noise eliminator 230 included in the output driver circuit 200 of FIG.

Referring to FIG. 7, the noise remover 230a may include an auxiliary pull-up NMOS transistor MN9, an auxiliary pull-down NMOS transistor MN10, and a drive control circuit 231. The drive control circuit 231 may include a first drive control unit 232 and a second drive control unit 233. [

The auxiliary pull-up NMOS transistor MN9 has a drain connected to the power supply voltage VDDQ and a source connected to the output node N8. The auxiliary pull-down NMOS transistor MN10 has a source connected to the ground voltage VSSQ and a drain connected to the output node N8. The first drive control section 232 is electrically connected to the first node N6 and the second node N7 and controls the auxiliary pull-up NMOS transistor MN9. The second drive control section 233 is electrically connected to the first node N6 and the second node N7 and controls the auxiliary pull-down NMOS transistor MNlO.

According to one embodiment of the present invention, the auxiliary pull-up NMOS transistor MN9 may have a low threshold voltage.

According to one embodiment of the present invention, the magnitude of the current flowing through the auxiliary pull-down NMOS transistor MNlO when the pull-up PMOS transistor MP5 is in the on state is such that the pull- The magnitude of the current flowing through the pull-down NMOS transistor MN8 may be smaller than the magnitude of the current flowing through the pull-down NMOS transistor MN8.

According to one embodiment of the present invention, the current flowing through the pull-down NMOS transistor MN8 when the pull-down NMOS transistor MN8 is on and the current flowing through the pull-down PMOS transistor MP5 when the pull- The ratio of the magnitude of the current flowing through the pull-down NMOS transistor MN10 may be 97: 3.

According to one embodiment of the present invention, in the semiconductor integrated circuit, the size of the auxiliary pull-down NMOS transistor MN10 may be smaller than the size of the pull-down NMOS transistor MN8.

The first drive control unit 232 may include a first PMOS transistor MP6, a first NMOS transistor MN12, a second PMOS transistor MP7, and a second NMOS transistor MN11.

The first PMOS transistor MP6 has a source and a gate connected in common to the first node N6, and a drain connected to the gate of the auxiliary pull-up NMOS transistor MN9. The first NMOS transistor MN12 has a gate connected to the first node N6, a drain connected to the second node N7, and a source connected to the gate of the auxiliary pull-up NMOS transistor MN9. The second PMOS transistor MP7 has a source and a gate connected in common to the second node N7, and a drain connected to the gate of the auxiliary pull-up NMOS transistor MN9. The second NMOS transistor MN11 has a drain connected to the first node N6, a gate connected to the second node N7, and a source connected to the gate of the auxiliary pull-up NMOS transistor MN9. The first PMOS transistor MP6, the first NMOS transistor MN12, the second PMOS transistor MP7, the second NMOS transistor MN11 and the auxiliary pull-up NMOS transistor MN9 are connected to the fourth node N9 do.

The second drive control unit 233 may include a third PMOS transistor MP8, a third NMOS transistor MN14, a fourth PMOS transistor MP9, and a fourth NMOS transistor MN13.

The third PMOS transistor MP8 has a source connected to the first node N6, a gate connected to the second node N7, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN10. The third NMOS transistor MN14 has a gate and a drain commonly connected to the second node N7, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN10. The fourth PMOS transistor MP9 has a source connected to the second node N7, a gate connected to the first node N6, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN10. The fourth NMOS transistor MN13 has a drain and a gate connected in common to the first node N6, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN10. The third PMOS transistor MP8, the third NMOS transistor MN14, the fourth PMOS transistor MP9, the fourth NMOS transistor MN13 and the auxiliary pull-down NMOS transistor MN10 are connected to the fifth node N10 do.

8 is a circuit diagram showing another example of the noise eliminator 230 included in the output drive circuit 200 of FIG.

Referring to FIG. 8, the noise remover 230b may include an auxiliary pull-down NMOS transistor MN10 and a drive control unit 231a.

The auxiliary pull-down NMOS transistor MN10 has a source connected to the ground voltage VSSQ and a drain connected to the output node N8. The driving control section 231a is electrically connected to the first node N6 and the second node N7 and controls the auxiliary pull-down NMOS transistor MNlO.

The driving control unit 231a may include a third PMOS transistor MP8, a third NMOS transistor MN14, a fourth PMOS transistor MP9, and a fourth NMOS transistor MN13.

The third PMOS transistor MP8 has a source connected to the first node N6, a gate connected to the second node N7, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN10. The third NMOS transistor MN14 has a gate and a drain commonly connected to the second node N7, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN10. The fourth PMOS transistor MP9 has a source connected to the second node N7, a gate connected to the first node N6, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN10. The fourth NMOS transistor MN13 has a drain and a gate connected in common to the first node N6, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN10. The third PMOS transistor MP8, the third NMOS transistor MN14, the fourth PMOS transistor MP9, the fourth NMOS transistor MN13 and the auxiliary pull-down NMOS transistor MN10 are connected to the fifth node N10 do.

9 is a circuit diagram showing an output driver circuit 300 capable of reducing noise according to another embodiment of the present invention.

9, the output driving circuit 100 includes a first buffer 310, a second buffer 320, a pull-up PMOS transistor MP16, a pull-down NMOS transistor MN16, and a noise remover . The noise eliminator may include a secondary pull-up PMOS transistor MP17, a secondary pull-down NMOS transistor MN17, a first driving control unit 340, and a second driving control unit 350. [

The first buffer 310 receives the input signal IN through the input line 301 and buffers the input signal IN to generate the first voltage signal INB and outputs the first voltage signal INB. 1 node N11. The second buffer 320 receives the input signal IN through the input line 301 and generates the first voltage signal INB by buffering the input signal IN and outputs the first voltage signal INB 2 node N12. In the example of FIG. 9, the first buffer 310 includes an inverter, and can generate the first voltage signal INB by inverting the phase of the input signal IN. The second buffer 320 includes an inverter and can generate the first voltage signal INB by inverting the phase of the input signal IN.

The pull-up PMOS transistor MP16 couples the power supply voltage VDDQ to the output node N14 in response to the first voltage signal INB. The pull-down NMOS transistor MN16 connects the ground voltage VSSQ to the output node N14 in response to the first voltage signal INB. The noise eliminator is electrically connected to the first node N11, the second node N12, the input terminal of the second buffer 320 and the output node N14, and the pull-up PMOS transistor MP16 is on And reduces the noise of the output signal DQ by forming a current path between the output node N14 and the ground voltage VSSQ when the pull-down NMOS transistor MN16 is in the OFF state. The output signal DQ may be output to the outside through the output line 303. [

The auxiliary pull-up PMOS transistor MP17 has a source connected to the power supply voltage VDDQ and a drain connected to the output node N14. The auxiliary pull-down NMOS transistor MN17 has a source connected to the ground voltage VSSQ and a drain connected to the output node N14. The first drive control unit 340 is electrically connected to the input terminals of the first node N11 and the second buffer 320 and controls the auxiliary pull-up PMOS transistor MP17. The second drive control unit 350 is electrically connected to the first node N11 and the second node N12 and controls the auxiliary pull-down NMOS transistor MN17.

The first drive control unit 340 may include a first PMOS transistor MP18, a first NMOS transistor MN18, a second PMOS transistor MP19, and a second NMOS transistor MN19.

The first PMOS transistor MP18 has a source connected to the input terminal of the second buffer 320, a gate connected to the first node N11, and a drain connected to the gate of the auxiliary pull-up PMOS transistor MP17. The first NMOS transistor MN18 has a gate and a source connected in common to the first node MN11 and a drain connected to the gate of the auxiliary pull-up PMOS transistor MP17. The second PMOS transistor MP19 has a source connected to the first node N11, a gate connected to the input terminal of the second buffer 320, and a drain connected to the gate of the auxiliary pull-up PMOS transistor MP17. The second NMOS transistor MN19 has a gate and a drain connected in common to the input terminal of the second buffer 320 and a source connected to the gate of the auxiliary pull-up PMOS transistor MP17.

The second driving control unit 350 may include a third PMOS transistor MP20, a third NMOS transistor MN20, a fourth PMOS transistor MP21, and a fourth NMOS transistor MN21.

The third PMOS transistor MP20 has a source connected to the first node N11, a gate connected to the second node N12, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN17. The third NMOS transistor MN20 has a gate and a drain commonly connected to the second node N12, and a source connected to the gate of the auxiliary pull-down NMOS transistor MN17. The fourth PMOS transistor MP21 has a source connected to the second node N12, a gate connected to the first node N11, and a drain connected to the gate of the auxiliary pull-down NMOS transistor MN17. The fourth NMOS transistor MN21 has a drain and a gate connected in common to the first node N11 and a source connected to the gate of the auxiliary pull-down NMOS transistor MN17.

According to one embodiment of the present invention, the magnitude of the current flowing through the auxiliary pull-down NMOS transistor MN17 when the pull-up PMOS transistor MP16 is in the ON state is the magnitude of the current flowing through the pull- May be smaller than the magnitude of the current flowing through the pull-down NMOS transistor MN16.

According to one embodiment of the present invention, the current flowing through the pull-down NMOS transistor MN16 when the pull-down NMOS transistor MN16 is on and the current flowing through the pull-down PMOS transistor MP16 when the pull- The ratio of the magnitude of the current flowing through the pull-down NMOS transistor MN17 may be 97: 3.

According to one embodiment of the present invention, in the semiconductor integrated circuit, the size of the auxiliary pull-down NMOS transistor MN17 may be smaller than the size of the pull-down NMOS transistor MN16.

10 is a circuit diagram showing an output driver circuit 400 capable of reducing noise according to another embodiment of the present invention.

10, the output driving circuit 400 includes a first buffer 410, a second buffer 420, a pull-up NMOS transistor 430, and a pull-down NMOS transistor 440.

The first buffer 410 receives the first input signal INN through the input line 401 and buffers the first input signal INN. The second buffer 120 receives a second input signal INP having an opposite phase to the first input signal INN through the input line 402 and buffers the second input signal INP. In the example of FIG. 10, the first buffer 410 may include an inverter and inverts the phase of the first input signal INN. The second buffer 420 may include an inverter to invert the phase of the second input signal INP.

The pull-up NMOS transistor 430 has a low threshold voltage (LVTN) and connects the power supply voltage VDDQ to the output line 403 in response to the output signal of the first buffer 410. [ The pull-down NMOS transistor 440 couples the ground voltage VSSQ to the output line 403 in response to the output signal of the second buffer 420. The output signal DQ may be output to the outside via the output line 403. [

11 to 14 are simulation diagrams for comparing the performance of the output driver circuit according to the prior art and the embodiment of the present invention. 11 shows waveforms of output voltages of a conventional output driver circuit composed of a pull-up PMOS transistor and a pull-down NMOS transistor, and Fig. 12 shows a waveform of a conventional output driver circuit composed of a pull- The waveform of the output voltage of FIG. 13 shows a waveform of the output voltage of the output driver circuit according to the embodiment of the present invention composed of a pull-up NMOS transistor and a pull-down NMOS transistor having a low threshold voltage, and Fig. 14 shows waveforms of pull- A waveform of an output voltage of an output driver circuit according to an embodiment of the present invention composed of an NMOS transistor, a pull-down NMOS transistor, and a noise remover.

Referring to FIGS. 11 to 14, it can be seen that eye sizes indicating signal integrity have values of 53 ps, 58 ps, 94 ps, and 102 ps, respectively. It can also be seen that the jitter has values of 34 ps, 38.1 ps, 28 ps, and 6.48 ps. Therefore, the semiconductor memory device having the output driver circuit having the characteristics of FIGS. 13 and 14 according to the embodiment of the present invention has high signal fidelity and little jitter. Further, the semiconductor memory device having the output driver circuit having the characteristics of Figs. 13 and 14 according to the embodiment of the present invention also has low current noise.

15 is a block diagram showing an example of a semiconductor memory device 1000 including an output driver circuit according to embodiments of the present invention.

15, a semiconductor memory device 1000 includes a memory cell array 1500 that operates in response to a word line enable signal WL and a column select signal CSL, an address input buffer 1100, a row decoder 1200, a column decoder 1300, an input / output sense amplifier 1600, and an output circuit 1700.

The address input buffer 1100 generates the row address signal ADDR_X and the column address signal ADDR_Y based on the external address ADDR. The row decoder 1200 decodes the row address signal ADDR_X to generate a word line enable signal WL. The column decoder 1300 decodes the column address signal ADDR_Y to generate a column selection signal CSL. The input / output sense amplifier 1600 amplifies the data output from the memory cell array 1500 to generate the first data SAO and transfers the data input from the outside to the memory cell array 1500.

The output circuit 1700 may include an output driving circuit according to the embodiments of the present invention. The output circuit 1700 can reduce the noise of the output signal and generate output data by forming a current path between the output node and the ground voltage when the pull-up transistor is on and the pull-down transistor is off.

16 is a block diagram showing one example of the output circuit 1700 included in the semiconductor memory device 1000 of Fig.

16, the output circuit 1700 may include an ordering circuit 1710, a first multiplexer 1720, a second multiplexer 1730, and an output drive circuit 1740.

The ordering circuit 1710 determines the output order for the first data SAO. The first multiplexer 1720 selects the output bit structure and outputs the second data in response to the output signal of the ordering circuit 1710. The second multiplexer 1730 performs the parallel-to-serial conversion on the second data in response to the output clock signal CLKDQ to generate the third data. The output drive circuit 1740 forms a current path between the output node and the ground voltage when the pull-up transistor is in an ON state and the pull-down transistor is in an OFF state, and generates output data based on the third data do.

The semiconductor memory device 1000 shown in FIG. 15 may include a dynamic random access memory (DRAM), a volatile memory chip such as a static random access memory (SRAM), a flash memory, a phase change memory a non-volatile memory chip such as a phase change memory, a magnetic random access memory (MRAM), or a resistive random access memory (RRAM), or a combination thereof.

17 is a diagram showing an example of a memory system including a semiconductor memory device according to an embodiment of the present invention.

17, the memory system 30 includes a motherboard 31, a chipset (or controller) 40, slots 35_1 and 35_2, memory modules 50 and 60, transmission lines 33 and 34 ). Busses 37 and 39 connect the chipset 40 to the slots 35_1 and 35_2. The terminal resistor Rtm may terminate each of the busses 37 and 39 on the PCB of the motherboard 31.

Although FIG. 17 illustrates two slots 35_1 and 35_2 and two memory modules 50 and 60 for convenience, the memory system 30 may include any number of slots and memory modules.

The chipset 40 may be mounted on the PCB of the motherboard 31 and may control the operation of the memory system 30. [ The chipset 40 may include connectors 41_1 and 41_2 and converters 43_1 and 43_2.

The converter 43_1 receives the parallel data generated in the chipset 40, converts the parallel data into serial data, and outputs the serial data to the transmission line 33 through the connector 41-1. The converter 43_1 receives the serial data through the transmission line 33, converts the serial data into parallel data, and outputs the parallel data to the chipset 40. [

The converter 43_2 receives the parallel data generated in the chipset 40, converts the parallel data into serial data, and outputs the serial data to the transmission line 34 through the connector 41-2. The converter 43_2 receives the serial data through the transmission line 34, converts the serial data into parallel data, and outputs the parallel data to the chipset 40. [ The transmission lines 33 and 34 included in the memory system 30 may be a plurality of optical fibers.

The memory module 50 may include a plurality of memory devices 55_1 to 55_n, a first connector 57, a second connector 51 and converters 53. [ The memory module 60 may include a plurality of memory devices 65_1 through 65_n, a first connector 57 ', a second connector 51', and converters 53 '.

The first connector 57 transmits the low-speed signal received from the chip set to the memory devices, and the second connector 51 can be connected to the transmission line 33 for transmitting the high-speed signal.

The converter 53 receives the serial data through the second connector 51, converts the serial data into parallel data, and outputs the parallel data to the plurality of memory devices 55_1 to 55_n. The converter 53 also receives serial data from the plurality of memory devices 55_1 to 55_n, converts the serial data into parallel data, and outputs the parallel data to the second connector 51. [

The plurality of memory devices 55_1 to 55_n and 65_1 to 65_n included in FIG. 17 may include semiconductor memory devices according to the embodiments of the present invention. Accordingly, the plurality of memory devices 55_1 to 55_9 may include an output circuit according to embodiments of the present invention. The output circuit included in the plurality of memory devices 55_1 to 55_9 is configured to form a current path between the output node and the ground voltage when the pull-up transistor is on and the pull-down transistor is off, Lt; / RTI >

  The plurality of memory devices 55_1 to 55_n and 65_1 to 65_n may be a volatile memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, Non-volatile memory chips such as phase change memory, magnetic random access memory (MRAM), or resistive random access memory (RRAM), or a combination thereof.

18 is a simplified perspective view showing one of the laminated semiconductor devices 2100 including the semiconductor memory device 1000 according to the embodiment of the present invention.

18, the laminated semiconductor device 2100 includes an interface chip 2110 and memory chips 2120, 2130, 2140, and 2150 electrically connected by a through-silicon vias 2160. Although the penetrating electrode 2160 arranged in two rows is shown in Fig. 18, the laminated semiconductor device 2100 may have any number of penetrating electrodes.

Memory chips 2120, 2130, 2140, 2150 included in the stacked semiconductor device 2100 may include output circuits according to embodiments of the present invention. The output circuit included in the memory chips 2120, 2130, 2140 and 2150 is configured to form a current path between the output node and the ground voltage when the pull-up transistor is on and the pull- Lt; / RTI > The interface chip 2110 interfaces between the memory chips 2120, 2130, 2140 and 2150 and the external device.

19 is a block diagram illustrating another example of a memory system 2200 including a semiconductor memory device according to an embodiment of the present invention.

19, a memory system 2200 includes a memory controller 1210 and a semiconductor memory device 2220.

The memory controller 2210 generates an address signal ADD and a command CMD and provides them to the semiconductor memory device 2220 via buses. The data DQ is transferred from the memory controller 2210 to the semiconductor memory device 2220 via the bus or from the semiconductor memory device 2220 to the memory controller 2210 via the bus.

Semiconductor memory device 2220 may include an output circuit having a noise reduction function according to embodiments of the present invention. The output circuit may form a current path between the output node and the ground voltage and generate output data when the pull-up transistor is in an on state and the pull-down transistor is in an off state.

20 is a block diagram illustrating one example of an electronic system 2300 including a semiconductor memory device according to an embodiment of the present invention.

20, an electronic system 2300 according to an embodiment of the present invention may include a controller 2310, an input / output device 2320, a storage device 2330, an interface 2340, and a bus 2350 have. The storage device 2330 may be a semiconductor memory device including an output circuit having a noise reduction function according to embodiments of the present invention. The output circuit may form a current path between the output node and the ground voltage and generate output data when the pull-up transistor is in an on state and the pull-down transistor is in an off state. The bus 2350 may serve to provide a path through which data is transferred between the controller 2310, the input / output device 2320, the storage device 2330, and the interface 2340.

The controller 2310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The input / output device 2320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 2330 may serve to store data and / or instructions executed by the controller 2310, and the like.

The storage device 2330 may be a volatile memory chip such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), a flash memory, a phase change memory, non-volatile memory chips such as magnetic random access memory (MRAM) or resistive random access memory (RRAM), or a combination thereof. The interface 2340 may serve to transmit data to or receive data from the communication network. The interface 2340 may include an antenna or a wired or wireless transceiver, and may transmit and receive data either wired or wirelessly. In addition, the interface 2340 may include an optical fiber, and may transmit and receive data through the optical fiber. The electronic system 2300 may further include an application chipset, a camera image processor, and an input / output device.

The electronic system 2300 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, A digital music system, and an information transmission / reception system. In the case where the electronic system 2300 is a device capable of performing wireless communication, the electronic system 2300 may be a CDMA (Code Division Multiple Access), a GSM (Global System for Mobile communication), an NADC (North American Digital Cellular) -TDMA (Enhanced-Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000.

The present invention is applicable to a semiconductor device and a memory system including the semiconductor device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100, 200, 300, 400: Power mixing circuit
110, 120: buffer
130, 230: Noise eliminator 1000: Semiconductor memory device
1100: address input buffer 1200:
1300: column decoder 1500: memory cell array
1600: I / O sense amplifier 1700: Output circuit
2100: Laminated semiconductor device 30, 2200: Memory system
2300: Electronic system

Claims (10)

A first buffer for buffering a first input signal to generate a first voltage signal and outputting the first voltage signal to a first node;
A second buffer for buffering a second input signal having a phase opposite to the first input signal to generate a second voltage signal and outputting the second voltage signal to a second node;
A pull-up NMOS transistor coupled to the output node in response to the first voltage signal;
A pull-down NMOS transistor coupled to the output node in response to the second voltage signal; And
The NMOS transistor is electrically connected to the first node, the second node, and the output node, and when the pull-up NMOS transistor is on and the pull-down NMOS transistor is off, And a noise eliminator for reducing the noise of the output signal by forming a current path in the output signal,
The noise eliminator
An auxiliary pull-up NMOS transistor having a drain coupled to the power supply voltage, and a source coupled to the output node;
A complementary pull-down NMOS transistor having a source coupled to the ground voltage and a drain coupled to the output node;
A first drive control unit electrically connected to the first node and the second node and controlling the auxiliary pull-up NMOS transistor; And
And a second drive control unit electrically connected to the first node and the second node and controlling the auxiliary pull-down NMOS transistor,
Wherein the first drive control unit includes:
A first PMOS transistor having a source and a gate commonly connected to the first node, and a drain coupled to a gate of the auxiliary pull-up NMOS transistor;
A first NMOS transistor having a gate coupled to the first node, a drain coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor;
A second PMOS transistor having a source and a gate commonly connected to the second node, and a drain coupled to a gate of the auxiliary pull-up NMOS transistor; And
A second NMOS transistor having a drain coupled to the first node, a gate coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor. delete The method according to claim 1,
And the magnitude of the current flowing through the current path when the pull-up NMOS transistor is on is smaller than the current flowing through the pull-down NMOS transistor when the pull-down NMOS transistor is on. Output drive circuit. delete The method according to claim 1,
The magnitude of the current flowing through the auxiliary pull-down NMOS transistor when the pull-up NMOS transistor is on is less than the magnitude of the current flowing through the pull-down NMOS transistor when the pull- And the output drive circuit. delete 2. The apparatus of claim 1, wherein the second drive control unit
A first PMOS transistor having a source coupled to the first node, a gate coupled to the second node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor;
A first NMOS transistor having a gate and a drain commonly connected to the second node, and a source coupled to a gate of the auxiliary pull-down NMOS transistor;
A second PMOS transistor having a source coupled to the second node, a gate coupled to the first node, and a drain coupled to a gate of the auxiliary pull-down NMOS transistor; And
A second NMOS transistor having a drain and a gate commonly connected to the first node, and a source coupled to a gate of the auxiliary pull-down NMOS transistor. delete delete A memory cell array operative in response to a word line enable signal and a column select signal;
An address input buffer for generating a row address signal and a column address signal based on an external address;
A row decoder for decoding the row address signal to generate a word line enable signal;
A column decoder for decoding the column address signal to generate a column select signal;
An input / output sense amplifier for amplifying data output from the memory cell array to generate first data and transferring externally input data to the memory cell array; And
And an output circuit for generating output data based on the first data,
Wherein the output circuit comprises:
A first buffer for buffering a first input signal applied as the first data to generate a first voltage signal and outputting the first voltage signal to a first node;
A second buffer for buffering a second input signal having a phase opposite to the first input signal to generate a second voltage signal and outputting the second voltage signal to a second node;
A pull-up NMOS transistor coupled to the output node in response to the first voltage signal;
A pull-down NMOS transistor coupled to the output node in response to the second voltage signal; And
The NMOS transistor is electrically connected to the first node, the second node, and the output node, and when the pull-up NMOS transistor is on and the pull-down NMOS transistor is off, And a noise eliminator for reducing the noise of the output signal by forming a current path in the output signal,
The noise eliminator
An auxiliary pull-up NMOS transistor having a drain coupled to the power supply voltage, and a source coupled to the output node;
A complementary pull-down NMOS transistor having a source coupled to the ground voltage and a drain coupled to the output node;
A first drive control unit electrically connected to the first node and the second node and controlling the auxiliary pull-up NMOS transistor; And
And a second drive control unit electrically connected to the first node and the second node and controlling the auxiliary pull-down NMOS transistor,
Wherein the first drive control unit includes:
A first PMOS transistor having a source and a gate commonly connected to the first node, and a drain coupled to a gate of the auxiliary pull-up NMOS transistor;
A first NMOS transistor having a gate coupled to the first node, a drain coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor;
A second PMOS transistor having a source and a gate commonly connected to the second node, and a drain coupled to a gate of the auxiliary pull-up NMOS transistor; And
A second NMOS transistor having a drain coupled to the first node, a gate coupled to the second node, and a source coupled to a gate of the auxiliary pull-up NMOS transistor.

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