KR102593643B1 - Pixel driving circuit and display panel - Google Patents

Abstract

The present application provides a pixel driving circuit (1) and a display panel, where the pixel driving circuit (1) includes a driving module (10), a data writing module (20), a storage module (30), and an interference filtering module (40). Includes, the driving module 10 drives the light emitting element (LED) to emit light, the data writing module 20 is configured to write the data signal to the storage module 30, and the storage module 30 is configured to write the data signal Accordingly, the time at which the first power signal (VDD) and the second power signal (VSS) are written to the control terminal (A1) of the driving module 10 is adjusted, and the potential of the control terminal (A1) of the driving module 10 is adjusted. is configured to maintain, and the interference filtering module 40 is configured to filter the interference signal among the electrical signals transmitted to the control terminal (A1) of the driving module 10.

Description

Pixel driving circuit and display panel

This application relates to the field of display technology, for example, pixel driving circuits and display panels.

This application claims priority of the Chinese patent application with application number 201910816892.5 filed with the Chinese Intellectual Property Office on August 30, 2019, the entire contents of which are incorporated herein by reference.

With the continued development of display technology, the application range of display panels is becoming increasingly broader, and people's demands for display panels are also increasing.

The pixel driving circuit in the display panel plays a very important role in ensuring that the light emitting element stably emits light. However, the performance of the relevant pixel driving circuit is still not ideal, and there is a problem of low stability.

This application provides a pixel driving circuit and a display panel to improve the stability of the pixel driving circuit.

The pixel driving circuit includes a driving module, a data writing module, a storage module, and an interference filtering module,

The driving module drives the light emitting element to emit light,

The data writing module is configured to write a data signal to the storage module, and the storage module adjusts a time for writing the first power signal and the second power signal to the control terminal of the driving module according to the data signal, Configured to maintain the potential of the control stage of the driving module,

The interference filtering module is configured to filter interference signals among the electrical signals transmitted to the control terminal of the driving module.

The present application further provides a display panel, wherein the display panel includes a plurality of pixel driving circuits according to any embodiment of the present application, wherein the display panel further includes a plurality of scan lines and a plurality of data lines, A plurality of pixel driving circuits are installed in a space formed by crossing a plurality of scan lines and the plurality of data lines, a control terminal of the data writing module is electrically connected to the corresponding scan line, and the first The stage is electrically connected to the corresponding data line.

The embodiment of the present application installs an interference filtering module used to filter interference signals among the electrical signals transmitted to the control terminal of the driving module in the pixel driving circuit, thereby improving the transmission quality and stability of the electrical signal transmitted to the control terminal of the driving module. Therefore, the potential of the control stage of the driving module is not easily affected by interference signals, and the stability is relatively good. Due to the interference of the effective data signal, the light emission of the light emitting element is unstable or the light emission is weak. By improving the problem of deterioration, it is advantageous to improve the stability of the pixel driving circuit, ensuring that the light emitting device continuously and stably emits light. In addition, the embodiment of the present application can maintain stable operating performance even if the pixel driving circuit receives a relatively large amount of interference when conducting a shipping test such as a reliability test for a display panel, thereby improving the yield and competitiveness of the display panel. I order it.

1 is a structural schematic diagram of a pixel driving circuit provided in an embodiment of the present application.
Figure 2 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application.
Figure 3 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application.
Figure 4 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application.
Figure 5 is a schematic diagram of a driving sequence of a pixel driving circuit provided in an embodiment of the present application.
Figure 6 is a structural schematic diagram of a display panel provided in an embodiment of the present application.

Hereinafter, the present application will be described in more detail by combining the attached drawings and examples. The reasons why low stability problems exist in pixel driving circuits are as follows. Due to the presence of many parasitic resistances and capacitors in the signal transmission path, the effective data signal is easily interfered with, causing the light emission of the light emitting element to become unstable or weak. Therefore, the pixel driving circuit has low stability. The problem exists.

Embodiments of the present application provide a pixel driving circuit. The pixel driving circuit is used to drive light-emitting devices such as Micro Light Emitting Diode (micro-LED/μLED) or Organic Light-Emitting Diode (OLED). Additionally, the corresponding pixel driving circuit can perform brightness control on the light emitting device by adopting a digital driving method.

1 is a structural schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Referring to FIG. 1, the corresponding pixel driving circuit includes a driving module 10, a data writing module 20, a storage module 30, and an interference filtering module 40. The driving module 10 drives the light emitting device (LED) to emit light. The data writing module 20 is configured to write a data signal (DATA) to the storage module 30. The storage module 30 adjusts the writing time of the first power signal (VDD) and the second power signal (VSS) to the control terminal (A1) of the driving module 10 according to the data signal (DATA), and the driving module 10 It is configured to maintain the potential of the control stage (A1) of (10). The interference filtering module 40 is configured to filter interference signals among the electrical signals transmitted to the control terminal (A1) of the driving module 10.

The driving module 10 is a circuit module that drives the light emitting device (LED) to emit light. For example, the driving module 10 receives control of a signal output by the storage module 30 and operates the light emitting device (LED). A driving signal is transmitted toward, and the corresponding driving signal may be a current driving signal or a voltage driving signal. For example, in a digital driving method, the size of the driving signal is constant and does not change, and the gray scale displayed by the light-emitting device (LED) is determined according to the retention time of the driving signal, and the longer the retention time of the driving signal, the lower the light-emitting device. The gray scale displayed by (LED) is higher. Conversely, the shorter the holding time of the driving signal, the lower the gray scale displayed by the light emitting element (LED), thereby implementing control of different gray scales.

The data writing module 20 is configured to write the data signal DATA to the circuit module provided by the pixel driving circuit. Illustratively, the data writing module 20 is controlled by the scan signal (SCAN) and transmits the data signal (DATA) toward the storage module 30, and the pulse width of the data signal (DATA) is controlled by the storage module ( 30) determines the width of the output signal. That is, the maintenance time of the first power signal (VDD) and the second power signal (VSS) is determined, and further, the maintenance time of the driving signal is determined.

The storage module 30 is configured to maintain the potential of the control terminal A1 of the driving module 10. Here, the storage module 30 can maintain the potential output by the storage module 30, that is, the potential of the first power signal (VDD) and the second power signal (VSS), and further, the data writing module 20 The potential of the control terminal A1 of the driving module 10 is maintained until the potential of the data signal DATA written by changes.

The interference filtering module 40 is a circuit module configured to filter an interference signal among the electrical signals transmitted to the control terminal (A1) of the driving module 10. That is, the interference filtering module is configured to filter the first power signal (VDD) or the second power signal (VDD). Interference signals in the power signal (VSS) can be filtered, and the time at which the first power signal (VDD) and the second power signal (VSS) are written to the control terminal (A1) of the driving module 10 is determined by the data writing module ( Since it is determined by the data signal written by the data writing module 20, the interference filtering module 40 controls the driving module 10 by the storage module 30 when the interference signal among the data signals written by the data writing module 20 is determined. Interference with the first power signal (VDD) or the second power signal (VSS) output to the stage (A1) can also be eliminated, improving the potential stability of the control stage (A1) of the driving module 10, and further Improves the stability of the operation of the pixel driving circuit.

The embodiment of the present application controls the driving module 10 by installing an interference filtering module 40 configured to filter the interference signal among the electrical signals transmitted to the control terminal A1 of the driving module 10 in the pixel driving circuit. By improving the transmission quality and stability of the electrical signal transmitted to the stage (A1), and preventing the potential of the control stage (A1) of the driving module 10 from being easily affected by interference signals, stability is excellent and a valid data signal is achieved. It improves the problem of unstable or weak light emission of the light emitting device (LED) due to interference with (DATA), and is advantageous in improving the stability of the pixel driving circuit, so that the light emitting device (LED) emits continuous and stable light. secure. Meanwhile, in the embodiment of the present application, when conducting a shipment test such as a reliability test for a display panel, stable operating performance can be maintained even if the data signal (DATA) receives a relatively large amount of interference, thereby improving the yield and competitiveness of the display panel. improve

Continuing to refer to FIG. 1, the signal input terminal (D1) of the interference filtering module 40 is electrically connected to the driving signal output terminal (C3) of the storage module 30, and the signal output terminal (D2) of the interference filtering module 40 ) is electrically connected to the control terminal (A1) of the driving module 10, that is, the interference filtering module 40 is connected in series between the storage module 30 and the driving module 10, so that the driving module 10 Before inputting an electrical signal to the control terminal (A1) of the electric signal, interference signals among the electrical signals are filtered to improve the stability of the potential input to the control terminal (A1) of the driving module 10.

Figure 2 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to Figure 2, the interference filtering module 40 may include a first signal path 401 and a second signal path 402, and the input terminal (D1-1) of the first signal path 401 and the second signal path 402. 2 The input terminal (D2-1) of the signal path 402 becomes the signal input terminal (D1) of the interference filtering module 40 after a short circuit, and the output terminal (D1-2) of the first signal path 401 and the second signal path The output terminal (D2-2) of 402 becomes the signal output terminal (D2) of the interference filtering module 40 after a short circuit, and the first signal path 401 and the second signal path 402 are alternately turned on.

In order to keep the light emitting device (LED) emitting light, the effective signal among the electrical signals output by the storage module 30 and transmitted to the control terminal (A1) of the driving module 10 is maintained constant within a specific time. Meanwhile, the frequency of the interference signal among the electrical signals output by the storage module 30 and transmitted to the control terminal A1 of the driving module 10 is higher than the frequency of the effective signal. The first signal path 401 and the second signal path 402 are turned on alternately, that is, the first signal path 401 and the second signal path 402 constitute a chopper circuit. The electrical signal output by the storage module 30 and transmitted to the control terminal (A1) of the driving module 10 passes alternately through the first signal path 401 and the second signal path 402 to the driving module 10. ) is transmitted to the control stage (A1), and the interference signal can be coupled and filtered in the alternating process.

What should be explained here is that there are various installation methods for the first signal path 401 and the second signal path 402, and some of the various installation methods are described below, but the present application is not limited to this.

Continuing to refer to FIG. 2, the first signal path 401 may include a 13th transistor (M13), and the first terminal of the 13th transistor (M13) may be connected to the input terminal (D1) of the first signal path 401. -1), and the second terminal of the thirteenth transistor (M13) is set as the output terminal (D1-2) of the first signal path 401. The second signal path 402 includes a 14th transistor (M14), the first terminal of the 14th transistor (M14) is the input terminal (D2-1) of the second signal path 402, and the 14th transistor ( The second terminal of M14) is set as the output terminal (D2-2) of the second signal path 402.

In the embodiment of the present application, through installing the interference filtering module 40, on the first side, the 13th transistor (M13) and the 14th transistor (M14) each configure a single transmission gate, and the single transmission gate itself Due to the capacitor filtering action, clutter interference in the electrical signal transmitted to the control terminal (A1) of the driving module 10 is filtered out, thereby improving the transmission quality of the electrical signal transmitted to the control terminal (A1) of the driving module 10. improves; As a second aspect, a relatively large number of pixels must be installed in the display area of the display panel, so the space reserved for the pixel driving circuit is limited, but the interference filtering module has a simple structure and is advantageous for improving the aperture ratio of the display panel; As a third aspect, the 13th transistor M13 and the 14th transistor M14 can be manufactured in the same manufacturing process as other transistors in the pixel driving circuit, which is advantageous in reducing manufacturing difficulty and, therefore, the cost of the pixel driving circuit. It is advantageous in reducing; As a fourth aspect, a control method for controlling the 13th transistor M13 and the 14th transistor M14 to be turned on alternately is simple, which is advantageous in reducing control costs.

Optionally, the channel types of the 13th transistor (M13) and the 14th transistor (M14) may be different, and the control terminal of the 13th transistor (M13) and the control terminal of the 14th transistor (M14) may include a first clock signal (CK). ) is connected. The first clock signal CK is a signal whose high and low potentials alternately change, and the 13th transistor M13 and the 14th transistor M14 may be alternately turned on under the control of the first clock signal CK. The 13th transistor (M13) is an N-type transistor, and the 14th transistor (M14) is a P-type transistor; Alternatively, the 13th transistor (M13) is a P-type transistor and the 14th transistor (M14) is an N-type transistor. FIG. 2 exemplarily shows that the 13th transistor (M13) is an N-type transistor and the 14th transistor (M14) is a P-type transistor. Under the alternately changing potential control of the first clock signal CK, the 13th transistor M13 and the 14th transistor M14 are alternately turned on to transmit an electrical signal to the control terminal A1 of the driving module 10. do.

Figure 3 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to FIG. 3, the first signal path 401 may include a first transistor (M1) and a second transistor (M2), and the first terminal of the first transistor (M1) may be connected to the first signal path 401. ) is the input terminal (D1-1), and the second terminal of the first transistor (M1) is electrically connected to the first terminal of the second transistor (M2), and the second terminal of the second transistor (M2) is connected to the first terminal of the first transistor (M1). This is the output terminal (D1-2) of the signal path 401. The second signal path 402 includes a third transistor (M3) and a fourth transistor (M4), and the first terminal of the third transistor (M3) is connected to the input terminal (D2-1) of the second signal path 402. The second terminal of the third transistor M3 is electrically connected to the first terminal of the fourth transistor M4 and the second terminal of the first transistor M1, and the second terminal of the fourth transistor M4 is electrically connected to the second terminal of the fourth transistor M4. is the output terminal (D2-2) of the second signal path 402.

Through this installation, the embodiment of the present application, in the first aspect, due to the capacitor filtering action of the first transistor (M1), the second transistor (M2), the third transistor (M3), and the fourth transistor (M4) themselves, filtering out clutter interference in the electrical signal transmitted to the control terminal (A1) of the driving module 10, thereby improving the transmission quality of the electrical signal transmitted to the control terminal (A1) of the driving module 10; As a second aspect, a relatively large number of pixels must be installed in the display area of the display panel, so the space reserved for the pixel driving circuit is limited, but the interference filtering module has a simple structure and is advantageous for improving the aperture ratio of the display panel; As a third aspect, each transistor can be manufactured in the same manufacturing process as other transistors in the pixel driving circuit, which is advantageous in reducing manufacturing difficulty and thus in reducing the cost of the pixel driving circuit; As a fourth aspect, the control method for controlling each transistor to turn on alternately is simple, which is advantageous in reducing control costs.

In the above embodiment, there are several control methods for the first transistor (M1), the second transistor (M2), the third transistor (M3), and the fourth transistor (M4), and some of them are described below. , this application is not limited thereto.

Continuing to refer to FIG. 3, the control terminal of the first transistor (M1), the control terminal of the second transistor (M2), the control terminal of the third transistor (M3), and the control terminal of the fourth transistor (M4) are short-circuited. , the first clock signal (CK) is connected. The first clock signal CK controls the first transistor M1 and the second transistor M2 to be turned on together, while controlling the third transistor M3 and the fourth transistor M4 to be turned off together; Alternatively, the first clock signal CK controls the first transistor M1 and the second transistor M2 to be turned off together, while controlling the third transistor M3 and the fourth transistor M4 to be turned on together. do. Accordingly, the channel types of the first transistor (M1) and the second transistor (M2) are the same, the channel types of the third transistor (M3) and the fourth transistor (M4) are the same, and the channel types of the third transistor (M3) and the fourth transistor (M4) are the same. 1 Transistor (M1) must be installed so that the channel types are different.

Optionally, the first transistor (M1) and the second transistor (M2) are each an N-type transistor, and the third transistor (M3) and the fourth transistor (M4) are each a P-type transistor; Alternatively, the first transistor M1 and the second transistor M2 are each a P-type transistor, and the third transistor M3 and the fourth transistor M4 are each an N-type transistor. FIG. 3 exemplarily shows that the first transistor M1 and the second transistor M2 are N-type transistors, and the third transistor M3 and the fourth transistor M4 are P-type transistors. The first clock signal CK is a signal whose high and low potentials alternately change, and the first signal path 401 consisting of the first transistor (M1) and the second transistor (M2), the third transistor (M3), and the fourth The second signal path 402 composed of a transistor (M4) is controlled to be turned on alternately, and the first signal path 401 and the second signal path 402 are alternately connected to the control terminal (A1) of the driving module 10. An electrical signal is transmitted to, that is, the first signal path 401 and the second signal path 402 constitute a chopper circuit. The electrical signal transmitted to the control terminal (A1) of the driving module 10 output by the storage module 30 is alternately transmitted to the driving module 10 through the first signal path 401 and the second signal path 402. is output to the control stage (A1), and the interference signal can be coupled and filtered in the alternating process.

Since the frequency of potential change of the first clock signal CK is relatively high, the frequency with which the first signal path 401 and the second signal path 402 are alternately turned on is relatively high, and the control stage of the driving module 10 ( It is more advantageous in filtering high-frequency interference signals among electrical signals transmitted through A1). Meanwhile, the interference signal among the electrical signals transmitted to the control terminal (A1) of the driving module 10 mainly uses high-frequency interference signals, and therefore, the embodiment of the present application is transmitted to the control terminal (A1) of the driving module 10. Further improves the filtering effect of interference signals in transmitted electrical signals. Meanwhile, the turn-on and turn-off states of the plurality of transistors are all controlled by the first clock signal line, which is advantageous in reducing the number of clock signal lines.

Figure 4 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application. A first clock signal is simultaneously applied to two control terminals among the control terminal of the first transistor (M1), the control terminal of the second transistor (M2), the control terminal of the third transistor (M3), and the control terminal of the fourth transistor (M4). (CK) is connected, and the other two of the control terminal of the first transistor (M1), the control terminal of the second transistor (M2), the control terminal of the third transistor (M3), and the control terminal of the fourth transistor (M4) A second clock signal (CKB) is simultaneously connected to the control terminal. The frequencies of the first clock signal (CK) and the second clock signal (CKB) are the same, and the potential heights are opposite.

Referring to Figure 4, the first transistor (M1) and the third transistor (M3) are each an N-type transistor, and the second transistor (M2) and the fourth transistor (M4) are each a P-type transistor. When the first clock signal (CK) is high potential and the second clock signal (CKB) is low potential, the electrical signal is transmitted through the first signal path 401 consisting of the first transistor (M1) and the second transistor (M2). transmitted to the control terminal (A1) of the driving module 10; When the first clock signal (CK) is at a low potential and the second clock signal (CKB) is at a high potential, the electrical signal is transmitted through the second signal path 402 consisting of the third transistor (M3) and the fourth transistor (M4). It is transmitted to the control terminal (A1) of the driving module 10. The channel types of the first transistor (M1) and the second transistor (M2) in the first signal path 401 are different, and the channels of the third transistor (M3) and the fourth transistor (M4) in the second signal path 402 are different. Since the types are different, during the turn-on and turn-off process of the first signal path 401, the characteristics of the first transistor (M1) and the second transistor (M2) are complementary, and the characteristic curve of the first transistor (M1) and the second transistor (M1) are complementary. The characteristic curve of the transistor M2 has an intersection point, that is, an operating equilibrium point, and it is advantageous for the first transistor M1 and the second transistor M2 to operate at each equilibrium point, which is advantageous for reducing the leakage current of the transistor. , further improving the stability of the pixel driving circuit. Likewise, during the turn-on and turn-off process of the second signal path 402, the characteristics of the third transistor M3 and the fourth transistor M4 are complementary, thereby improving the stability of the pixel driving circuit.

Referring to FIGS. 2 to 4 , optionally, the pixel driving circuit may further include a first reset module 50, and the first reset module 50 operates the control terminal A1 of the driving module 10. It is configured to reset, preventing abnormal light emission of the light emitting element (LED) due to the potential transmitted to the control terminal (A1) of the driving module 10 when switching between two frame screens on the display panel due to the influence of the previous frame, It is advantageous for improving the stability of the pixel driving circuit and the display effect of the display panel.

Continuing to refer to FIGS. 2 to 4, optionally, a reset signal (Reset) is connected to the control terminal (E1) of the first reset module 50, and the first terminal (E2) of the first reset module 50 ) is connected to the first power signal (VDD), and the second terminal (E3) of the first reset module 50 is electrically connected to the driving signal output terminal (C3) of the storage module 30. Since the first power signal VDD is relatively stable, resetting the control stage A1 of the driving module 10 using the first power signal VDD is advantageous for further improving the stability of the pixel driving circuit. .

Continuing to refer to FIGS. 2 to 4 , optionally, the first reset module 50 includes an 11th transistor MA1, and the control terminal of the 11th transistor MA1 is connected to the first reset module 50. It is set as the control stage (E1), the first stage of the 11th transistor (MA1) is set as the first stage (E2) of the first reset module 50, and the 2nd stage of the 11th transistor (MA1) is set as the first reset stage. This is the second stage (E3) of the module 50. By installing the first reset module 50 in this way, it is advantageous to manufacture the 11th transistor MA1 and other transistors in the pixel driving circuit in the same manufacturing process, which is advantageous in reducing manufacturing difficulty and reducing the cost of the pixel driving circuit. It is advantageous to do so. In addition, the control method of the 11th transistor MA1 is simple, which is advantageous in reducing control costs.

Continuing to refer to FIGS. 2 to 4 , optionally, the pixel driving circuit further includes a second reset module 60, wherein the second reset module 60 is connected to the first end (G1) of the light emitting element (LED). It is configured to reset the display panel when switching between two frames, preventing abnormal light emission of the light emitting element (LED) due to the potential of the first stage of the light emitting element (LED) being influenced by the previous frame, and pixel driving circuit. further improves the stability and display effect of the display panel.

Continuing to refer to FIGS. 2 to 4, optionally, a reset signal (Reset) is connected to the control terminal (F1) of the second reset module 60, and the first terminal (F2) of the second reset module 60 ) is electrically connected to the first terminal (G1) of the light emitting device (LED), and the second terminal (F3) of the second reset module 60 is electrically connected to the second terminal (G2) of the light emitting device (LED). Connected, that is, the second reset module 60 and the light emitting element (LED) are connected in parallel. Since the second reset module 60 and the light emitting device (LED) are connected in parallel, when the second reset module 60 is turned on, the first end (G1) and the second end (G2) of the light emitting device (LED) This short circuit prevents abnormal light emission of the light emitting element (LED) due to the potential of the first stage of the light emitting element (LED) being influenced by the previous frame when switching between two frame screens on the display panel, thereby stabilizing the pixel driving circuit. further improves.

Continuing to refer to FIGS. 2 to 4 , optionally, the second reset module 60 includes a twelfth transistor MA2, and the control terminal of the twelfth transistor MA2 is connected to the second reset module 60. It is set as the control stage (F1), the first stage of the twelfth transistor (MA2) is set as the first stage (F2) of the second reset module 60, and the second stage of the twelfth transistor (MA2) is set as the second reset stage. This is the second stage (F3) of the module 60. By installing the second reset module 60 in this way, it is advantageous to manufacture the twelfth transistor MA2 and other transistors in the pixel driving circuit in the same manufacturing process, which is advantageous in reducing manufacturing difficulty and reducing the cost of the pixel driving circuit. It is advantageous to do so. In addition, the control method of the twelfth transistor MA2 is simple, which is advantageous in reducing control costs.

1 to 4, optionally, a scanning signal (SCAN) is connected to the control terminal (B1) of the data writing module 20, and a data signal is connected to the first terminal (B2) of the data writing module 20. (DATA) is connected, the second terminal (B3) of the data writing module 20 is electrically connected to the data signal input terminal (C2) of the storage module 30, and the first power signal input terminal of the storage module 30 A first power signal (VDD) is connected to (C1), and a second power signal (VSS) is connected to the second power signal input terminal (C4) of the storage module 30.

2 to 4, optionally, the storage module 30 includes a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), and an eighth transistor (M8). The first terminal of the fifth transistor M5 and the first terminal of the sixth transistor M6 become the first power signal input terminal C1 of the storage module 30 after short circuit, and the control terminal of the fifth transistor M5 and the first terminal of the sixth transistor M6 become the first power signal input terminal C1 of the storage module 30 after short circuit. The second terminal of the 6th transistor (M6), the control terminal of the 7th transistor (M7), and the 1st terminal of the 8th transistor (M8) become the data signal input terminal (C2) of the storage module 30 after short circuit, and the 5th terminal The second terminal of the transistor M5, the control terminal of the sixth transistor M6, the first terminal of the seventh transistor M7, and the control terminal of the eighth transistor M8 are connected to the driving signal of the storage module 30 after short circuit. It becomes the output terminal (C3), and the second terminal of the seventh transistor (M7) and the second terminal of the eighth transistor (M8) become the second power signal input terminal (C4) of the storage module 30 after short circuit.

The types of the fifth transistor M5 and the seventh transistor M7 are different, and the types of the sixth transistor M6 and the eighth transistor M8 are different. The fifth transistor (M5) and the seventh transistor (M7) constitute the first inverter (38), and the control stage of the fifth transistor (M5) and the seventh transistor (M7) is the inverter of the first inverter (38). It is the input terminal (H1), and the second terminal of the fifth transistor (M5) and the first terminal of the seventh transistor (M7) are the inverting input terminal (H2) of the first inverter (38). Likewise, the sixth transistor (M6) and the eighth transistor (M8) constitute the second inverter (39), and the control terminal of the sixth transistor (M6) and the eighth transistor (M8) is of the second inverter (39). It is an inverting input terminal (J1), and the second terminal of the sixth transistor (M6) and the first terminal of the eighth transistor (M8) are the inverting input terminal (J2) of the second inverter (39). The inverting input terminal (H1) of the first inverter (38) and the inverting input terminal (J2) of the second inverter (39) are electrically connected, and the inverting input terminal (H2) of the first inverter (38) and the second inverter (39) are electrically connected. The inverting input terminal (J1) of (39) is electrically connected, that is, the first inverter (38) and the second inverter (39) form an anti-parallel connection relationship and form the storage module (30).

Continuing to refer to FIGS. 2 to 4 , optionally, the data writing module 20 includes a ninth transistor M9, and the control terminal of the ninth transistor M9 is connected to the control terminal of the data writing module 20. (B1), the first terminal of the ninth transistor (M9) is the first terminal (B2) of the data writing module 20, and the second terminal of the ninth transistor (M9) is the data writing module (20). This is the second stage (B3). The driving module 10 includes a tenth transistor (M10), the control terminal of the tenth transistor (M10) is the control terminal (A1) of the driving module 10, and the first terminal of the tenth transistor (M10) is is set as the first stage (A2) of the driving module 10, and the second stage of the tenth transistor (M10) is set as the second stage (A3) of the driving module 10.

Figure 5 is a schematic diagram of a driving sequence of a pixel driving circuit provided in an embodiment of the present application. 4 and 5, the driving sequence of the pixel driving circuit includes a first step (T1), a second step (T2), and a third step (T3). The second transistor (M2), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the ninth transistor (M9), the tenth transistor (M10), the eleventh transistor (MA1), and 12 The transistor MA2 is a P-type transistor, the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 are N-type transistors, and the first power signal VDD ) is a high potential, and the second power signal (VSS) is a low potential.

In the first stage (T1), the reset signal (Reset) is at a low potential, the first clock signal (CK) is at a low potential, the second clock signal (CKB) is at a high potential, and the data signal (DATA) is at a low potential. and the scanning signal (SCAN) is high potential. The 11th transistor MA1 is turned on in response to the low voltage level of the reset signal (Reset), and the first power signal (VDD) is connected to the control terminal of the 10th transistor (M10) and the driving signal output terminal (C3) of the storage module 30. is entered into The 11th transistor MA1 performs reset initialization on the control terminal of the 10th transistor M10, and since the storage module 30 has a bidirectional transmission function, the 11th transistor MA1 is connected to the storage module 30. The sixth transistor (M6) is turned off in response to the high potential of the first power signal (VDD), and the eighth transistor (M8) is turned on in response to the high potential of the first power signal (VDD). The second power signal (VSS) is output to the control terminal of the fifth transistor (M5) and the seventh transistor (M7), and the driving signal output terminal (C3) of the storage module 30 is output to the first power signal (VDD). Maintains high potential output. The tenth transistor M10 is turned off in response to the high potential of the electrical signal transmitted to the control terminal A1 of the driving module 10. The twelfth transistor MA2 is turned on in response to the low potential of the reset signal Reset, inputs the second power signal VSS to the first terminal G1 of the light emitting device LED, and The first stage (G1) and the second stage (G2) have the same potential, initialization is performed on the first stage of the light emitting device (LED), and the light emitting device (LED) maintains a state in which it does not emit light.

In the second stage (T2), the reset signal (Reset) is at a high potential, the first clock signal (CK) is at a high potential, the second clock signal (CKB) is at a low potential, and the data signal (DATA) is at a high potential. , and the scanning signal (SCAN) is low potential. The 11th transistor MA1 and the 12th transistor MA2 are turned off in response to the high potential of the reset signal Reset. The ninth transistor M9 is turned on in response to the low potential of the scan signal SCAN and transmits the high potential of the data signal DATA to the driving signal output terminal C3 of the storage module 30. latches the corresponding data signal (DATA) and outputs a low potential of the second power signal (VSS). The first transistor M1 is turned on in response to the high voltage level of the first clock signal CK, the second transistor M2 is turned on in response to the low voltage level of the second clock signal CKB, and the third transistor ( M3) is turned off in response to the low voltage level of the second clock signal CKB, and the fourth transistor M4 is turned off in response to the high voltage level of the first clock signal CK. The low potential of the second power signal (VSS) is transmitted to the control terminal of the tenth transistor (M10) through the first transistor (M1) and the second transistor (M2), and the tenth transistor (M10) receives the second power signal. In response to a low potential of (VSS), it is turned on to output a driving current, and the light emitting device (LED) is driven to emit light.

In the third stage (T3), the reset signal (Reset) is at a high potential, the first clock signal (CK) alternates between high and low potentials, and the second clock signal (CKB) alternates between high and low potentials, The potentials of the first clock signal CK and the second clock signal CKB are opposite to each other, the data signal DATA has a low potential, and the scan signal SCAN has a high potential. The 11th transistor MA1 and the 12th transistor MA2 are turned off in response to the high potential of the reset signal Reset. The ninth transistor M9 is turned off in response to the high potential of the scan signal SCAN, and the storage module 30 racks the data signal DATA of the second stage T2, and continues to use the second power signal ( VSS) outputs low potential. The first signal path 401 and the second signal path 402 are alternately turned on, and the second power signal VSS is alternately turned on through the first signal path 401 and the second signal path 402. It is transmitted to the control terminal of the transistor M10, and the tenth transistor M10 is turned on in response to the low potential of the second power signal VSS, outputs a driving current, and drives the light emitting device LED to emit light.

Embodiments of the present application further provide a display panel. Figure 6 is a structural schematic diagram of a display panel provided in an embodiment of the present application. Referring to FIG. 6, the display panel includes a plurality of pixel driving circuits 1 provided in any embodiment of the present application, and therefore, the display panel provided in the embodiment of the present application also includes the pixel driving circuit 1 provided in the embodiment of the present application. It has technical effects, but is not explained again here.

The display panel further includes a plurality of scan lines (2) and a plurality of data lines (3), and a plurality of scan lines (2) and a plurality of data lines (3) are formed in the space (4) formed by crossing the plurality of scan lines (2) and the plurality of data lines (3). A pixel driving circuit (1) is installed, the control terminal of the data writing module is electrically connected to the corresponding scan line (2), and the first end of the data writing module is electrically connected to the corresponding data line (3). do. The pixel driving circuit receives a scan signal transmitted from the gate driving module 5 through a corresponding scan line 2, and receives a data signal from the source driving circuit 6 through a corresponding data line 3, The display panel thereby implements the display function. Optionally, the display panel may be an organic light emitting display panel.

An embodiment of the present application further provides a display device, which includes a display panel provided by any embodiment of the present application, and the display panel includes a plurality of pixel driving circuits provided by any embodiment of the present application. do. The display device may be a mobile phone, a computer, or an electronic device such as a wearable device, and the embodiments of the present application do not limit the form of the display device. The display device provided in the embodiment of the present application also has the technical effects described in the above embodiment, and the description will not be repeated here.

Claims (13)

It includes a driving module, a data writing module, a storage module and an interference filtering module;
The driving module drives the light emitting element to emit light;
The data writing module is configured to write a data signal to the storage module, and the storage module adjusts a time for writing the first power signal and the second power signal to the control terminal of the driving module according to the data signal, configured to maintain the potential of a control stage of the driving module;
The interference filtering module is configured to filter interference signals among the electrical signals transmitted to the control terminal of the driving module,
The signal input terminal of the interference filtering module is electrically connected to the driving signal output terminal of the storage module, and the signal output terminal of the interference filtering module is electrically connected to the control terminal of the driving module,
The interference filtering module includes a first signal path and a second signal path, and the input end of the first signal path and the input end of the second signal path become the signal input end of the interference filtering module after short-circuiting, and the first signal path becomes a signal input end of the interference filtering module. The output end of the signal path and the output end of the second signal path become the signal output end of the interference filtering module after short-circuiting, and the first signal path and the second signal path are turned on alternately,
The first signal path includes a first transistor and a second transistor, the first terminal of the first transistor is the input terminal of the first signal path, and the second terminal of the first transistor is the input terminal of the second transistor. It is electrically connected to the first stage, and the second stage of the second transistor is the output stage of the first signal path;
The second signal path includes a third transistor and a fourth transistor, the first terminal of the third transistor is the input terminal of the second signal path, and the second terminal of the third transistor is the input terminal of the fourth transistor. A pixel driving circuit electrically connected to the first stage and the second stage of the first transistor, and wherein the second stage of the fourth transistor is an output stage of the second signal path. According to claim 1,
A first clock signal is simultaneously connected to two control terminals of the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor, and the first transistor A second clock signal is simultaneously connected to the other two control terminals of the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor, and the first clock signal and the A pixel driving circuit characterized in that the frequency of the second clock signal is the same and the potential height is opposite. According to claim 1,
A pixel driving circuit, wherein the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are short-circuited and then connected to the first clock signal. The method according to any one of claims 1 to 3,
Further comprising a first reset module configured to reset the control stage of the driving module,
A reset signal is connected to the control terminal of the first reset module, a first power signal is connected to the first terminal of the first reset module, and the second terminal of the first reset module is a driving signal output terminal of the storage module. A pixel driving circuit characterized in that it is electrically connected to. The method according to any one of claims 1 to 3,
Further comprising a second reset module configured to reset the first stage of the light emitting device,
A reset signal is connected to the control terminal of the second reset module, the first terminal of the second reset module is electrically connected to the first terminal of the light emitting device, and the second terminal of the second reset module is connected to the light emitting device. A pixel driving circuit characterized in that it is electrically connected to the second stage of. The method according to any one of claims 1 to 3,
A scan signal is connected to the control terminal of the data writing module, the data signal is connected to the first terminal of the data writing module, and the second terminal of the data writing module is electrically connected to the data signal input terminal of the storage module. and the first power signal is connected to a first power signal input terminal of the storage module, and the second power signal is connected to a second power signal input terminal of the storage module. According to claim 6,
The storage module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
The first terminal of the fifth transistor and the first terminal of the sixth transistor become the first power signal input terminal of the storage module after short circuit, the control terminal of the fifth transistor, the second terminal of the sixth transistor, and the first terminal of the sixth transistor. The control terminal of the 7th transistor and the first terminal of the eighth transistor become the data signal input terminal of the storage module after short circuit, the second terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the seventh transistor The first stage and the control stage of the eighth transistor become the driving signal output stage of the storage module after a short circuit, and the second stage of the seventh transistor and the second stage of the eighth transistor become the second power source of the storage module after a short circuit. A pixel driving circuit characterized by being a signal input terminal. A display panel comprising a plurality of pixel driving circuits according to any one of claims 1 to 3,
The display panel further includes a plurality of scan lines and a plurality of data lines, the plurality of pixel driving circuits are installed in a space formed by crossing the plurality of scan lines and the plurality of data lines, and the data writing module A display panel wherein the control terminal is electrically connected to a corresponding scan line, and the first terminal of the data writing module is electrically connected to the corresponding data line. delete delete delete delete delete