WO2021036299A1

WO2021036299A1 - Pixel driving circuit and display panel

Info

Publication number: WO2021036299A1
Application number: PCT/CN2020/086034
Authority: WO
Inventors: 黄飞
Original assignee: 成都辰显光电有限公司
Priority date: 2019-08-30
Filing date: 2020-04-22
Publication date: 2021-03-04
Also published as: KR102593643B1; KR20220025055A; CN113936586B; CN113936586A

Abstract

A pixel driving circuit (1) and a display panel. The pixel driving circuit (1) comprises a drive module (10), a data write module (20), a storage module (30), and an interference filter module (40), wherein the drive module (10) is configured to drive a light-emitting device (LED) to emit light; the data write module (20) is configured to write a data signal to the storage module (30); the storage module (30) is configured to regulate, according to the data signal, the time when a first power supply signal (VDD) and a second power supply signal (VSS) are written to a control end (A1) of the drive module (10), and is configured to maintain the potential of the control end (A1) of the drive module (10); and the interference filter module (40) is configured to filter out an interference signal in an electric signal transmitted to the control end (A1) of the drive module (10).

Description

Pixel driving circuit and display panel

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with application number 201910816892.5 on August 30, 2019. The entire content of this application is incorporated into this application by reference.

Technical field

The present application relates to the field of display technology, for example, to a pixel driving circuit and a display panel.

Background technique

With the continuous development of display technology, the application range of display panels has become wider and wider, and people's requirements for display panels have become higher and higher.

The pixel driving circuit in the display panel plays a very important role in driving the light-emitting device to emit light stably. However, the performance of the related pixel driving circuit is not yet ideal, and there is a problem of poor stability.

Summary of the invention

The present application provides a pixel driving circuit and a display panel to improve the stability of the pixel driving circuit.

A pixel driving circuit includes:

A driving module configured to drive the light-emitting device to emit light;

Data writing module;

A storage module, the data writing module is configured to write a data signal into the storage module, and the storage module is configured to adjust a first power signal and a second power signal to write the control of the drive module according to the data signal Terminal time, and the potential of the control terminal configured to maintain the drive module;

The interference filtering module is configured to filter interference signals in the electrical signals transmitted to the control terminal of the driving module.

The present application also provides a display panel, including: a plurality of pixel driving circuits as described in any of the embodiments of the present application, the display panel further including a plurality of scan lines and a plurality of data lines, the plurality of scan lines A plurality of pixel driving circuits are arranged in the space formed by intersecting the plurality of data lines, the control end of the data writing module is electrically connected to the corresponding scan line, and the first end of the data writing module is electrically connected to the corresponding scan line. The data line is electrically connected.

In the embodiment of the present application, an interference filtering module is provided in the pixel drive circuit, and the interference filtering module is used to filter interference signals in the electrical signals transmitted to the control terminal of the drive module, thereby improving the electrical signals transmitted to the control terminal of the drive module. The transmission quality and stability of the drive module are not easily affected by the interference signal, and the stability is better. It improves the problem that the effective data signal is interfered, which will cause the light-emitting device to emit unstable or weaken light. It is beneficial to improve the stability of the pixel driving circuit, thereby ensuring continuous and stable light emission of the light-emitting device. In addition, in the embodiment of the present application, when the display panel undergoes factory tests such as reliability testing, the pixel driving circuit is subject to more interference and can maintain stable working performance, thereby improving the yield and competitiveness of the display panel.

Description of the drawings

FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application;

2 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application;

3 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application;

4 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application;

FIG. 5 is a schematic diagram of driving timing of a pixel driving circuit provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the application.

detailed description

The application will be further described in detail below with reference to the drawings and embodiments. The reason for the poor stability of the pixel drive circuit lies in the fact that there are more parasitic resistances and capacitances in the signal transmission path, which makes the effective data signal susceptible to interference, resulting in unstable or weakened light emission of the light-emitting device. , The pixel drive circuit has the problem of poor stability.

The embodiment of the present application provides a pixel driving circuit. The pixel driving circuit can be used to drive light emitting devices such as Micro Light Emitting Diode (micro-LED/μLED) or Organic Light-Emitting Diode (OLED). In addition, the pixel driving circuit can use a digital driving method to control the brightness of the light-emitting device.

FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application. Referring to FIG. 1, the pixel driving circuit includes: a driving module 10, a data writing module 20, a storage module 30 and an interference filtering module 40. The driving module 10 is configured to drive the light emitting device LED to emit light. The data writing module 20 is configured to write the data signal DATA into the storage module 30. The storage module 30 is configured to adjust the time when the first power signal VDD and the second power signal VSS are written into the control terminal A1 of the driving module 10 according to the data signal DATA, and is configured to maintain the potential of the control terminal A1 of the driving module 10. The interference filtering module 40 is configured to filter interference signals in the electrical signals transmitted to the control terminal A1 of the driving module 10.

The driving module 10 is configured as a circuit module that drives the light-emitting device LED to emit light. For example, the driving module 10 is controlled by the output signal of the storage module 30 to transmit a driving signal to the light-emitting device LED. The driving signal may be a current driving signal or a voltage driving signal. Exemplarily, in the digital driving method, the magnitude of the driving signal is constant, and the gray scale displayed by the light-emitting device LED depends on the sustaining time of the driving signal. The longer the sustaining time of the driving signal, the higher the gray scale displayed by the light-emitting device LED ; On the contrary, the shorter the sustaining time of the driving signal, the lower the gray scale displayed by the light-emitting device LED, so as to realize the control of different gray scales.

The data writing module 20 is configured to write the data signal DATA into the circuit module provided by the pixel driving circuit. Exemplarily, the data writing module 20 is controlled by the scan signal SCAN and transmits a data signal DATA to the storage module 30. The pulse width of the data signal DATA determines the width of the signal output by the storage module 30, that is, the first power signal VDD and The sustaining time of the second power signal VSS in turn determines the sustaining time of the driving signal.

The storage module 30 is configured to maintain the potential of the control terminal A1 of the drive module 10. Here, the storage module 30 can maintain the potential output by the storage module 30, that is, the potential of the first power signal VDD and the second power signal VSS, and then maintain the potential of the control terminal A1 of the drive module 10 until the data writing module 20 writes The potential of the data signal DATA changes.

The interference filter module 40 is configured as a circuit module that filters out interference signals in the electrical signal transmitted to the control terminal A1 of the drive module 10, that is, the interference filter module can filter out the first power signal VDD or the second power signal VSS. The interference signal, since the time when the first power signal VDD and the second power signal VSS are written into the control terminal A1 of the drive module 10 depends on the data signal written by the data writing module 20, the interference filtering module 40 can also eliminate The interference signal in the data signal written by the data writing module 20 interferes with the first power signal VDD or the second power signal VSS output from the storage module 30 to the control terminal A1 of the drive module 10, which improves the control terminal of the drive module 10. The potential stability of A1 further improves the stability of the pixel drive circuit.

In the embodiment of the present application, an interference filtering module 40 is provided in the pixel driving circuit, and the interference filtering module 40 is configured to filter interference signals in the electrical signals transmitted to the control terminal A1 of the driving module 10, thereby improving the transmission to the driving module. The transmission quality and stability of the electrical signal of the control terminal A1 of 10, so that the potential of the control terminal A1 of the drive module 10 is not easily affected by the interference signal, and the stability is better, which improves the effective data signal DATA. The problem of unstable or weakened light emission of the light-emitting device LED helps to improve the stability of the pixel driving circuit, thereby ensuring the continuous and stable light emission of the light-emitting device LED. In addition, in the embodiment of the present application, when the display panel undergoes factory tests such as reliability tests, the data signal DATA is subject to more interference and stable working performance can be maintained, thereby improving the yield and competitiveness of the display panel.

Continuing to refer to Figure 1, the signal input terminal D1 of the interference filtering module 40 is electrically connected to the drive signal output terminal C3 of the storage module 30, and the signal output terminal D2 of the interference filtering module 40 is electrically connected to the control terminal A1 of the drive module 10, namely The interference filtering module 40 is connected in series between the storage module 30 and the drive module 10, so that before the control terminal A1 of the drive module 10 inputs the electrical signal, the interference signal in the electrical signal is filtered, and the input to the drive module is improved 10's control terminal A1's potential stability.

FIG. 2 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application. Referring to FIG. 2, the interference filtering module 40 may include: a first signal path 401 and a second signal path 402. The input terminal D1-1 of the first signal path 401 and the input terminal D2-1 of the second signal path 402 are short-circuited. As the signal input terminal D1 of the interference filtering module 40, the output terminal D1-2 of the first signal path 401 and the output terminal D2-2 of the second signal path 402 are short-circuited as the signal output terminal D2 of the interference filtering module 40, The first signal path 401 and the second signal path 402 are turned on alternately.

In order to maintain the LED of the light-emitting device to emit light, the effective signal in the electrical signal output by the storage module 30 and transmitted to the control terminal A1 of the drive module 10 will remain constant for a certain period of time, while the output by the storage module 30 is transmitted to the control of the drive module 10 The frequency of the interference signal in the electrical signal of the terminal A1 will be higher than the frequency of the effective signal. The first signal path 401 and the second signal path 402 are turned on alternately, that is, the first signal path 401 and the second signal path 402 form a chopper circuit, and the electrical signal output by the storage module 30 is transmitted to the control terminal A1 of the drive module 10 The first signal path 401 and the second signal path 402 are alternately output to the control terminal A1 of the driving module 10, and the interference signal can be coupled and filtered out during the alternating process.

It should be noted that there are multiple ways of setting up the first signal path 401 and the second signal path 402, and several of the multiple setting ways will be described below, but they are not meant to limit the application.

Continuing to refer to FIG. 2, the first signal path 401 may include a thirteenth transistor M13, the first end of the thirteenth transistor M13 is used as the input terminal D1-1 of the first signal path 401, and the second end of the thirteenth transistor M13 is used as The output terminal D1-2 of the first signal path 401. The second signal path 402 includes a fourteenth transistor M14. The first terminal of the fourteenth transistor M14 serves as the input terminal D2-1 of the second signal path 402, and the second terminal of the fourteenth transistor M14 serves as the input terminal D2-1 of the second signal path 402. The output terminal D2-2.

The embodiment of the present application adopts the configuration of the interference filtering module 40 described above: In the first aspect, the thirteenth transistor M13 and the fourteenth transistor M14 respectively constitute a single-tube transmission gate. Due to the capacitive filtering effect of the single-tube transmission gate itself, it is beneficial to Filter out the clutter interference in the electric signal transmitted to the control terminal A1 of the drive module 10, and improve the transmission quality of the electric signal transmitted to the control terminal A1 of the drive module 10. In the second aspect, the display area of the display panel needs to be set relatively With more pixels, the space reserved for the pixel drive circuit is limited, and the structure of the interference filtering module is simple, which is beneficial to increase the aperture ratio of the display panel. In the third aspect, the thirteenth transistor M13 and the fourteenth transistor M14 can be driven by the pixel. The other transistors in the circuit are prepared in the same manufacturing process, which helps to reduce the difficulty of preparation, thereby helping to reduce the cost of the pixel driving circuit; the fourth aspect is to control the control of the thirteenth transistor M13 and the fourteenth transistor M14 alternately turning on The method is simple and helps reduce control costs.

Optionally, the channel types of the thirteenth transistor M13 and the fourteenth transistor M14 may be different, and the control terminal of the thirteenth transistor M13 and the control terminal of the fourteenth transistor M14 are connected to the first clock signal CK. The first clock signal CK is a signal with alternating high and low potentials, and the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on alternately under the control of the first clock signal CK. The thirteenth transistor M13 is an N-type transistor and the fourteenth transistor M14 is a P-type transistor; or the thirteenth transistor M13 is a P-type transistor and the fourteenth transistor M14 is an N-type transistor. FIG. 2 exemplarily shows a case where the thirteenth transistor M13 is an N-type transistor and the fourteenth transistor M14 is a P-type transistor. Under the alternate potential control of the first clock signal CK, the thirteenth transistor M13 and the fourteenth transistor M14 are alternately turned on to transmit an electrical signal to the control terminal A1 of the driving module 10.

FIG. 3 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application. 3, the first signal path 401 may include a first transistor M1 and a second transistor M2, the first terminal of the first transistor M1 is used as the input terminal D1-1 of the first signal path 401, and the second terminal of the first transistor M1 It is electrically connected to the first terminal of the second transistor M2, and the second terminal of the second transistor M2 serves as the output terminal D1-2 of the first signal path 401. The second signal path 402 includes a third transistor M3 and a fourth transistor M4. The first terminal of the third transistor M3 serves as the input terminal D2-1 of the second signal path 402, and the second terminal of the third transistor M3 is connected to the fourth transistor M4. The first terminal of the first transistor M1 is electrically connected to the second terminal of the first transistor M1, and the second terminal of the fourth transistor M4 serves as the output terminal D2-2 of the second signal path 402.

The embodiment of the application is set up as follows: In the first aspect, due to the capacitive filtering effect of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, it is beneficial to filter out the control terminal A1 transmitted to the driving module 10. The clutter interference in the electrical signal can improve the transmission quality of the electrical signal transmitted to the control terminal A1 of the drive module 10. In the second aspect, since the display area of the display panel needs to be provided with more pixels, it is reserved for the pixel drive circuit The space is limited, and the structure of the interference filtering module is simple, which is beneficial to increase the aperture ratio of the display panel. In the third aspect, each transistor can be prepared in the same manufacturing process with other transistors in the pixel drive circuit, which is beneficial to reduce the difficulty of manufacturing, thereby It is beneficial to reduce the cost of the pixel driving circuit; in the fourth aspect, the control method of alternate conduction of each transistor is simple, which is beneficial to reduce the control cost.

In the foregoing embodiment, there are multiple control modes for the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. Several of them are described below, but they are not intended to limit the application.

Continuing to refer to FIG. 3, the control terminal of the first transistor M1, the control terminal of the second transistor M2, the control terminal of the third transistor M3, and the control terminal of the fourth transistor M4 are short-circuited and then connected to the first clock signal CK. The first clock signal CK controls the first transistor M1 and the second transistor M2 to turn on together, while controlling the third transistor M3 and the fourth transistor M4 to turn off together; or, the first clock signal CK controls the first transistor M1 and the second transistor M1 to turn off. While the transistors M2 are turned off together, the third transistor M3 and the fourth transistor M4 are controlled to be turned on together. Therefore, it is necessary to set the channel types of the first transistor M1 and the second transistor M2 to be the same, the channel types of the third transistor M3 and the fourth transistor M4 are the same, and the channel types of the third transistor M3 and the first transistor M1 are different.

Optionally, the first transistor M1 and the second transistor M2 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors; or, the first transistor M1 and the second transistor M2 are both P-type transistors. , The third transistor M3 and the fourth transistor M4 are both N-type transistors. FIG. 3 exemplarily shows that the first transistor M1 and the second transistor M2 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors. The first clock signal CK is a signal with alternating high and low potentials, thereby controlling the first signal path 401 formed by the first transistor M1 and the second transistor M2 and the second signal path 402 formed by the third transistor M3 and the fourth transistor M4 to alternately conduct. The first signal path 401 and the second signal path 402 alternately transmit electrical signals to the control terminal A1 of the driving module 10, that is, the first signal path 401 and the second signal path 402 form a chopper circuit. The electrical signal output by the storage module 30 and transmitted to the control terminal A1 of the drive module 10 is alternately output to the control terminal A1 of the drive module 10 through the first signal path 401 and the second signal path 402, and the interference signal can be coupled during the alternating process. Filtered.

Since the frequency of the potential change of the first clock signal CK is relatively high, the frequency at which the first signal path 401 and the second signal path 402 are alternately turned on is relatively high, which is more conducive to filtering out the signal transmitted to the control terminal A1 of the driving module 10 High-frequency interference signals in electrical signals. The interference signals in the electrical signals transmitted to the control terminal A1 of the drive module 10 are mainly high-frequency interference signals. Therefore, the embodiment of the present application further improves the interference signals in the electrical signals transmitted to the control terminal A1 of the drive module 10 The filtering effect. In addition, the on and off states of the multiple transistors are controlled by the first clock signal line, which is beneficial to reduce the number of clock signal lines.

FIG. 4 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the application. Two of the control terminal of the first transistor M1, the control terminal of the second transistor M2, the control terminal of the third transistor M3, and the control terminal of the fourth transistor M4 are simultaneously connected to the first clock signal CK, and the first transistor M1 The other two control terminals of the control terminal of the second transistor M2, the control terminal of the third transistor M3, and the control terminal of the fourth transistor M4 are simultaneously connected to the second clock signal CKB. The frequencies of the first clock signal CK and the second clock signal CKB are equal and the potentials are opposite.

Referring to FIG. 4, the first transistor M1 and the third transistor M3 are both N-type transistors, and the second transistor M2 and the fourth transistor M4 are both P-type transistors. When the first clock signal CK is at a high potential and the second clock signal CKB is at a low potential, it is transmitted to the control terminal A1 of the driving module 10 through the first signal path 401 formed by the first transistor M1 and the second transistor M2; When the clock signal CK is at a low potential and the second clock signal CKB is at a high potential, the electrical signal is transmitted to the control terminal A1 of the driving module 10 through the second signal path 402 formed by the third transistor M3 and the fourth transistor M4. Since the channel types of the first transistor M1 and the second transistor M2 in the first signal path 401 are different, the channel types of the third transistor M3 and the fourth transistor M4 in the second signal path 402 are different. During the turn-on and turn-off of the 401, the characteristics of the first transistor M1 and the second transistor M2 are complementary, and the characteristic curve of the first transistor M1 and the characteristic curve of the second transistor M2 have a cross point, that is, the working balance point, which is beneficial to the first transistor M1 and the second transistor M2. Both the one transistor M1 and the second transistor M2 work at a balance point, which helps to reduce the leakage current of the transistor and further improves the stability of the pixel driving circuit. Similarly, during the on and off of the second signal path 402, the characteristics of the third transistor M3 and the fourth transistor M4 are complementary, which improves the stability of the pixel driving circuit.

2 to 4, optionally, the pixel drive circuit may further include: a first reset module 50, the first reset module 50 is configured to reset the control terminal A1 of the drive module 10, avoiding two frames on the display panel When the screen is switched, the potential transmitted to the control terminal A1 of the driving module 10 is affected by the previous frame, resulting in abnormal light emission of the light-emitting device LED, which is beneficial to improve the stability of the pixel driving circuit and the display effect of the display panel.

Continuing to refer to FIGS. 2 to 4, optionally, the control terminal E1 of the first reset module 50 is connected to the reset signal Reset, the first terminal E2 of the first reset module 50 is connected to the first power signal VDD, and the first reset module 50 The second end E3 of the storage module 30 is electrically connected to the drive signal output end C3 of the storage module 30. Since the first power signal VDD is relatively stable, using the first power signal VDD to reset the control terminal A1 of the driving module 10 is beneficial to further improve the stability of the pixel driving circuit.

Continuing to refer to FIGS. 2 to 4, optionally, the first reset module 50 includes an eleventh transistor MA1, the control terminal of the eleventh transistor MA1 serves as the control terminal E1 of the first reset module 50, and the first reset module 50 has a control terminal E1 of the eleventh transistor MA1. One end is used as the first end E2 of the first reset module 50, and the second end of the eleventh transistor MA1 is used as the second end E3 of the first reset module 50. The arrangement of the first reset module 50 in this way facilitates the preparation of the eleventh transistor MA1 and other transistors in the pixel driving circuit in the same manufacturing process, which is beneficial to reduce the difficulty of preparation, thereby helping to reduce the cost of the pixel driving circuit; in addition, The control method of the eleventh transistor MA1 is simple, which is beneficial to reduce the control cost.

Continuing to refer to FIGS. 2 to 4, optionally, the pixel driving circuit further includes a second reset module 60 configured to reset the first terminal G1 of the light-emitting device LED, avoiding two frames on the display panel When the screen is switched, the potential of the first end of the light-emitting device LED is affected by the previous frame, which causes the phenomenon of abnormal light emission of the light-emitting device LED, which further improves the stability of the pixel driving circuit and the display effect of the display panel.

Continuing to refer to Figures 2 to 4, optionally the control terminal F1 of the second reset module 60 is connected to the reset signal Reset, the first terminal F2 of the second reset module 60 is electrically connected to the first terminal G1 of the light emitting device LED, and the second The second terminal F3 of the reset module 60 is electrically connected to the second terminal G2 of the light emitting device LED, that is, the second reset module 60 is connected in parallel with the light emitting device LED. Since the second reset module 60 is connected in parallel with the light-emitting device LED, when the second reset module 60 is turned on, the first terminal G1 and the second terminal G2 of the light-emitting device LED are short-circuited, thereby avoiding switching between two frames of the display panel At this time, the potential of the first end of the light-emitting device LED is affected by the previous frame, which causes the phenomenon of abnormal light emission of the light-emitting device LED, which further improves the stability of the pixel driving circuit.

Continuing to refer to FIGS. 2 to 4, optionally, the second reset module 60 includes a twelfth transistor MA2, the control terminal of the twelfth transistor MA2 serves as the control terminal F1 of the second reset module 60, and the second reset module 60 One end is used as the first terminal F2 of the second reset module 60, and the second terminal of the twelfth transistor MA2 is used as the second terminal F3 of the second reset module 60. The arrangement of the second reset module 60 in this way facilitates the preparation of the twelfth transistor MA2 and other transistors in the pixel drive circuit in the same manufacturing process, which is beneficial to reduce the difficulty of preparation, and thus is beneficial to reduce the cost of the pixel drive circuit; in addition, The control method of the twelfth transistor MA2 is simple, which is beneficial to reduce the control cost.

1 to 4, optionally, the control terminal B1 of the data writing module 20 is connected to the scan signal SCAN, the first terminal B2 of the data writing module 20 is connected to the data signal DATA, and the second terminal B2 of the data writing module 20 is connected to the data signal DATA. Terminal B3 is electrically connected to the data signal input terminal C2 of the storage module 30, the first power signal input terminal C1 of the storage module 30 is connected to the first power signal VDD, and the second power signal input terminal C4 of the storage module 30 is connected to the second power supply The signal VSS.

2 to 4, optionally, the storage module 30 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the first end of the fifth transistor M5 and the first end of the sixth transistor M6 One end is short-circuited as the first power signal input terminal C1 of the memory module 30, the control terminal of the fifth transistor M5, the second terminal of the sixth transistor M6, the control terminal of the seventh transistor M7, and the first terminal of the eighth transistor M8. The terminal is shorted as the data signal input terminal C2 of the memory module 30, the second terminal of the fifth transistor M5, the control terminal of the sixth transistor M6, the first terminal of the seventh transistor M7 and the control terminal of the eighth transistor M8 are shorted The second terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8 are short-circuited and used as the second power signal input terminal C4 of the memory module 30.

The fifth transistor M5 and the seventh transistor M7 are of different types, and the sixth transistor M6 and the eighth transistor M8 are of different types. The fifth transistor M5 and the seventh transistor M7 constitute the first inverter 38, the control terminals of the fifth transistor M5 and the seventh transistor M7 are the inverting input terminal H1 of the first inverter 38, and the fifth transistor M5 is the first inverter 38. The second terminal and the first terminal of the seventh transistor M7 serve as the inverted output terminal H2 of the first inverter 38. Similarly, the sixth transistor M6 and the eighth transistor M8 constitute the second inverter 39, the control terminals of the sixth transistor M6 and the eighth transistor M8 are the inverting input terminal J1 of the second inverter 39, and the sixth transistor The second terminal of M6 and the first terminal of the eighth transistor M8 serve as the inverted output terminal J2 of the second inverter 39. The inverting input terminal H1 of the first inverter 38 is electrically connected to the inverting output terminal J2 of the second inverter 39, and the inverting output terminal H2 of the first inverter 38 is inverted from the inverting output terminal H2 of the second inverter 39. The input terminal J1 is electrically connected, that is, the first inverter 38 and the second inverter 39 form an anti-parallel connection relationship, forming the memory module 30.

Continuing to refer to FIGS. 2 to 4, optionally, the data writing module 20 includes a ninth transistor M9, the control terminal of the ninth transistor M9 serves as the control terminal B1 of the data writing module 20, and the first terminal of the ninth transistor M9 serves as The first terminal B2 of the data writing module 20 and the second terminal of the ninth transistor M9 serve as the second terminal B3 of the data writing module 20. The driving module 10 includes a tenth transistor M10, the control terminal of the tenth transistor M10 is used as the control terminal A1 of the driving module 10, the first terminal of the tenth transistor M10 is used as the first terminal A2 of the driving module 10, and the second terminal of the tenth transistor M10 is The end is used as the second end A3 of the driving module 10.

FIG. 5 is a schematic diagram of a driving sequence of a pixel driving circuit provided by an embodiment of the application. 4 and 5, the driving timing of the pixel driving circuit includes: a first phase T1, a second phase T2, and a third phase T3. The second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, the eleventh transistor MA1, and the twelfth transistor MA2 are P-type transistors, and the first transistor M1 , The third transistor M3, the seventh transistor M7, and the eighth transistor M8 are N-type transistors, the first power signal VDD is at a high potential, and the second power signal VSS is at a low potential.

In the first stage T1, the reset signal Reset is at a low level, the first clock signal CK is at a low level, the second clock signal CKB is at a high level, the data signal DATA is at a low level, and the scan signal SCAN is at a high level. The eleventh transistor MA1 is turned on in response to the low level of the reset signal Reset, and the first power signal VDD is input to the control terminal of the tenth transistor M10 and the drive signal output terminal C3 of the memory module 30. The eleventh transistor MA1 resets and initializes the control terminal of the tenth transistor M10, and because the memory module 30 has the function of bidirectional transmission, the eleventh transistor MA1 realizes the reset initialization of the memory module 30, and the sixth transistor M6 responds to the first The power signal VDD is turned off at the high potential, and the eighth transistor M8 is turned on in response to the high potential of the first power signal VDD, and the second power signal VSS is output to the control terminals of the fifth transistor M5 and the seventh transistor M7 to store The drive signal output terminal C3 of the module 30 maintains the high level output of the first power signal VDD. The tenth transistor M10 is turned off in response to the high potential of the electrical signal transmitted to the control terminal A1 of the driving module 10. The twelfth transistor MA2 is turned on in response to the low potential of the reset signal Reset, and the second power signal VSS is input to the first terminal G1 of the light emitting device LED. The first terminal G1 and the second terminal G2 of the light emitting device LED have the same potential. The first end of the light-emitting device LED is initialized, and the light-emitting device LED remains in a non-luminous state.

In the second stage T2, the reset signal Reset is at a high level, the first clock signal CK is at a high level, the second clock signal CKB is at a low level, the data signal DATA is at a high level, and the scan signal SCAN is at a low level. The eleventh transistor MA1 and the twelfth transistor MA2 are turned off in response to the high potential of the reset signal Reset. The ninth transistor M9 is turned on in response to the low potential of the scan signal SCAN, and transmits the high potential of the data signal DATA to the drive signal output terminal C3 of the memory module 30. The memory module 30 latches the data signal DATA and outputs the second power signal VSS is low, the first transistor M1 is turned on in response to the high level of the first clock signal CK, the second transistor M2 is turned on in response to the low level of the second clock signal CKB, and the third transistor M3 is turned on in response to the second clock signal CKB is turned off at the low level, the fourth transistor M4 is turned off in response to the high level of the first clock signal CK, and the low potential of the second power signal VSS is transmitted to the tenth transistor through the first transistor M1 and the second transistor M2. At the control end of M10, the tenth transistor M10 is turned on in response to the low potential of the second power signal VSS, outputs a driving current, and drives the light-emitting device LED to emit light.

In the third stage T3, the reset signal Reset is at a high potential, the high and low potentials of the first clock signal CK alternate, the high and low potentials of the second clock signal CKB alternate, and the potentials of the first clock signal CK and the second clock signal CKB are alternated. On the contrary, the data signal DATA is at a low potential, and the scan signal SCAN is at a high potential. The eleventh transistor MA1 and the twelfth transistor MA2 are turned off in response to the high potential of the reset signal Reset. The ninth transistor M9 is turned off in response to the high potential of the scan signal SCAN, and the memory module 30 latches the data signal DATA of the second stage T2, and continues to output the low potential of the second power signal VSS. The first signal path 401 and the second signal path 402 are turned on alternately, and the second power signal VSS is alternately transmitted to the control terminal of the tenth transistor M10 through the first signal path 401 and the second signal path 402. The tenth transistor M10 responds to the first signal path 401 and the second signal path 402. The second power signal VSS is turned on at a low potential, outputs a driving current, and drives the light-emitting device LED to emit light.

The embodiment of the present application also provides a display panel. FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the application. Referring to FIG. 6, the display panel includes a plurality of pixel driving circuits 1 as provided in any embodiment of the present application. Therefore, the display panel provided in the embodiment of the present application also has the technical effects described in the foregoing embodiments, and will not be omitted here. Go into details.

The display panel also includes: a plurality of scan lines 2 and a plurality of data lines 3; a space 4 formed by a plurality of scan lines 2 and a plurality of data lines 3 is provided with a plurality of pixel driving circuits 1; control of the data writing module The terminal is electrically connected to the corresponding scan line 2, and the first terminal of the data writing module is electrically connected to the corresponding data line 3. The pixel drive circuit receives the scan signal sent by the gate drive module 5 through the corresponding scan line 2 and receives the data signal of the source drive circuit 6 through the corresponding data line 3, and the display panel realizes the display function accordingly. Alternatively, the display panel may be an organic light emitting display panel.

An embodiment of the present application further provides a display device, including a display panel as provided in any embodiment of the present application, and the display panel includes a plurality of pixel driving circuits as provided in any embodiment of the present application. The display device may be a mobile phone, or may be an electronic device such as a computer or a wearable device, and the embodiment of the present application does not limit the specific form of the display device. The display device provided by the embodiment of the present application also has the technical effects described in the above-mentioned embodiment, which will not be repeated here.

Claims

A pixel driving circuit includes:

A driving module configured to drive the light-emitting device to emit light;

Data writing module;

A storage module, the data writing module is configured to write a data signal into the storage module, and the storage module is configured to adjust a first power signal and a second power signal to write the control of the drive module according to the data signal Terminal time, and the potential of the control terminal configured to maintain the drive module;

The interference filtering module is configured to filter the interference signals in the electrical signals transmitted to the control terminal of the driving module.
The pixel driving circuit according to claim 1, wherein the signal input terminal of the interference filtering module is electrically connected to the drive signal output terminal of the storage module, and the signal output terminal of the interference filtering module is electrically connected to the drive signal output terminal of the storage module. The control end of the module is electrically connected.
3. The pixel driving circuit according to claim 2, wherein the interference filtering module comprises:

The first signal path and the second signal path, the input end of the first signal path and the input end of the second signal path are short-circuited as the signal input end of the interference filtering module, and the first signal path The output terminal of and the output terminal of the second signal path are short-circuited as the signal output terminal of the interference filtering module, and the first signal path and the second signal path are turned on alternately.
4. The pixel driving circuit according to claim 3, wherein the first signal path includes a first transistor and a second transistor, the first end of the first transistor is used as an input end of the first signal path, and The second end of the first transistor is electrically connected to the first end of the second transistor, and the second end of the second transistor is used as the output end of the first signal path;

The second signal path includes a third transistor and a fourth transistor, the first end of the third transistor is used as the input end of the second signal path, and the second end of the third transistor is connected to the fourth transistor. The first end of and the second end of the first transistor are electrically connected, and the second end of the fourth transistor is used as the output end of the second signal path.
The pixel driving circuit according to claim 4, wherein the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are The two control terminals are simultaneously connected to the first clock signal, the other of the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor The two control terminals are simultaneously connected to a second clock signal, and the frequencies of the first clock signal and the second clock signal are equal and the potentials are opposite.
The pixel driving circuit according to claim 4, wherein the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor are short-circuited Then access the first clock signal.
The pixel driving circuit according to any one of claims 1-6, further comprising:

The first reset module is configured to reset the control terminal of the drive module.
8. The pixel driving circuit according to claim 7, wherein the control terminal of the first reset module is connected to a reset signal, the first terminal of the first reset module is connected to a first power signal, and the first reset module The second end of the storage module is electrically connected to the drive signal output end of the storage module.
The pixel driving circuit according to any one of claims 1-6, further comprising:

A second reset module, the second reset module is configured to reset the first end of the light-emitting device.
9. The pixel driving circuit according to claim 9, wherein the control terminal of the second reset module is connected to a reset signal, the first terminal of the second reset module is electrically connected to the first terminal of the light-emitting device, so The second end of the second reset module is electrically connected to the second end of the light-emitting device.
The pixel drive circuit according to any one of claims 1 to 6, wherein the control end of the data writing module is connected to a scan signal, and the first end of the data writing module is connected to the data signal, so The second end of the data writing module is electrically connected to the data signal input end of the storage module, the first power signal input end of the storage module is connected to the first power signal, and the second power supply of the storage module The signal input terminal is connected to the second power signal.
11. The pixel driving circuit according to claim 11, wherein the storage module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

The first terminal of the fifth transistor and the first terminal of the sixth transistor are short-circuited and used as the first power signal input terminal of the memory module. The control terminal of the fifth transistor and the first terminal of the sixth transistor The second terminal, the control terminal of the seventh transistor, and the first terminal of the eighth transistor are short-circuited as the data signal input terminal of the memory module. The second terminal of the fifth transistor, the sixth terminal The control terminal of the transistor, the first terminal of the seventh transistor, and the control terminal of the eighth transistor are short-circuited as the drive signal output terminal of the storage module. The second terminal of the seventh transistor and the control terminal of the eighth transistor are short-circuited. The second terminal of the eight transistors is short-circuited and used as the second power signal input terminal of the storage module.
A display panel, comprising a plurality of pixel driving circuits according to any one of claims 1-12, the display panel further comprising a plurality of scan lines and a plurality of data lines, the plurality of scan lines and the plurality of data lines The multiple pixel drive circuits are arranged in the space formed by the intersection of the data lines, the control end of the data writing module is electrically connected to the corresponding scan line, and the first end of the data writing module is connected to the corresponding data line. Electric connection.