KR100700843B1 - Voltage Controller and Driving Method of Light Emitting Display Using The Same - Google Patents

Abstract

The present invention relates to a voltage adjusting unit capable of displaying an image having a desired luminance.

The voltage regulator of the present invention is selected by the voltage generator for generating a plurality of voltages and the counting signal, and a plurality of voltages for outputting any one of two or more voltages supplied from the voltage generator in response to the control signal. And a voltage selector.

With this arrangement, the present invention controls the desired pixel current to flow while gradually decreasing the increase / decrease range of the voltage supplied to the pixel.

Description

Voltage controller and driving method of light emitting display device using same {Voltage Controller and Driving Method of Light Emitting Display Using The Same}             

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an embodiment of the data integrated circuit shown in FIG. 2.

4 is a block diagram illustrating another embodiment of the data integrated circuit shown in FIG. 2.

FIG. 5 is a detailed block diagram illustrating the voltage adjuster illustrated in FIGS. 3 and 4.

FIG. 6 is a diagram illustrating turn-on and turn-off timings of the switching device illustrated in FIG. 5.

FIG. 7 is a diagram illustrating a voltage range controlled by the voltage adjusting unit shown in FIG. 5.

FIG. 8 is a diagram illustrating an embodiment of the voltage adjuster illustrated in FIG. 5.

FIG. 9 is a circuit diagram illustrating the voltage generator illustrated in FIG. 8.

FIG. 10 is a diagram illustrating another embodiment of the voltage regulator shown in FIG. 5.

FIG. 11 is a diagram illustrating still another embodiment of the voltage adjusting unit illustrated in FIG. 5.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: image display unit 40,140: pixel

50,150: timing controller 129: data integrated circuit

200: shift register portion 210: sampling latch portion

220: holding latch portion 230: voltage digital to analog converter

240: current digital-analog converter 250: voltage regulator

252: comparison unit 254: voltage control unit

256: control unit 260: buffer unit

270: level shifter 300: voltage generator

302,304,306,308,310: Voltage selector

The present invention relates to a voltage adjusting unit and a method of driving a light emitting display device using the same. More particularly, the present invention relates to a voltage adjusting unit and a method of driving a light emitting display device using the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device emits light from a light emitting device by supplying a current corresponding to the data signal to the light emitting device using a transistor formed for each pixel.

1 illustrates a conventional light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed in an area partitioned by scan lines S1 to Sn and data lines D1 to Dm; Controlling the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20 The timing control part 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal.

The image display unit 30 receives the first power source VDD and the second power source VSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power source VDD and the second power source VSS receives a current flowing from the first power source VDD to the second power source VSS via the light emitting element in response to the data signal. The control generates light corresponding to the data signal.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, in the related art, light having a desired luminance may not be generated due to a nonuniform threshold voltage of a transistor included in each of the pixels 40. In the related art, there is no method of measuring and controlling the current flowing in each of the pixels 40 in response to the data signal.

Accordingly, it is an object of the present invention to provide a voltage adjusting unit and a method of driving a light emitting display device using the same so as to display an image having a desired luminance.

In order to achieve the above object, the first aspect of the present invention is a voltage generator for generating a plurality of voltages and at least two voltages selected by the counting signal, corresponding to the control signal supplied from the voltage generator A voltage regulator including a plurality of voltage selectors for outputting any one of them is provided.

Preferably, the voltage selection unit is composed of l (l is a natural number), the voltage range that can be supplied from each of the l voltage selection unit is set differently. The voltage range is set lower from the first voltage selector to the l-th voltage selector. The first voltage selector is sequentially selected from the first voltage selector by the counting signal. The voltage range of the first voltage selector is set to be 1/2 lower than the voltage range of the first voltage selector.

According to a second aspect of the present invention, there is provided a first step of generating a gradation voltage and a gradation current corresponding to data, a second step of supplying the gradation voltage to pixels, and a pixel flowing in the pixels in response to the gradation voltage. And a third step of adjusting a voltage value of the gradation voltage by comparing a current with the gradation current, wherein the third step is repeated l (l is a natural number) and the pixel current and the gradation current become the same or similar. The present invention provides a method of driving a light emitting display device that increases or decreases the voltage value.

Preferably, in the third step, the increase and decrease of the voltage value is lowered from the first to the l-th. The increase and decrease range of the l-th voltage is set to be 1/2 lower than the increase and decrease range of the l-1 th voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 11 which can be easily implemented by those skilled in the art.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention includes pixels formed in regions partitioned by scan lines S1 to Sn, data lines D1 to Dm, and feedback lines F1 to Fm. An image display unit 130 including 140, a scan driver 110 for driving the scan lines S1 to Sn, a data driver 120 for driving the data lines D1 to Dm, and a scan. A timing controller 150 for controlling the driver 110 and the data driver 120 is provided.

The image display unit 130 includes pixels 140 connected to the scan lines S1 to Sn, the data lines D1 to Dm, and the feedback lines F1 to Fm. The scan lines S1 to Sn are formed in a horizontal direction to supply scan signals to the pixels 140. The data lines D1 to Dm are formed in the vertical direction to supply data signals to the pixels 140. The feedback lines F1 to Fm supply the pixel current supplied from the pixels 140 to the data driver 120 in response to the data signal. To this end, the feedback lines F1 to Fm are formed in the same direction (that is, the vertical direction) with the data lines D1 to Dm. The feedback lines F1 to Fm receive current from the pixels 140 to which the current data signal is supplied. In other words, the pixel current generated in the pixels 140 currently receiving the scan signal is supplied to the data driver 120 via the feedback lines F1 to Fm.

On the other hand, the pixels 140 are supplied with the first power source VDD and the second power source VSS from the outside. Each of the pixels 140 supplied with the first power source VDD and the second power source VSS has a second power source via the light emitting element from the first power source VDD in response to a data signal from the data line D. FIG. The current (pixel current) flowing to VSS is controlled. The pixels 140 supply the pixel current to the feedback line F when the data signal is supplied to the data line D. FIG.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal. Here, the data driver 120 supplies a predetermined gray scale voltage to the data lines D as a data signal.

The data driver 120 receives the pixel current from each of the pixels 140 via the feedback lines F1 to Fm. The data driver 120 receiving the pixel current checks whether the current value of the pixel current corresponds to the data. For example, when the pixel current to flow in the pixel 140 corresponding to the number of bits (or gradation value) of the data (Data) is 10 ㎂, the data driver 120 checks whether the pixel current supplied to it is 10 ㎂ do. Here, when the desired current is not supplied from each of the pixels 140, the data driver 120 changes the gray voltage so that a desired current flows from each of the pixels 140. To this end, the data driver 120 includes at least one data integrated circuit 129 including j channels (where j is a natural number).

3 is a view illustrating in detail the data integrated circuit shown in FIG. 2.

Referring to FIG. 3, the data integrated circuit 129 may include a shift register unit 200 for sequentially generating sampling signals, and a sampling latch unit 210 for sequentially storing data in response to the sampling signals. The data data of the sampling latch unit 210 may be temporarily stored, and the stored data may be stored in a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 230 and a current digital-to-analog converter. Holding latch 220 for supplying to the 240 (hereinafter referred to as " IDAC unit "), VDAC unit 230 for generating a gradation voltage Vdata corresponding to the gradation value of data Data, and data Changing the gray scale voltage Vdata in response to the IDAC unit 240 generating the gray scale current Idata corresponding to the gray scale value of Data and the pixel current Ipixel supplied from the feedback lines F1 to Fj. The voltage adjusting block 250 and the gray scale voltage Vdata supplied from the voltage adjusting block 250. And a buffer unit 260 for supplying to the data lines (D1 to Dj).

The shift register unit 200 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 200 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 200 includes j shift registers 2001 to 200j.

The sampling latch unit 210 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 200. Here, the sampling latch unit 210 includes j sampling latches 2101 to 210j to store j data. Each of the sampling latches 2101 to 210j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2101 to 210j is set to a size of k bits.

The holding latch unit 220 receives data from the sampling latch unit 210 and stores the data when the source output enable signal SOE is input. The holding latch unit 220 supplies data stored therein to the VDAC unit 230 and the IDAC unit 240 when the source output enable signal SOE is input. To this end, the holding latch unit 220 includes j holding latches 2201 to 220j set to k bits.

The VDAC unit 230 generates a gray voltage Vdata corresponding to a bit value (that is, a gray value) of the data Data, and supplies the generated gray voltage Vdata to the voltage adjusting block 250. Here, the VDAC unit 230 generates j gray voltages Vdata corresponding to j data Data supplied from the holding latch unit 220.

The IDAC unit 240 generates a gradation current Idata corresponding to the bit value of the data, and supplies the generated gradation current Idata to the voltage adjusting block 250. Here, the IDAC unit 240 generates j gradation currents Idata corresponding to j data Data supplied from the holding latch unit 220.

The voltage adjustment block 250 is supplied with a gray voltage Vdata, a gray current Idata, and a pixel current Ipixel. The voltage adjusting block 250 supplied with the gradation voltage Vdata, the gradation current Idata, and the pixel current Ipixel compares the current difference between the gradation current Idata and the pixel current Ipixel, and compares the current difference with each other. Correspondingly, the gradation voltage Vdata is adjusted. Ideally, the voltage adjusting block 250 adjusts the voltage value of the gray voltage Vdata so that the gray current Idata and the pixel current Ipixel can be set to the same value. To this end, the voltage adjusting block 250 includes j voltage adjusting units 2501 to 250j.

The buffer unit 260 supplies the gray voltages supplied from the voltage adjusting block 250 to the j data lines D1 to Dj. To this end, the buffer unit 260 includes j buffers 2601 to 260j.

Meanwhile, in the present invention, as shown in FIG. 4, the level shifter unit 270 may be further included between the holding latch unit 220, the VDAC unit 230, and the IDAC unit 240. The level shifter unit 270 increases the voltage level of the data Data supplied from the holding latch unit 220 and supplies it to the VDAC unit 230 and the IDAC unit 240. When data having a high voltage level is supplied to the data integrated circuit 129 from an external system, a manufacturing cost increases because circuit components corresponding to the voltage level need to be installed. Therefore, the data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level sheeter 270 to a high voltage level.

FIG. 5 is a view illustrating in detail the voltage adjusting unit illustrated in FIG. 4. In FIG. 5, the j th voltage adjustor 250j is illustrated for convenience of description.

Referring to FIG. 5, the voltage adjusting unit 250j includes a comparing unit 252, a voltage adjusting unit 254, a control unit 256, a first capacitor C1, and a switching device M1.

The switching element M1 is provided between the VDAC unit 230 and the buffer 260j. The switching device M1 is turned on or turned off under the control of the controller 256. In practice, the switching element M1 is turned on only in the data signal supply period (first period) during one horizontal period as shown in Fig. 6, and is turned off in the other feedback period (second period).

The first capacitor C1 is provided between the first node N1, which is a common terminal of the switching element M1, and the buffer 260j, and the voltage adjusting unit 254. The first capacitor C1 installed between the first node N1 and the voltage adjusting unit 254 increases or decreases the voltage value of the first node N1 in response to the voltage supplied from the voltage adjusting unit 254. That is, when a high voltage is supplied from the voltage adjusting unit 254, the voltage value of the first node N1 is increased by the first capacitor C1, and when a low voltage is supplied from the voltage adjusting unit 254, the first capacitor is supplied. The voltage value of the first node N1 is decreased by C1. Meanwhile, in FIG. 5, although the first capacitor C1 is illustrated as one, two or more first capacitors C1 may be installed. Detailed description thereof will be described later.

The comparator 252 receives the gradation current Idata from the IDAC unit 240 and the pixel current Ipixel from the pixel 140. Here, the pixel current Ipixel is supplied from the pixel 140 to which the current data signal is supplied. The comparison unit 252 supplied with the pixel current Ipixel and the gradation current Idata compares the gradation current Idata and the pixel current Ipixel, and compares the first control signal or the second control signal corresponding to the result of the comparison. Is supplied to the voltage adjusting unit 254. For example, the comparator 252 generates the first control signal when the gradation current Idata is greater than the pixel current Ipixel, and the second control signal when the gradation current Idata is smaller than the pixel current Ipixel. Is generated and supplied to the voltage adjusting unit 254.

The voltage adjustor 254 supplies a voltage value corresponding to the first control signal or the second control signal to the first capacitor C1. For example, the voltage adjustor 254 supplies a predetermined voltage to the first capacitor C1 so that the voltage of the first node N1 is lowered when the first control signal is input. Here, when the voltage of the first node N1 (ie, the gray voltage Vdata) falls, the pixel current Ipixel flowing in the pixels 140 increases. The voltage adjusting unit 254 supplies a predetermined voltage to the first capacitor C1 so that the voltage of the first node N1 is increased when the second control signal is input. Herein, when the voltage of the first node N1 (ie, the gray voltage Vdata) increases, the pixel current Ipixel flowing in the pixels 140 decreases.

The controller 256 turns on the switching element M1 during the data signal supply period during one horizontal period 1H, and turns off the switching element M1 during the feedback period. In addition, the control unit 256 supplies a counting signal that gradually increases during the feedback period to the voltage adjusting unit 254. For example, the controller 256 supplies a counting signal to the voltage regulator 254 that is increased from " 1 " to " l " (l is a natural number). To this end, a counter (not shown) is included in the control unit 256. The counting signal of the controller 256 is initialized when the reset signal Reset is supplied. Here, the reset signal Reset is set to a signal supplied in units of one horizontal period. For example, the reset signal Reset may be used as the horizontal synchronization signal H or the scan signal.

Referring to the operation process in detail, first, the control unit 256 turns on the switching element M1 during the data signal supply period during one horizontal period 1H. When the switching device M1 is turned on, the gray voltage Vdata supplied from the VDAC unit 230 is supplied to the data line Dj via the buffer 260j. The gray voltage Vdata supplied to the data line Dj is supplied to the pixel 140 selected by the scan signal as a data signal. The pixel 140 receiving the data signal supplies the pixel current Ipixel corresponding to the data signal to the feedback line Fj.

Thereafter, the control unit 256 turns off the switching element M1 during the feedback period of one horizontal period 1H. When the switching device M1 is turned off, the first node N1 is floated. At this time, the first node N1 maintains the voltage of the gray voltage Vdata by a parasitic capacitor (not shown).

During the feedback period, the comparator 252 receives the gradation current Idata and the pixel current Ipixel supplied from the IDAC unit 240. Here, the gradation current Idata is an ideal current value that should actually flow in the pixel 140 in response to the data, and the pixel current Ipixel is a current value that actually flows in the pixel 140. The comparison unit 252, which is supplied with the pixel current Ipixel and the gradation current Idata, compares the pixel current Ipixel and the gradation current Idata, and applies the first control signal or the second control signal in response to the comparison result. It generates and supplies to the voltage regulator 254.

During the feedback period, the controller 256 supplies a counting signal, which is increased from "1" to "l", to the voltage adjusting unit 254. The voltage adjusting unit 254 receiving the counting signal supplies a predetermined voltage value to the first capacitor C1 in response to the first control signal or the second control signal supplied from the comparator 252. Here, the voltage adjusting unit 254 is a voltage value supplied to the first capacitor C1 so that the gradation current Idata and the pixel current Ipixel may be the same or similar to the first control signal or the second control signal. To control. Then, the voltage value of the first node N1 is changed corresponding to the voltage value supplied to the first capacitor C1. That is, the gray voltage Vdata applied to the first node N1 is changed in response to the voltage value supplied to the first capacitor C1, and the changed voltage is transferred to the pixel 140 via the buffer 260j. Supplied.

Then, in the pixel 140, a pixel current Ipixel corresponding to the changed gray voltage Vdata is generated. In practice, the present invention controls the pixel current Ipixel flowing through the pixel 140 to be approximately equal to the gradation current Idata while repeating the above process l times during the feedback period.

Meanwhile, the voltage range increased or decreased by the voltage adjusting unit 254 is determined by the counting signal. For example, when the first counting signal (eg, “1”) is supplied, the voltage adjustor 254 increases or decreases the voltage within the first voltage range VR1 as shown in FIG. 7. When the second counting signal (eg, “2”) is supplied, the voltage adjusting unit 254 increases or decreases the voltage within the second voltage range VR2 lower than the first voltage range VR1. Here, the second voltage range VR2 may be set to about 1/2 of the first voltage range VR2. When the third counting signal (eg, “3”) is supplied, the voltage adjustor 254 increases or decreases the voltage within the third voltage range VR3 lower than the second voltage range VR2. That is, as the counting signal is increased, the voltage range increased or decreased by the voltage controller 254 is lowered. Here, the lowering voltage range may be set to 1/2 of the previous voltage range. In this manner, the voltage adjusting unit 254 controls the voltage supplied to the first capacitor C1 so that the gray voltage Idata and the pixel current Ipixel can be the same or similar.

8 is a view showing a voltage adjusting unit according to an embodiment of the present invention. In FIG. 8, "l" is assumed to be 5 for convenience of description. That is, the voltage regulator 254 includes five voltage selectors.

Referring to FIG. 8, the voltage adjusting unit 254 according to the embodiment of the present invention may include a voltage generator 300, first voltage selectors 302 to fifth voltage selector 310, and first voltage. A first capacitor C1 is provided between each of the selectors 302 to fifth voltage selector 310 and the first node N1.

The voltage generator 300 may include the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4, the fifth voltage V5, the sixth voltage V6, and the fifth voltage V6. The seventh voltage V7 is generated, and the generated first voltages V1 to seventh voltages V7 are supplied to the voltage selectors 302 to 310. To this end, the voltage generator 300 includes a plurality of voltage divider resistors R1 to R6 installed between the first voltage V1 and the seventh voltage V7 as shown in FIG. 9. The divided resistors R1 to R6 divide the first voltage V1 and the seventh voltage V7 to generate the second voltage V2 to the sixth voltage V6.

Therefore, the voltage value of the voltage generated by the voltage generator 300 is lowered from the first voltage V1 to the seventh voltage V7. Hereinafter, for convenience of description, the first voltage V1 320 kV, the second voltage V2 160 kV, the third voltage V3 80 kV, the fourth voltage V4 40 kV, and the fifth voltage V5 20 It is assumed that the sixth voltage V6 is 10 Hz and the seventh voltage V7 is 0 Hz.

Each of the first voltage selector 302, the second voltage selector 304, the third voltage selector 306, the fourth voltage selector 308, and the fifth voltage selector 310 is a voltage generator ( Three voltages are supplied. Here, the first voltage selector 302 to the fifth voltage selector 310 are commonly supplied with the seventh voltage V7 as a reference voltage.

In detail, the first voltage selector 302 receives the first voltage V1 (high voltage), the second voltage V2 (intermediate voltage), and the seventh voltage V7 from the voltage generator 300. Low voltage). That is, the first voltage selector 302 has a voltage range of 320 kV. The first voltage selector 302, which receives the first voltage V1, the second voltage V2, and the seventh voltage V7, is supplied from the counting signal supplied from the controller 256 and the comparator 252. In response to the control signal, any one of the voltages supplied thereto is supplied to the first capacitor C1. Then, the voltage of the first node N1 changes in response to the voltage supplied from the first voltage selector 302. For example, the first voltage selector 302 is selected when a counting signal corresponding to "1" is input and outputs a second voltage V2 (intermediate voltage). The first voltage selector 302 outputs the seventh voltage V7 so that the voltage of the first node N1 is lowered when the first control signal is input from the comparator. Outputs V1).

The second voltage selector 304 supplies the second voltage V2 (high voltage), the third voltage V3 (intermediate voltage), and the seventh voltage V7 (low voltage) from the voltage generator 300. Receive. Here, the second voltage selector 304 has a voltage range 160 kV corresponding to half of the voltage range 320 kV of the first voltage selector 320. The second voltage selector 304, which receives the second voltage V2, the third voltage V3, and the seventh voltage V7, is supplied from the counting signal supplied from the controller 256 and the comparator 252. In response to the control signal, any one of the voltages supplied thereto is supplied to the first capacitor C1. Then, the voltage of the first node N1 changes in response to the voltage supplied from the second voltage selector 304. For example, the second voltage selector 304 is selected when a counting signal corresponding to "2" is input and outputs the third voltage V3. The second voltage selector 304 outputs the seventh voltage V7 so that the voltage of the first node N1 is lowered when the first control signal is input from the comparator. Outputs V2).

The third voltage selector 306 supplies the third voltage V3 (high voltage), the fourth voltage V4 (middle voltage), and the seventh voltage V7 (low voltage) from the voltage generator 300. Receive. Here, the third voltage selector 306 has a voltage range 80 kV corresponding to half of the voltage range 160 kV of the second voltage selector 304. The third voltage selector 306, which receives the third voltage V3, the fourth voltage V4, and the seventh voltage V7, is supplied from the counting signal supplied from the controller 256 and the comparator 252. In response to the control signal, any one of the voltages supplied thereto is supplied to the first capacitor C1. Then, the voltage of the first node N1 changes in response to the voltage supplied from the third voltage selector 306. For example, the third voltage selector 306 is selected when a counting signal corresponding to "3" is input and outputs the fourth voltage V4. The third voltage selector 306 outputs the seventh voltage V7 so that the voltage of the first node N1 is lowered when the first control signal is input from the comparator. Outputs V3).

The fourth voltage selector 308 supplies the fourth voltage V4 (high voltage), the fifth voltage V5 (middle voltage), and the seventh voltage V7 (low voltage) from the voltage generator 300. Receive. Here, the fourth voltage selector 308 has a voltage range 40 kV corresponding to half of the voltage range 80 kV of the third voltage selector 306. The fourth voltage selector 308, which receives the fourth voltage V4, the fifth voltage V5, and the seventh voltage V7, is supplied from the counting signal supplied from the controller 256 and the comparator 252. In response to the control signal, any one of the voltages supplied thereto is supplied to the first capacitor C1. Then, the voltage of the first node N1 changes in response to the voltage supplied from the fourth voltage selector 308. For example, the fourth voltage selector 308 is selected when a counting signal corresponding to “4” is input and outputs the fifth voltage V5. The fourth voltage selector 308 outputs the seventh voltage V7 so that the voltage of the first node N1 is lowered when the first control signal is input from the comparator. Outputs V4).

The fifth voltage selector 310 supplies a fifth voltage V5 (high voltage), a sixth voltage V6 (intermediate voltage), and a seventh voltage V7 (low voltage) from the voltage generator 300. Receive. Here, the fifth voltage selector 310 has a voltage range 20 kV corresponding to half of the voltage range 40 kV of the fourth voltage selector 308. The fifth voltage selector 310 that receives the fifth voltage V5, the sixth voltage V6, and the seventh voltage V7 is supplied from the counting signal supplied from the controller 256 and the comparator 252. In response to the control signal, any one of the voltages supplied thereto is supplied to the first capacitor C1. Then, the voltage of the first node N1 changes in response to the voltage supplied from the fifth voltage selector 310. For example, the fifth voltage selector 310 is selected when a counting signal corresponding to “5” is input and outputs a sixth voltage V6. The fifth voltage selector 310 outputs the seventh voltage V7 so that the voltage of the first node N1 is lowered when the first control signal is input from the comparator. Outputs V5).

That is, the voltage adjusting unit 254 of the present invention increases or decreases the voltage value of the first node N1 in response to the first control signal or the second control signal so that a desired pixel current Ipixel flows in the pixels 140. Let's do it. In addition, the voltage adjusting unit 254 of the present invention sets the voltage range which is increased or decreased as the counting signal increases. In other words, the voltage adjusting unit 254 of the present invention controls the desired pixel current (Ipixel) to flow in the pixels 140 while setting the voltage range which is increased or decreased as the counting signal increases.

Meanwhile, the voltage adjusting unit according to the embodiment of the present invention shown in FIG. 8 may be changed in various forms. For example, in FIG. 8, the seventh voltage V7 having the lowest voltage value is supplied to all the voltage selectors 302 to 310 as a reference voltage. However, in the present invention, as shown in FIG. 10, the highest first voltage V1 may be supplied to all of the selectors 302 to 310 as a reference voltage.

10 is a view showing a voltage adjusting unit according to another embodiment of the present invention. 10, only the voltage range supplied to the voltage selectors is changed compared to the voltage adjuster illustrated in FIG. 8, and the operation of the voltage adjuster is substantially the same.

Referring to FIG. 10, the voltage adjusting unit 254 according to the embodiment of the present invention may include a voltage generator 300, first voltage selector 302 to fifth voltage selector 310, and first voltage. A first capacitor C1 is provided between each of the selectors 302 to fifth voltage selector 310 and the first node N1.

The voltage generator 300 may include the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4, the fifth voltage V5, the sixth voltage V6, and the fifth voltage V6. The seventh voltage V7 is generated, and the generated first voltages V1 to seventh voltages V7 are supplied to the voltage selectors 302 to 310. Here, for convenience of description, the first voltage V1 320 kV, the second voltage V2 310 kV, the third voltage V3 300 kV, the fourth voltage V4 280 kV, and the fifth voltage V5 240 It is assumed that the sixth voltage V6 is 160 Hz and the seventh voltage V7 is 0 Hz.

Each of the first voltage selector 302, the second voltage selector 304, the third voltage selector 306, the fourth voltage selector 308, and the fifth voltage selector 310 is a voltage generator ( Three voltages are supplied. Here, the first voltage selector 302 to the fifth voltage selector 310 are commonly supplied with the first voltage V1 as a reference voltage.

The first voltage selector 302 receives the first voltage V1, the sixth voltage V6, and the seventh voltage V7. Therefore, the first voltage selector 302 has a voltage range of 320 kV. When the first voltage selector 302 is selected by the counting signal, the first voltage selector 302 outputs an intermediate voltage, that is, a sixth voltage V6 among the voltages input to the first voltage selector 302. Thereafter, the first voltage selector 302 supplies one of the first voltage V1 and the seventh voltage V7 to the first capacitor C1 in response to the first control signal or the second control signal. do.

The second voltage selector 304 receives the first voltage V1, the fifth voltage V5, and the sixth voltage V6. Therefore, the second voltage selector 304 has a voltage range of 160 kV. When the second voltage selector 304 is selected by the counting signal, the second voltage selector 304 outputs an intermediate voltage, that is, a fifth voltage V5 among the voltages input thereto. Thereafter, the second voltage selector 304 supplies one of the first voltage V1 and the sixth voltage V6 to the first capacitor C1 in response to the first control signal or the second control signal. do.

The third voltage selector 306 receives the first voltage V1, the fourth voltage V4, and the fifth voltage V5. Therefore, the third voltage selector 306 has a voltage range of 80 kV. When the third voltage selector 306 is selected by the counting signal, the third voltage selector 306 outputs an intermediate voltage, that is, a fourth voltage V4, among the voltages input thereto. Thereafter, the third voltage selector 306 supplies one of the first voltage V1 and the fifth voltage V5 to the first capacitor C1 in response to the first control signal or the second control signal. do.

The fourth voltage selector 308 receives the first voltage V1, the third voltage V3, and the fourth voltage V4. Therefore, the fourth voltage selector 308 has a voltage range of 40 kV. When the fourth voltage selector 308 is selected by the counting signal, the fourth voltage selector 308 outputs an intermediate voltage, that is, a third voltage V3, among the voltages input to the fourth voltage selector 308. Thereafter, the fourth voltage selector 308 supplies one of the first voltage V1 and the fourth voltage V4 to the first capacitor C1 in response to the first control signal or the second control signal. do.

The fifth voltage selector 310 receives the first voltage V1, the second voltage V2, and the third voltage V3. Accordingly, the fifth voltage selector 308 has a voltage range of 20 kV. When the fifth voltage selector 310 is selected by the counting signal, the fifth voltage selector 310 outputs an intermediate voltage, that is, the second voltage V2, among the voltages input to the fifth voltage selector 310. Thereafter, the fifth voltage selector 310 supplies one of the first voltage V1 and the third voltage V3 to the first capacitor C1 in response to the first control signal or the second control signal. do.

That is, the voltage adjusting unit 254 according to another embodiment of the present invention corresponds to the first control signal or the second control signal so that a desired pixel current Ipixel flows in the pixels 140. Increase or decrease the voltage value of. Here, the voltage selectors 302 to 310 included in the voltage adjustor 254 are supplied with the highest voltage as the reference voltage, and set the voltage range to be increased or decreased as the counting signal increases from the reference voltage. Therefore, as the counting signal increases, the voltage value of the first node N1 is adjusted so that a desired pixel current Ipixel gradually flows.

Meanwhile, in the present invention, the voltage adjustor 254 may select an intermediate voltage as a reference voltage supplied to the first voltage selector 302 to the fifth voltage selector 310 as shown in FIG. 11.

11 is a view showing a voltage adjusting unit according to another embodiment of the present invention.

Referring to FIG. 11, the voltage adjusting unit 254 according to another embodiment of the present invention may include a voltage generator 300, first voltage selectors 302 to fifth voltage selector 310, and a first voltage selector 310. A first capacitor C1 is provided between each of the first voltage selector 302 to the fifth voltage selector 310 and the first node N1.

The voltage generator 300 may include the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4, the fifth voltage V5, the sixth voltage V6, and the fifth voltage V6. The seventh voltage V7, the eighth voltage V8, the ninth voltage V9, the tenth voltage V10, and the eleventh voltage V11 are generated, and the generated first voltages V1 to eleventh voltages ( V11) is supplied to the voltage selector 302-310. Here, for convenience of description, the first voltage (V1) 320 kV, the second voltage (V2) 240 kV, the third voltage (V3) 200 kV, the fourth voltage (V4) 180 kV, the fifth voltage (V5) 170 ㎷, 6th voltage (V6) 160㎷, 7th voltage (V7) 150㎷, 8th voltage (V8) 140㎷, 9th voltage (V9) 120㎷, 10th voltage (V10) 80㎷ and 11th voltage (V11) It is assumed to be 0 ms.

Each of the first voltage selector 302, the second voltage selector 304, the third voltage selector 306, the fourth voltage selector 308, and the fifth voltage selector 310 is a voltage generator ( Three voltages are supplied. Here, the first voltage selector 302 to the fifth voltage selector 310 are commonly supplied with the sixth voltage V6 as a reference voltage as a reference.

The first voltage selector 302 receives the first voltage V1, the sixth voltage V6, and the eleventh voltage V11. Therefore, the first voltage selector 302 has a voltage range of 320 kV. The first voltage selector 302 outputs the sixth voltage V6 when the first voltage selector 302 is selected by the counting signal, and the first voltage V1 and the eleventh when the first control signal or the second control signal is supplied. One of the voltages V11 is supplied to the first capacitor C1.

The second voltage selector 304 receives the second voltage V2, the sixth voltage V6, and the tenth voltage V10. Therefore, the second voltage selector 304 has a voltage range of 160 kV. The second voltage selector 304 outputs the sixth voltage V6 when selected by the counting signal, and outputs the sixth voltage V2 and the tenth when the first control signal or the second control signal is supplied. One of the voltages V10 is supplied to the first capacitor C1.

The third voltage selector 306 receives the third voltage V3, the sixth voltage V6, and the ninth voltage V9. Therefore, the third voltage selector 306 has a voltage range of 80 kV. The third voltage selector 306 outputs the sixth voltage V6 when selected by the counting signal, and outputs the sixth voltage V3 and the ninth when the first control signal or the second control signal is supplied. One of the voltages V9 is supplied to the first capacitor C1.

The fourth voltage selector 308 receives the fourth voltage V4, the sixth voltage V6, and the eighth voltage V8. Therefore, the fourth voltage selector 308 has a voltage range of 40 kV. The fourth voltage selector 308 outputs the sixth voltage V6 when selected by the counting signal, and outputs the fourth voltage V4 and the fourth when the first control signal or the second control signal is supplied. One of the eight voltages V8 is supplied to the first capacitor C1.

The fifth voltage selector 310 receives the fifth voltage V5, the sixth voltage V6, and the seventh voltage V7. Therefore, the fifth voltage selector 310 has a voltage range of 20 kV. The fifth voltage selector 310 outputs the sixth voltage V6 when selected by the counting signal, and the fifth voltage V5 and the seventh when the first control signal or the second control signal is supplied. One of the voltages V7 is supplied to the first capacitor C1.

That is, the voltage adjusting unit 254 according to another embodiment of the present invention corresponds to the first control signal or the second control signal so that a desired pixel current Ipixel flows in the pixels 140. Increase or decrease the voltage value of). Here, each of the voltage selectors 302 to 310 included in the voltage adjustor 254 receives an intermediate voltage as a reference voltage, and sets a low voltage range that increases or decreases as the counting signal increases from the intermediate voltage. Therefore, as the counting signal increases, the voltage value of the first node N1 is adjusted so that a desired pixel current Ipixel gradually flows.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the voltage adjusting unit and the method of driving the light emitting display device using the same according to the embodiment of the present invention, the gradation current corresponding to the data and the pixel current flowing in the pixel are compared, and the pixel current is corresponding to the compared result. By changing the gradation voltage (data signal) so that the change to a current value similar to the gradation current, an image of desired luminance can be displayed. In addition, the present invention controls the desired pixel current to flow while gradually decreasing the increase / decrease range of the voltage supplied to the pixel in response to the comparison result between the gradation current and the pixel current.

Claims (15)

A voltage adjusting unit for increasing or decreasing a voltage value supplied to a pixel in response to a counting signal and a control signal supplied from the outside; A voltage generator for generating a plurality of voltages; And a plurality of voltage selectors selected by the counting signal and configured to output any one of two or more voltages supplied from the voltage generator in response to the control signal. The method of claim 1, The voltage selector is composed of l (l is a natural number), the voltage range that can be supplied from each of the l voltage selector is set differently. The method of claim 2, And the voltage range is set lower from the first voltage selector to the l-th voltage selector. The method of claim 3, And a first voltage selector sequentially selected from the first voltage selector by the counting signal. The method of claim 3, And the voltage range of the first voltage selector is set to be 1/2 lower than the voltage range of the first voltage selector. The method of claim 5, Each of the voltage selectors receives a high voltage and a low voltage from the voltage generator and an intermediate voltage between the high voltage and the low voltage to achieve the voltage range. The method of claim 6, And the low voltages supplied to each of the voltage selectors are equally set. The method of claim 6, And the high voltages supplied to each of the voltage selectors are equally set. The method of claim 6, And an intermediate voltage supplied to each of the voltage selectors is equally set. The method of claim 6, Each of the voltage selectors outputs the intermediate voltage when selected by the counting signal, and outputs any one of the high voltage and the low voltage when the control signal is supplied. The method of claim 1, The voltage generator includes a plurality of voltage divider to generate the plurality of voltages. The method of claim 1, And a capacitor disposed between each of the voltage selectors and the first node electrically connected to the pixel. A first step of generating a gradation voltage and a gradation current corresponding to the data; Supplying the gray voltage to the pixels; Comprising a third step of adjusting the voltage value of the gray voltage by comparing the pixel current flowing in the pixels and the gray current corresponding to the gray voltage, And the third step is repeated l (l is a natural number) and increases or decreases the voltage value so that the pixel current and the gradation current become the same or similar. The method of claim 13, And in the third step, the range of increase and decrease of the voltage value is lowered from first to lth. The method of claim 14, And the increase / decrease range of the l-th voltage is set to be 1/2 lower than the increase / decrease range of the l-1 th voltage.

Images