KR100611913B1 - Data driver and light emitting display for the same - Google Patents

Abstract

The present invention relates to a data integrated circuit and a light emitting display device using the same, comprising: a latch unit configured to input the data into the voltage digital-analog converter and the current digital-analog converter in response to a sampling signal, and sequentially the sampling A shift register unit for generating a signal and transferring the signal to the latch unit, a voltage digital-analog converter for generating a gray scale voltage in response to data, a current digital-analog converter for generating a gray scale current in response to the data, and the gray voltage In response to the feedback of the pixel current flowing in the pixels, the amount of current charged in the first capacitor is increased or decreased, and the voltage level applied to the first capacitor is varied according to the increase or decrease of the amount of current, and the gray level voltage is supplied to the pixels. The voltage adjusting block of which the voltage level of the variable and the first operation and the second A data integrated circuit and a light emitting display device using the same, comprising: a switching block for switching a work, transferring the gray voltage to the pixel in the first operation, and feeding back the pixel current from the pixel to the voltage adjusting block in the second operation. To provide.

Feedback, organic EL, data driver

Description

Data integrated circuit and light emitting display device using the same {DATA DRIVER AND LIGHT EMITTING DISPLAY FOR THE SAME}

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 2.

FIG. 4 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 2.

5 is a view showing in detail the voltage adjusting block employed in the light emitting display device according to the present invention.

FIG. 6 is a circuit diagram illustrating a second embodiment of the pixel illustrated in FIG. 5.

FIG. 7 is a waveform diagram of a voltage adjusting block and a signal input to a pixel shown in FIG. 5.

*** Explanation of symbols on main parts of drawings ***

10,110: scan driver 20,120: data driver

30,130: image display unit 40,140: pixel

50,150: timing controller 129: data integrated circuit

200: shift register portion 210: sampling latch portion

220: holding latch portion 230: voltage digital to analog converter

240: current digital-analog converter 250: voltage regulator

251: current increasing unit 252: comparison unit

253 control unit 260 buffer unit

270: level shifter 280: switching unit

The present invention relates to a data integrated circuit and a light emitting display using the same, and more particularly, to a data integrated circuit and a light emitting display using the same to display an image having a desired brightness.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device emits light from a light emitting device by supplying a current corresponding to the data signal to the light emitting device using a transistor formed for each pixel.

1 illustrates a conventional light emitting display device. Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed in an area partitioned by scan lines S1 to Sn and data lines D1 to Dm; Controlling the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20 The timing control part 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal.

The image display unit 30 receives the first power source VDD and the second power source VSS from the outside and supplies the same to the pixels 40. Each of the pixels 40 supplied with the first power supply VDD and the second power supply VSS is connected to the second power supply VSS from the first power supply VDD through the light emitting device OLED in response to the data signal. By controlling the flowing current, light corresponding to the data signal is generated.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, in the related art, light having a desired luminance may not be generated due to a nonuniform threshold voltage of a transistor included in each of the pixels 40. In the related art, there is no method of measuring and controlling the current flowing in each of the pixels 40 in response to the data signal.

Accordingly, an object of the present invention is to provide a data integrated circuit and a light emitting display device using the same, capable of displaying an image having a desired brightness.

As a technical means for achieving the above object, a first aspect of the present invention is a latch unit for inputting the data into the voltage digital-analog converter and the current digital-analog converter corresponding to a sampling signal, and sequentially A shift register unit for generating a sampling signal and transferring it to the latch unit, a voltage digital-analog converter for generating a gray scale voltage in response to data, and a current digital-analog converter for generating a gray scale current in response to the data; The pixel current supplied to the first capacitor is increased or decreased by receiving a feedback of pixel current flowing through the pixels in response to the gray scale voltage, and the voltage level applied to the first capacitor is varied according to the increase or decrease of the current amount to supply the pixels. The voltage adjusting block in which the voltage level of the gray scale voltage is variable, Switching and transferring the gray voltages to the pixels in the first operation, and to provide a data driving circuit comprising a switching block for feeding back the pixel current with the voltage control unit on the pixel in the second operation.

According to a second aspect of the present invention, there is provided an image display unit including a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, and scanning signals and light emission control signals with the plurality of scan lines. A scan driver for sequentially supplying the data driver and a data driver for supplying a gradation voltage to the plurality of data lines as a data signal, wherein the data driver is one of the first to ninth embodiments of the present invention. A light emitting display device including the data integrated circuit according to the above description is provided.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 2, referring to FIG. 2, in the light emitting display device according to an exemplary embodiment of the present invention, the first scan lines S11 to S1n, the second scan lines S21 to S2n, and the light emission control lines E1 to En ) And an image display unit 130 including pixels 140 formed in regions partitioned by the data lines D1 to Dm, first scan lines S11 to S1n, and second scan lines S21 to S2n. ) And the scan driver 110 for driving the emission control lines E1 to En, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. It includes a timing controller 150 for controlling the.

The image display unit 130 is formed in an area partitioned by the first scan lines S11 to S1n, the second scan lines S21 to S2n, the emission control lines E1 to En, and the data lines D1 to Dm. Pixels 140 are provided. The pixels 140 receive a first power source VDD and a second power source VSS from an external source. Each of the pixels 140 supplied with the first power source VDD and the second power source VSS receives a second signal from the first power source VDD via a light emitting element in response to a data signal supplied from the data line D. FIG. The pixel current flowing to the power supply VSS is controlled. The pixels 140 supply the pixel current to the data driver 120 through the data line D during a part of one horizontal period.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal. Here, the data driver 120 supplies a predetermined gray scale voltage to the data lines D as a data signal.

The data driver 120 receives a pixel current from the pixels 140 during a part of the second period of one horizontal period, and checks whether the supplied pixel current has a current value corresponding to the data. For example, when the pixel current to flow in the pixel 140 corresponding to the number of bits (or gradation value) of the data (Data) is 10 ㎂, the data driver 120 checks whether the pixel current supplied to it is 10 ㎂ do. Here, when the desired current is not supplied from each of the pixels 140, the data driver 120 changes the gray voltage so that a desired current flows from each of the pixels 140. To this end, the data driver 120 includes at least one data integrated circuit 129 including j channels (where j is a natural number). The detailed configuration of the data integrated circuit 129 will be described later.

FIG. 3 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 2. Referring to FIG. 3, the data integrated circuit 129 may include a shift register unit 200 for sequentially generating sampling signals, and a sampling latch unit 210 for sequentially storing data in response to the sampling signals. The data data of the sampling latch unit 210 may be temporarily stored, and the stored data may be stored in a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 230 and a current digital-to-analog converter. Holding latch 220 for supplying to the 240 (hereinafter referred to as " IDAC unit "), VDAC unit 230 for generating a gradation voltage Vdata corresponding to the gradation value of data Data, and data Changing the gradation voltage Vdata in response to the IDAC unit 240 generating the gradation current Idata corresponding to the gradation value of Data and the pixel current Ipixel supplied from the data lines D1 to Dj. The voltage adjusting block 250 and the gray scale voltage Vdata supplied from the voltage adjusting block 250. A buffer unit 260 for supplying the data lines D1 to Dj, and a switch block for selectively connecting the data lines D1 to Dj with any one of the buffer unit 260 and the voltage adjusting block 250. 280).

The shift register unit 200 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 200 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 200 includes j shift registers 2001 to 200j.

The sampling latch unit 210 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 200. Here, the sampling latch unit 210 includes j sampling latches 2101 to 210j to store j data. Each of the sampling latches 2101 to 210j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2101 to 210j is set to a size of k bits.

The holding latch unit 220 receives data from the sampling latch unit 210 and stores the data when the source output enable signal SOE is input. The holding latch unit 220 supplies data stored therein to the VDAC unit 230 and the IDAC unit 240 when the source output enable signal SOE is input. To this end, the holding latch unit 220 includes j holding latches 2201 to 220j set to k bits.

The VDAC unit 230 generates a gray voltage Vdata corresponding to a bit value (that is, a gray value) of the data Data, and supplies the generated gray voltage Vdata to the voltage adjusting block 250. Here, the VDAC unit 230 generates j gray voltages Vdata corresponding to j data Data supplied from the holding latch unit 220. To this end, the VDAC unit 230 includes j voltage generators 2301 to 230j. Hereinafter, for convenience of description, the gray voltage Vdata generated by the VDAC unit 230 will be referred to as a first gray voltage Vdata.

The IDAC unit 240 generates a gradation current Idata corresponding to the bit value of the data, and supplies the generated gradation current Idata to the voltage adjusting block 250. Here, the IDAC unit 240 generates j gradation currents Idata corresponding to j data Data supplied from the holding latch unit 220. To this end, the IDAC unit 240 includes j current generation units 2401 to 240j.

The voltage adjusting block 250 receives a first gray voltage Vdata, a gray current Idata, and a pixel current Ipixel. The voltage adjusting block 250 supplied with the first gradation voltage Vdata, the gradation current Idata, and the pixel current Ipixel compares the current difference between the gradation current Idata and the pixel current Ipixel, and compares the currents. In response to the difference, the voltage value of the first gradation voltage Vdata is readjusted. After that, the first gray voltage Vdata readjusted by the voltage adjusting block 250 will be referred to as a second gray voltage. Ideally, the voltage adjusting block 250 controls the voltage value of the second gradation voltage so that the gradation current Idata and the pixel current Ipixel can be set to the same value. To this end, the voltage adjusting block 250 includes j voltage adjusting units 2501 to 250j.

The buffer unit 260 supplies the first gray voltage Vdata or the second gray voltage supplied from the voltage adjusting block 250 to the j data lines D1 to Dj. To this end, the buffer unit 260 includes j buffers 2601 to 260j.

The switch block 280 performs a switching operation by dividing one horizontal period 1H into a first period and a second period, and in the first period, the data lines D1 to Dj are connected to the buffer unit 260j, and the second period is connected. In the period, the buffer unit 260j and the voltage adjusting block 250 are selectively connected. To this end, the switch block 280 is provided with j switch portions (2801 to 280j). In the first period, a predetermined time is allowed to apply a sufficient voltage to the pixel.

Meanwhile, the data integrated circuit of the present invention may further include a level shifter unit 270 between the holding latch unit 220, the VDAC unit 230, and the IDAC unit 240 as shown in FIG. 4. The level shifter unit 270 increases the voltage level of the data Data supplied from the holding latch unit 220 and supplies it to the VDAC unit 230 and the IDAC unit 240. When data having a high voltage level is supplied to the data integrated circuit 129 from an external system, a manufacturing cost increases because circuit components corresponding to the voltage level need to be installed. Therefore, the data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level sheeter 270 to a high voltage level.

5 is a view showing in detail the voltage adjusting block employed in the light emitting display device according to the present invention. In FIG. 5, for convenience of description, the pixel connected to the j th voltage adjusting unit 250j and the j th voltage adjusting unit 250j will be described. Referring to FIG. 5, the voltage adjusting unit 250j includes the voltage adjusting unit 250j of the present invention including the current increasing unit 251, the comparing unit 252, the control unit 253, the first capacitor C1, and the first capacitor C1. The switching device SW1 is provided and connected to the pixel 140 through the switch unit 280j. The pixel 140 includes a pixel circuit and a light emitting device OLED, and the pixel circuit includes the first to fourth transistors M4 and the second capacitor C2.

Referring to the voltage adjusting unit 250j, the first switching device SW1 is provided between the VDAC and the current increasing and decreasing unit 251. The switching device SW1 is turned on or turned off under the control of the controller 253. In practice, the first switching device SW1 is turned on only in the first period (data signal supply period) of one horizontal period as shown in FIG. 7, and is turned off in the second period (feedback period).

The current increasing unit 251 includes second to fifth switching elements SW2 to SW5, and the second switching element SW2, the fourth switching element SW4, and the fifth switching element SW5 are P MOS transistors. The third switching device SW3 is implemented with an N MOS transistor.

The second to fifth switching elements SW5 are arranged to be connected to a source and a drain, respectively, the gate of the second switching element SW2 and the gate of the third switching element SW3 are connected to each other, and the fourth switching element SW4 is connected. The gate of and the gate of the fifth switching device (SW5) is connected. In addition, the gate of the second switching element SW2 and the gate of the third switching element SW3 are connected to the output terminal of the comparing unit 252, and according to the output signal of the comparing unit, the second switching element SW2 and the third switching element. The switching operation of (SW3) is determined.

The switching signal line CSW is connected to the gate of the fourth switching element SW4 and the gate of the fifth switching element SW5 to receive the switching signal csw through the switching signal line CSW. The switching signal line transmits a switching signal from the controller 253 and determines the on / off operation of the fourth switching device SW4 and the fifth switching device SW5.

The first power source VDD is connected to one end of the second switching device SW2, the second power source VSS is connected to one end of the third switching device SW3, and the first power source VDD is connected to the first power source VDD. The current flows from the first power supply VDD to the second power supply VSS by having a voltage higher than that of the second power supply VSS.

The comparator 252 receives the gradation current Idata from the IDAC unit 240 and the pixel current Ipixel from the pixel 140. Here, the pixel current Ipixel is supplied from the pixel 140 to which the current data signal is supplied. The comparison unit 252, which receives the pixel current Ipixel and the gradation current Idata, compares the gradation current Idata and the pixel current Ipixel, and supplies a control signal corresponding to the result of the current increase / decrease unit 251. To pass on. In this case, the control signal output from the comparator 252 may have various voltage values according to the difference between the gradation current Idata and the pixel current Ipixel. That is, if the difference between the gradation current Idata and the pixel current Ipixel is large, the absolute value of the voltage level of the control signal becomes large. If the difference between the gradation current Idata and the pixel current Ipixel is small, the voltage level of the control signal is small. The absolute value of is reduced so that the amount of current flowing through the second switching device SW2 and the third switching device SW3 varies according to the magnitude of the voltage level of the control signal.

The controller 253 turns on the first switching device SW1 during the data signal supply period during one horizontal period 1H, and turns off the first switching device SW1 during the feedback period.

In addition, the control unit 253 transfers the switching signal csw through the switching signal line CSW to control the fourth switching element SW4 and the fifth switching element SW5 of the current increase / decrease unit 251 to thereby switch the first switch. When the device SW1 is turned on, the fourth switching device SW4 and the fifth switching device SW5 are turned off so that the gray voltage received through the VDAC is transferred to the first node N1. When the first switching device SW1 is turned off, the fourth switching device SW4 and the fifth switching device SW5 are turned on so that the second switching device SW2 and the third switching device SW3 are turned on. Make a current path between them.

The first capacitor C1 is connected to the first node N1, stores the gray voltage supplied from the VDAC 230 through the current increasing unit 251, and the current flows in by the second switching device SW2. Or the current charged by the third switching device SW3 flows toward the second power supply VSS to change the gray voltage stored in the first capacitor C1.

The gray voltage is transmitted to the buffer 260j to increase the current driving capability of the gray voltage to the pixel 140. In this case, the first capacitor C1 may be a parasitic capacitor C1 of the data line.

The switch unit 280j is divided into a first switch T1 and a second switch T2, and the first switch T1 is connected between the buffer 260j and the pixel 140 to be output from the buffer 260j. The gray voltage is selectively transmitted to the pixel 140, and the second switch T2 is connected between the data line and the comparator 252 and selectively compares the pixel current Ipixel transmitted through the second transistor M2. Passed to section 252.

The first switch T1 and the second switch T2 are connected to the gate of the first scan line S1 to perform a switching operation according to the first scan signal s1 transmitted through the first scan line S1. The first switch T1 is implemented with a P MOS transistor and the second switch T2 is implemented with an N MOS transistor to maintain different states. Therefore, when the first switch T1 is turned on, the gray voltage Vdata is transmitted to the pixel, and at this time, the second switch T2 is turned off so that the gray voltage Vdata is transmitted to the comparator 252. When the second switch T2 is turned on, the pixel current Ipixel generated in the pixel is transmitted to the comparator 252, and the first switch is turned off, so that the pixel current Ipixel is supplied to the buffer 260j. Prevent delivery.

In the description of the pixel, the first transistor M1 has a source connected to the pixel power supply ELVDD, a drain connected to the second node N2, and a gate connected to the third node N3 so that the pixel current Ipixel is used. And a gray value of the pixel current Ipixel according to the voltage of the third node N3.

The second transistor M2 has a source connected to a second node N2, a drain connected to a data line, a gate connected to a second scan line S2, and a pixel current Ipixel formed by the first transistor M1. To the data line.

The third transistor M3 has a source connected to the second node N2, a drain connected to the light emitting device OLED, and a gate connected to the light emission control line E, and the light emitted through the light emission control line E. When the size of the pixel current Ipixel flowing through the second node N2 is equal to the size of the gradation current Idata when the switching operation is performed by the control signal e, the light is transmitted to the light emitting device OLED. ) To emit light.

The fourth transistor M4 switches the voltage passing through the buffer 260j to the third node N3 according to the scan signal and transfers the voltage to the third node N3 from the first transistor M1. To generate current. In this case, the gate of the fourth transistor M4 is connected to the first scan line S1 to perform a switching operation according to the first scan signal s1.

Therefore, when the first scan signal s1 is the on signal, the gray voltage Vdata is transmitted to the pixel 140, and when the second scan signal s2 is the on signal, the pixel current Ipixel is fed back and the emission control signal e Is a on signal, the pixel current Ipixel is transferred to the light emitting device OLED.

In addition, as shown in FIG. 6, the pixels may be configured by implementing the first to fourth transistors M4 as N-MOS transistors.

FIG. 7 is a waveform diagram of a voltage adjusting block and a signal input to a pixel shown in FIG. 5. Referring to FIG. 7, the operation of the voltage adjusting block and the pixel of FIG. 5 will be described in detail. First, the controller 253 first switches the first switching element SW1 during a first period (data signal supply period) of one horizontal period 1H. Turn on). When the first switching device SW1 is turned on, the gray voltage Vdata supplied from the VDAC unit 230 is output via the buffer 260j. At this time, the first switch T1 is turned on by the first scan signal s1 to supply the gray voltage Vdata to the data line Dj. The gray voltage Vdata supplied to the data line Dj is supplied to the pixel 140 selected by the first scan signal s1 as a data signal. The pixel 140 supplied with the data signal generates a pixel current Ipixel corresponding to the data signal.

Thereafter, the controller 253 turns off the first switching device SW1 during the second period of the first horizontal period 1H. When the first switching device SW1 is turned off, the first node N1 is floated. At this time, the first node N1 maintains the voltage of the gray voltage Vdata by the first capacitor C1. In this case, the first capacitor C1 may be implemented as a parasitic capacitor of a data line.

When the first switching device SW1 is turned off, the first switch T1 is turned off by the first scan signal s1 and the second switch T2 is turned on by the second scan. The second transistor M2 is turned on by the signal s2. In this case, the pixel current Ipixel generated in the pixel 140 is transferred to the data line through the second transistor M2, and the data line is connected to the comparator 252 through the second switch T2 to form the pixel 140. ), The pixel current Ipixel flowing to the comparator 252 is transmitted to the comparator 252 via the data line.

The comparison unit 252 receives the gray current Idata supplied from the IDAC unit 240 and compares the gray current Idata with the pixel current Ipixel. Here, the gradation current Idata is an ideal current value that should actually flow in the pixel 140 corresponding to the data, and the pixel current Ipixel is a current value that actually flows in the pixel 140.

The comparator 252 generates a control signal in response to a result of comparing the pixel current Ipixel and the gradation current Idata, and supplies the control signal to the current increaser 251 to supply the first capacitor C1 in the current increaser 251. The gray voltage (Vdata) applied to () is varied. Then, the first switch T1 is turned on by the first scan signal s1, the second switch T2 is turned off, and the second transistor M2 is turned on by the second scan signal s2. When turned off, the first capacitor C1 transfers the changed gray voltage value back to the pixel 140 to generate the corrected pixel current Ipixel in the pixel 140.

In the feedback period, the voltage adjusting block and the pixel 140 repeatedly perform the above operation to correct the gray voltage Vdata so that the current generated in the pixel 140 is fed back regardless of the threshold voltage of the first transistor M1. Through the process, the pixel current Ipixel having the same size as the gradation current Idata is generated to be transferred to the light emitting device OLED.

Referring to the operation of the current increasing unit 251 in detail, the control signal generated by comparing the pixel current Ipixel and the data current ratio in the comparing unit 252 is the second switching element SW2 of the current increasing unit 251. ) And one of the second switching element SW2 or the third switching element SW3 is turned on according to the voltage of the control signal. The amount of current transferred to the data line through the second switching element SW2 and the data through the third switching element SW3 according to the voltages applied to the gates of the second switching element SW2 and the third switching element SW3. The amount of current flowing out of the line is determined.

At this time, when the current is transferred to the data line or the current flows out of the data line, a change in the amount of current charged in the first capacitor C1 occurs and a predetermined voltage value stored in the first capacitor C1 is changed. Will change. This changed voltage is supplied to the pixel 140 via the buffer 260i.

In addition, during the feedback period, the controller 253 transfers the switching signal csw through the switching signal line CSW according to the signal output from the comparator 252, so that the fourth switching device SW4 of the current increase / decrease unit 251 is provided. And the fifth switching device SW5. The switching signal csw repeats the on-off operation during the feedback period to prevent the gray voltage from being changed by the first power source VDD or the second power source VSS when the first switching device SW1 is turned on. And transfer it to the first capacitor C1. Then, the pixel 140 generates the pixel current Ipixel corresponding to the predetermined voltage transmitted by the first capacitor C1.

Referring to the operation of the pixel, firstly, the fourth transistor M4 is turned on by the first scan signal s1 so that the first transistor M1 generates a pixel current Ipixel and flows to the second node N2. Let's go. The amount of the pixel current Ipixel is determined by the voltage transmitted to the third node N3 of the first transistor M1. At this time, the second transistor M2 is turned on by the first scan signal s1, and the third transistor M3 is turned off by the light emission control signal e to compare the pixel current Ipixel with the comparison unit ( 252). When the pixel current Ipixel and the gradation current Idata are the same through a feedback process, a voltage for flowing the pixel current in the second capacitor C2 is stored, and the third transistor is generated by the emission control signal e. The M3 is turned on so that the pixel current Ipixel flows to the light emitting device OLED, so that the pixel current having the same magnitude as the gradation current is generated regardless of the threshold voltage of the first transistor M1. Will flow into.

In practice, the present invention controls the pixel current Ipixel flowing in the pixel 140 to be approximately equal to the gradation current Idata while repeating the above process for the second period.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

A data integrated circuit and a light emitting display device using the same according to the present invention compare a gradation current corresponding to data with a pixel current flowing in a pixel, and in response to the comparison result, the gradation voltage so that the pixel current is changed to a current value similar to the gradation current. By changing the (data signal), an image of desired luminance can be displayed.

In particular, in the present invention, since the gradation voltage is changed by receiving a pixel current from each of the pixels, an image having a desired luminance can be displayed regardless of non-uniformity of transistors included in each of the pixels.

Claims (11)

A latch unit configured to input the data into the voltage digital-analog converter and the current digital-analog converter in response to a sampling signal; A shift register unit sequentially generating the sampling signal and transferring the sampling signal to the latch unit; A voltage digital-analog converter configured to generate grayscale voltages in correspondence with the data; A current digital-analog converter configured to generate a gradation current corresponding to the data; The pixel current flowing through the pixels in response to the gray voltage is fed back to increase or decrease the amount of current charged in the first capacitor, and the voltage level applied to the first capacitor is changed to be supplied to the pixels according to the increase or decrease of the amount of current. A voltage adjusting block in which a voltage level of the gray voltage is varied; And And a switching block for switching a first operation and a second operation, transferring the gray voltage to the pixel in the first operation, and feeding back the pixel current from the pixel to the voltage adjusting block in the second operation. Circuit. The method of claim 1, The switching block has a plurality of switch units, each of the switch unit, A first switch connected between the buffer unit and the data line and turned on in the first operation; And And a second switch connected between the data line and the voltage adjusting block to be turned on in the second operation. The method of claim 2, And the switch unit performs the first operation during a first period of one horizontal period and repeats the first operation and the second operation for a second period other than the first period. The method of claim 1, And the first capacitor is at least one capacitor of a parasitic capacitor of a data line and a capacitor connected separately. The method of claim 1, The voltage adjusting block compares the pixel current with the gradation current and increases or decreases the voltage stored in the first capacitor in response to the comparison result. The method of claim 5, The voltage adjusting block includes j voltage adjusting units for controlling j (j is a natural number) gray voltages. The method of claim 6, The voltage adjusting unit A first switching element disposed between the voltage digital-analog converter and a first node; A comparator for comparing the pixel current with the gradation current; A current increasing / decreasing unit which increases or decreases the amount of current supplied to the first capacitor under the control of the comparing unit; And And a control unit for controlling the switching element. The method of claim 7, wherein And the control unit turns on the first switching device for a first period for one horizontal period, and turns off the switching device for a second period except the first period. The method of claim 7, wherein The current increase and decrease portion A second switching element having a first electrode connected to a first power source, a second electrode connected to a first node, and a gate connected to an output terminal of the comparator; And A first switching electrode connected to a second power source, a second electrode connected to the first node, and a gate connected to the output terminal of the comparator; The second switching device and the third switching device are turned on at different times by the output of the comparator, the second switching device delivers current to the data line, and the third switching device is connected to the data line. Data integrated circuit that reduces the charged current. An image display section including a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; A scan driver for sequentially supplying a scan signal and a light emission control signal to the plurality of scan lines; And A data driver connected to the plurality of data lines and configured to supply a gray voltage to the plurality of data lines as a data signal; The data driver includes a data integrated circuit according to any one of claims 1 to 9. The method of claim 10, The pixel is Light emitting element; A first transistor configured to receive a third power source and flow a pixel current according to a voltage applied to the gate; A second transistor selectively receiving the pixel current and transferring the pixel current to a data line; A third transistor for selectively flowing the pixel current to the light emitting element; The fourth transistor configured to selectively transfer the gray voltage output from the buffer unit to the gate of the first transistor according to the scan signal; And And a second capacitor that maintains the voltage transmitted to the gate of the first transistor for a predetermined time.

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