KR100629591B1 - Sample and hold circuit and data driving circuit using the same - Google Patents

Abstract

The present invention relates to a sample and hold circuit capable of displaying an image of a desired luminance.

The sample and hold circuit of the present invention includes a first switch connected between a digital-analog converter and a driver, a second switch connected between a data line and the driver, a current source for supplying current to the driver, and the digital And a driver for charging a predetermined voltage in correspondence with the current data signal supplied from the analog converter and the current supplied from the current source.

By such a configuration, in the present invention, the charging time can be shortened while minimizing the amount of current changed due to a switching error, thereby displaying an image having a desired brightness.

Description

Sample and hold circuit and data driving circuit using the same {Sample and hold circuit and Data Driving Circuit Using the same}

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the data driving circuit shown in FIG.

FIG. 3 is a circuit diagram illustrating the sample and hold circuit shown in FIG. 2 in detail.

4 is a waveform diagram illustrating driving timings of the switches illustrated in FIG. 3.

FIG. 5 is a diagram showing a second embodiment of the data driving circuit shown in FIG.

<Explanation of symbols for the main parts of the drawings>

10: scan driver 20: data driver

30 pixel portion 40 pixel

50: timing controller 100: data driving circuit

110: shift register portion 120: sampling latch portion

130: holding latch portion 140: DAC portion

150: output stage 160: level shifter portion

170: drive unit

The present invention relates to a sample and hold circuit and a data driving circuit using the same, and more particularly, to a sample and hold circuit and a data driving circuit using the same to display an image having a desired luminance.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel displays, a light emitting display displays an image using a light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

The light emitting display device includes a plurality of pixels positioned at an intersection of the data lines and the scan lines. The pixels are selected when the scan signal is supplied to the scan line and charge a voltage corresponding to a predetermined voltage (data signal) supplied to the data line. The pixels generate light having a predetermined luminance by supplying a current corresponding to the charged voltage to the light emitting device. In this case, light of predetermined luminance emitted from each of the pixels is combined to display a predetermined image in the recovery unit.

However, the conventional pixels include a plurality of transistors, and there is a problem in that a desired image is not displayed due to variations in threshold voltages and electron mobility of the transistors. In order to overcome this problem, a method using a current as a data signal has been proposed. In fact, when current is used as the data signal, there is an advantage in that a uniform image can be displayed regardless of threshold voltage unevenness and variation in electron mobility of transistors.

Meanwhile, a plurality of sample and hold circuits are provided in the data driving circuit for supplying current. The sample and hold circuit charges a predetermined voltage in response to the current data signal supplied thereto, and receives a current corresponding to the charged voltage from the pixel via the data line. Then, each of the pixels is charged with a predetermined voltage corresponding to the current supplied to the sample and hold, and generates a predetermined light corresponding to the charged voltage.

However, since the conventional sample and hold circuit is supplied with a fine current (for example, a unit of charge) as a data signal, the transistors are driven in a sub-threshold region (that is, the voltage of Vgs is the Vth voltage). As such, when the transistors included in the sample and hold circuits are driven in the sub-threshold voltage region, a current may be sensitively changed due to a switching error. In fact, when the transistors are driven in the sub-threshold voltage region, the amount of change in current is largely set when the switching elements are turned off, and thus a desired image cannot be displayed.

In addition, the conventional sample and hold circuit does not charge the desired voltage within one horizontal period because the micro current is supplied as the data signal. As described above, when the desired voltage is not charged in the sample and hold circuit, a desired current is not supplied from the pixel, and thus, the pixel unit cannot display an image having a desired luminance.

Accordingly, an object of the present invention is to provide a sample-and-hold circuit and a data driving circuit using the same, which can display an image having a desired luminance.

In order to achieve the above object, a first aspect of the present invention provides a first switch connected between a digital-analog converter and a driver, a second switch connected between a data line and the driver, and supplying current to the driver. And a driving unit for charging a predetermined voltage corresponding to a current data signal supplied from the digital-analog converter and a current supplied from the current source.

Preferably, the first switch and the second switch are alternately turned on and off. The driving unit is connected between the first transistor and the second transistor connected in series between the first switch and the base voltage source, and between the first electrode and the gate electrode of the first transistor such that the first transistor is connected in a diode form. A third switch, a fourth switch connected between the first electrode and the gate electrode of the second transistor such that the second transistor is connected in a diode form, and connected between the gate electrode of the first transistor and the ground voltage source. And a second capacitor connected between the first capacitor and the gate electrode of the second transistor and the ground voltage source.

A second aspect of the present invention includes a digital-analog converter for generating a current data signal corresponding to a bit value of data supplied from the outside; A data driving circuit having an output stage including a plurality of sample and hold circuits according to any one of claims 1 to 6 is provided.

Preferably, the data driving circuit includes a shift register section for sequentially generating a sampling signal, and a latch section for storing the data in response to the sampling signal and supplying the stored data to the digital-analog converter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5 that can be easily implemented by those skilled in the art.

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes a pixel unit 30 including a plurality of pixels 40 connected to scan lines S1 to Sn and data lines D1 to Dm. And a scan driver 10 for driving the scan lines S1 to Sn, a data driver 20 for driving the data lines D1 to Dm, a scan driver 10 and a data driver 20 The timing control part 50 for controlling is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 which receives the scan driving control signal SCS sequentially supplies the scan signal to the scan lines S1 to Sn. That is, the scan driver 10 selects the pixels 40 to which the data signal is supplied while sequentially supplying the scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 supplied with the data driving control signal DCS receives a predetermined current corresponding to a bit value of data from the pixel 40 selected by the scan signal. That is, the data driver 20 of the present invention is configured as a current sink type in which a predetermined current is supplied from the pixel 40 in response to the data signal. To this end, the data driver 20 includes at least one data driver circuit 100. The detailed configuration of the data driving circuit 100 will be described later.

The pixel portion 30 includes pixels 40 formed at intersections of the scan lines S1 to Sn and the data lines D1 to Dm. Each of the pixels 40 receives a first power source ELVDD and a second power source ELVSS. Such pixels 40 are selected when a scan signal is supplied to supply a predetermined current to the data driver 20. In this case, each of the pixels 40 is charged with a voltage corresponding to the current supplied to the data driver 20. Afterwards, each of the pixels 40 supplies an electric current from the first power source ELVDD to the second power source ELVSS via a light emitting device (not shown) in response to the voltage charged therein, thereby providing an image having a predetermined brightness. Is displayed.

FIG. 2 is a diagram showing a first embodiment of the data driving circuit shown in FIG. In FIG. 2, it is assumed that the data driving circuit 100 has j channels where j is a natural number of two or more.

Referring to FIG. 2, the data driving circuit 100 according to the first embodiment of the present invention sequentially outputs data in response to a sampling signal and a shift register unit 110 for sequentially generating sampling signals. The sampling latch unit 120 to store the data and the data of the sampling latch unit 120 are temporarily stored, and the stored data are referred to as the digital-to-analog converter 140 (hereinafter referred to as "DAC unit"). Holding latch unit 130 for supplying the data, a DAC unit 140 for generating a predetermined current (i.e., a data signal) corresponding to the grayscale value (bit value) of the data Data, and a DAC unit An output stage 150 is provided to charge a predetermined voltage in response to the data signal supplied from 140 and to sink the current corresponding to the charged voltage from the pixels 40.

The shift register unit 110 receives a source shift clock SSC and a source start pulse SSP from the timing controller 50. The shift register unit 110 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 110 includes j shift registers 1101 to 110j.

The sampling latch unit 120 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register unit 110. Here, the sampling latch unit 120 includes j sampling latches 1201 to 120j to store j data. The sampling latches 1201 to 120j have a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 1201 to 120j is set to a size of k bits.

The holding latch unit 130 receives data from the sampling latch unit 120 and stores the data. The holding latch unit 130 supplies the data Data stored therein to the DAC unit 140. To this end, the holding latch unit 130 includes j holding latches 1301 to 130j set to k bits. Meanwhile, the sampling latch unit 120 and the holding latch unit 130 may be collectively referred to as a latch unit.

The DAC unit 140 receives data from the holding latch unit 130. The DAC unit 140 receiving the data Data generates a data signal having a predetermined current corresponding to the gray value (bit value) of the data Data, and supplies the generated data signal to the output stage 150.

The output stage 150 receives a current data signal from the DAC unit 140 and charges a voltage corresponding to the supplied current data signal. Each of the output stages 150 receives a current corresponding to the voltage charged therein from the pixels 40 via the data lines D1 to Dj. To this end, the output stage 150 includes a plurality of sample and hold circuits 1501 to 150j positioned for each channel.

3 is a circuit diagram illustrating an example of a sample and hold circuit. In FIG. 3, a sample and hold circuit connected to the j th data line Dj will be illustrated for convenience of description.

Referring to FIG. 3, the sample and hold circuit of the present invention includes a first switch SW1, a current source CS, a second switch SW2, and a driver 170.

The first switch SW1 is installed between the driving unit 170 and the DAC unit 140. The first switch SW1 is turned on when the data signal is supplied from the DAC unit 140 and is turned off for the rest of the period.

The second switch SW2 is provided between the driver 170 and the data line Dj. The second switch SW2 is turned on when the driver 170 sinks current from the pixel 40 via the data line Dj, and is turned off for the rest of the period. To this end, the second switch SW2 is alternately turned on and off with the first switch SW1 as shown in FIG. 4.

The current source CS supplies a predetermined current to the driver 170. The current source CS is provided for each sample and hold circuit 1501 to 150j to supply a constant current to the driver 170.

The driving unit 170 charges a predetermined voltage in response to the current supplied from the data signal and the current source CS when the first switch SW1 is turned on. When the second switch SW2 is turned on, the driver 170 sinks a predetermined current from the pixel 40 via the data line Dj in response to the voltage value charged therein.

To this end, the driving unit 170 is connected to the third switch (SW3), the fourth switch (SW4), the first capacitor (C1), the second capacitor (C2), the first transistor (M1) and the second transistor (M2). Equipped.

The first transistor M1 and the second transistor M2 are connected in series between the first switch SW1 and the ground voltage source GND. Here, the first electrode of the first transistor M1 is connected to the first switch SW1, and the second electrode is connected to the first electrode of the second transistor M2. The gate electrode of the first transistor M1 is connected to the first capacitor C1. On the other hand, the first electrode is set to an electrode different from the second electrode. For example, if the first electrode is set as the drain electrode, the second electrode is set as the source electrode.

The first electrode of the second transistor M2 is connected to the second electrode of the first transistor M1, and the second electrode is connected to the ground voltage source GND. The gate electrode of the second transistor M2 is connected to the second capacitor C2.

The third switch SW3 is connected between the first electrode and the gate electrode of the first transistor M1. The third switch SW3 is turned on and off at the same time as the first switch SW1 as shown in FIG. 4. On the other hand, when the third switch SW3 is turned on, the first transistor M1 is connected in the form of a diode.

The fourth switch SW4 is connected between the first electrode and the gate electrode of the second transistor M2. As shown in FIG. 4, the fourth switch SW4 is turned on and off at the same time as the first switch SW1. On the other hand, when the fourth switch SW4 is turned on, the second transistor M2 is connected in the form of a diode.

The first capacitor C1 is connected between the gate electrode of the first transistor M1 and the ground voltage source GND. The first capacitor C1 charges a predetermined voltage in response to the current flowing through the first transistor M1.

The second capacitor C2 is connected between the gate electrode of the second transistor M2 and the ground voltage source GND. The second capacitor C2 charges a predetermined voltage in response to the current flowing through the second transistor M2.

The operation of the sample and hold circuit 150j of the present invention will be described in detail with reference to FIGS. 3 and 4. First, the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned on in response to a control signal supplied from the outside.

When the third switch SW3 is turned on, the first transistor M1 is connected in the form of a diode, and when the fourth switch SW4 is turned on, the second transistor M2 is connected in the form of a diode. When the first switch SW1 is turned on, the driving unit 170 and the DAC unit 140 are electrically connected to each other. Then, the current data signal supplied from the DAC unit 140 is supplied to the base voltage source GND via the first transistor M1 and the second transistor M2 connected in a diode form. The current supplied from the current source CS is also supplied to the base voltage source GND via the first transistor M1 and the second transistor M2 connected in the form of a diode.

At this time, the first capacitor C1 charges a predetermined voltage corresponding to the current supplied through the first transistor M1. The second capacitor C2 charges a predetermined voltage in response to the current supplied through the second transistor M2. That is, the first capacitor C1 and the second capacitor C2 are charged with a voltage corresponding to the current data signal and the current supplied from the current source CS. Here, since the current supplied from the current source CS always maintains a constant value, the voltage value charged in the first capacitor C1 and the second capacitor C2 is determined by the current value of the data signal.

After a predetermined voltage is charged in the first capacitor C1 and the second capacitor C2, the first switch SW1, the third switch SW3, and the fourth switch SW4 are turned off, and the second switch is turned off. (SW2) is turned on. When the second switch SW2 is turned on, the data line Dj and the driver 170 are electrically connected to each other.

When the second switch SW2 is turned on and the data line Dj and the driver 170 are electrically connected to each other, the first transistor M1 corresponds to the data line charged in response to the voltage value charged in the first capacitor C1. A predetermined current is sinked from the pixel 40 via Dj. In practice, the first transistor M1 sinks a predetermined current from the pixel 40 connected to the current source CS and the data line Dj in response to the voltage charged in the first capacitor C1. Here, since the current value of the current source CS is kept constant, the current corresponding to the data signal is supplied from the pixel 40 to the first transistor M1. Similarly, the second transistor M2 also sinks a predetermined current from the pixel 40 connected to the current source CS and the data line Dj in response to the voltage value charged in the second capacitor C2. Then, the pixel 40 is charged with a predetermined voltage in response to the current supplied to the driver 170, and generates light having a predetermined brightness in response to the charged voltage.

In the sample and hold circuit of the present invention, the current of the data source CS as well as the current of the data signal is additionally supplied to the driver 170. As such, when the current of the current source CS is additionally supplied to the driving unit 170, the first capacitor C1 and the second capacitor C2 may be charged with a predetermined voltage or more, and accordingly, the first transistor M1 may be charged. And the second transistor M2 can be driven in a stable region. In other words, the voltages charged in the first capacitor C1 and the second capacitor C2 are increased so that the first transistor M1 and the second transistor M2 are driven in a stable region instead of the sub-threshold voltage region. As such, when the first transistor M1 and the second transistor M2 are driven in a stable region, the amount of current changed due to a switching error can be reduced.

In the sample and hold circuit of the present invention, the first capacitor C1 and the second capacitor C2 can be charged to a desired voltage in a short time by supplying the current of the current source CS to the driver 170. In detail, the current value of the data signal is generally set to a fine current of about ㎂. Therefore, it takes a long time to charge the first capacitor C1 and the second capacitor C2 with a voltage value corresponding to the current value of the data signal without the current of the current source CS. However, when the current of the current source CS is additionally supplied in addition to the data signal, a desired voltage can be charged in the first capacitor C1 and the second capacitor C2 in a short time.

FIG. 5 is a diagram showing a second embodiment of the data driving circuit shown in FIG. 5, the same components as those in FIG. 2 are assigned the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 5, the data driving circuit 100 according to the second exemplary embodiment of the present invention further includes a level shifter 160 installed between the holding latch 130 and the DAC 140. The level shifter unit 160 increases the voltage level of data Data supplied from the holding latch unit 130 and supplies it to the DAC unit 140. When data having a high voltage level is supplied from the external system to the data driving circuit 100, the manufacturing cost increases because circuit components corresponding to the high voltage level must be installed in the light emitting display device. Accordingly, data Data having a low voltage level is supplied from the outside of the data driving circuit 100, and the data Shift having the low voltage level is boosted by the level shifter 160 to a high voltage level. Accordingly, circuit components corresponding to low voltage levels may be installed in the light emitting display device, thereby reducing manufacturing costs.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Therefore, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the sample and hold circuit and the data driving circuit using the same, the current source is provided in the sample and hold circuit and the voltage corresponding to the current source and the current data signal is charged to the driving unit. The amount of change in current due to switching error can be minimized. In the present invention, a desired voltage can be charged in the driving unit in a short time, and thus an image having a desired luminance can be displayed on the light emitting display device.

Claims (9)

A first switch connected between the digital-analog converter and the driver, A second switch connected between the data line and the driving unit; A current source for supplying current to the drive unit; And a driver for charging a predetermined voltage in correspondence with the current data signal supplied from the digital-analog converter and the current supplied from the current source. The method of claim 1, And the first switch and the second switch are alternately turned on and off. The method of claim 2, The driving unit A first transistor and a second transistor connected in series between the first switch and a base voltage source; A third switch connected between the first electrode and the gate electrode of the first transistor such that the first transistor is connected in the form of a diode; A fourth switch connected between the first electrode and the gate electrode of the second transistor so that the second transistor is connected in the form of a diode; A first capacitor connected between the gate electrode of the first transistor and the base voltage source; And a second capacitor connected between the gate electrode of the second transistor and the base voltage source. The method of claim 3, wherein And the third switch and the fourth switch are turned on and off at the same time as the first switch. The method of claim 4, wherein The first capacitor charges a voltage corresponding to the current supplied from the data signal and the current source to the first transistor when the first switch is turned on, and the second capacitor is configured to turn on the first switch. And a sample and hold circuit for charging a voltage corresponding to the data signal and the current supplied from the current source to the second transistor. The method of claim 4, wherein And a first transistor and a second transistor configured to receive a current corresponding to a voltage charged in the first capacitor and the second capacitor from a pixel connected with the data line when the second switch is turned on. A digital-analog converter for generating a current data signal corresponding to a bit value of data supplied from the outside; A data driving circuit comprising an output stage comprising a plurality of the sample and hold circuits according to any one of claims 1 to 6. The method of claim 7, wherein The data driving circuit A shift register section for sequentially generating sampling signals; And a latch unit for storing the data in response to the sampling signal and for supplying the stored data to the digital-analog converter. The method of claim 8, And a level shifter unit for raising a voltage level of data stored in the latch unit to supply the digital-analog converter.

Images