KR100595102B1 - Data Integrated Circuit and Light Emitting Display Using the Same - Google Patents

Abstract

The present invention relates to a data integrated circuit capable of supplying an accurate output voltage by compensating a threshold voltage.

Each of the buffers included in the data integrated circuit of the present invention includes a first capacitor, a second capacitor, a voltage source, a second terminal connected to the voltage source, a first terminal connected to the data line, and a gate terminal connected to the first capacitor and the first capacitor. A first transistor connected to one side of the second capacitor, a first switching unit for charging the first capacitor with a voltage corresponding to the threshold voltage of the first transistor, and a second capacitor corresponding to the threshold voltage of the first transistor. A data integrated circuit having a second switching unit for charging a voltage is provided.

With this arrangement, in the present invention, the data signal supplied from the outside can be transmitted to the data line without voltage drop, and thus the image display unit can display an image having a desired luminance.

Description

Data integrated circuit and light emitting display device using the same             

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating in detail the data integrated circuit shown in FIG. 1.

3 is a circuit diagram illustrating in detail the buffer illustrated in FIG. 2.

4 is a waveform diagram illustrating a first embodiment of a driving waveform supplied to the buffer shown in FIG. 3.

FIG. 5 is a waveform diagram illustrating a second embodiment of a driving waveform supplied to the buffer shown in FIG. 3.

<Explanation of symbols for the main parts of the drawings>

110: scan driver 120: data driver

121: shift register section 122: sampling latch section

123: holding latch portion 124: level shifter portion

125: DAC unit 126: buffer unit

127: buffer 127a, 127b: circuit portion

129: data integrated circuit 130: image display unit

140: pixel 150: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data integrated circuit and a light emitting display device using the same, and more particularly, to a data integrated circuit and a light emitting display device using the same to compensate for a threshold voltage so as to supply an accurate output voltage.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device uses a driving thin film transistor (TFT) formed for each pixel to supply light corresponding to a data signal to the light emitting device to emit light from the light emitting device.

Such a light emitting display generates a data signal using data supplied from the outside, and displays the image having a desired brightness by supplying the generated data signal to the pixels via the data lines. Here, at least one data integrated circuit is used to convert data supplied from the outside into a data signal.

The data integrated circuit converts data supplied from the outside into a data signal corresponding to the gray scale value, and supplies the converted data signal to the data lines via buffers. The buffers are composed of a plurality of transistors to supply a data signal supplied thereto to the data lines.

However, in the conventional buffers, a voltage drop is generated by a voltage corresponding to the threshold voltage of the transistor when the data signal is supplied to the data lines. In other words, in the conventional buffer, the voltage of the data signal drops by the threshold voltage of the transistor, thereby causing a problem in that an image of a desired luminance cannot be displayed.

Accordingly, an object of the present invention is to provide a data integrated circuit and a light emitting display device using the same, capable of supplying an accurate output voltage by compensating a threshold voltage.

In order to achieve the above object, a first aspect of the present invention provides a data integrated circuit having a plurality of buffers for transferring a data signal supplied from a digital-to-analog converter to a data line, wherein each of the buffers includes a plurality of buffers. A first capacitor having a first capacitor, a second capacitor and a voltage source, a second terminal connected to the voltage source, a first terminal connected to the data line, and a gate terminal connected to one side of the first capacitor and the second capacitor; A first switching unit for charging the first capacitor to a voltage corresponding to the threshold voltage of the first transistor, and a second switching unit for charging the second capacitor to a voltage corresponding to the threshold voltage of the first transistor It provides a data integrated circuit provided.

Preferably, the first switching unit is disposed between one side of the first capacitor and the digital-analog converter and is driven by a first control signal, and between the other side of the first capacitor and the data line. And a third transistor installed and driven by the first control signal. The second switching unit includes a fourth transistor provided between the other side of the second capacitor and the data line and driven by the first control signal and the second control signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5 that can be easily implemented by those skilled in the art.

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes an image display unit 130 including pixels 140 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm. And the scan driver 110 for driving the scan lines S1 to Sn, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. A timing controller 150 for controlling is provided.

The scan driver 110 generates a scan signal in response to the scan drive control signal SCS from the timing controller 150, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 110 generates a light emission control signal in response to the scan drive control signals SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En.

The data driver 120 generates data signals in response to the data driving control signal DCS from the timing controller 150, and supplies the generated data signals to the data lines D1 to Dm. To this end, the data driver 120 includes at least one data integrated circuit 129. The data integrated circuit 129 converts data supplied from the outside into a data signal and supplies the data to the data lines D1 to Dm. The detailed configuration of the data integrated circuit 129 will be described later.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 rearranges the data Data supplied from the outside and supplies the data to the data driver 120.

The image display unit 130 receives the first power source VDD and the second power source VSS from the outside. The first power source VDD and the second power source VSS supplied to the image display unit 130 are supplied to the respective pixels 140. The pixels 140 supplied with the first power source VDD and the second power source VSS display an image corresponding to the data signal supplied from the data integrated circuit 129.

FIG. 2 is a block diagram illustrating in detail the data integrated circuit shown in FIG. 1. Here, it is assumed that the data integrated circuit is composed of i channels so that i (i is a natural number) data lines can be connected.

Referring to FIG. 2, the data integrated circuit 129 according to an exemplary embodiment of the present invention stores a shift register 121 for sequentially generating sampling signals and sequentially stores data in response to the sampling signals. The sampling latch unit 122 for holding, the holding latch unit 123 for temporarily storing data Data stored in the sampling latch unit 122 and supplying the stored data to the level shifter 124, and data A level shifter unit 124 for raising the voltage level of Data and a digital-analog converter (hereinafter, referred to as a "DAC unit") for generating a data signal corresponding to the grayscale value of the data ( 125, and a buffer unit 126 for temporarily storing and outputting data signals.

The shift register unit 121 receives the source shift clock SSC and the source start pulse SSP from the timing controller 150. The shift register unit 121 supplied with the source shift clock SSC and the source start pulse SSP sequentially generates i sampling signals while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 121 includes i shift registers.

The sampling latch unit 122 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 121. Here, the sampling latch unit 122 includes i sampling latches for storing i data. Each of the sampling latches has a size corresponding to the number of bits of data. For example, when the data are k bits, each of the sampling latches is set to a size of k bits.

The holding latch unit 123 receives data from the sampling latch unit 122 and stores the data when the source output enable signal SOE is input from the timing controller 150. The holding latch unit 123 supplies the data Data stored therein to the level shifter unit 124 when the source output enable signal SOE is input. To this end, the holding latch unit 123 includes i holding latches identical to the sampling latch unit 122. The size of the holding latch (the number of bits that can be stored) is set to k bits in the same manner as the sampling latch.

The level sheeter unit 124 increases the voltage level of the data Data supplied from the holding latch unit 123 and supplies it to the DAC unit 125. Substantially, supplying data having a high voltage level from the external system to the data integrated circuit 129 increases manufacturing costs because circuit components corresponding to the voltage level need to be installed. Therefore, data Data having a low voltage level is supplied from the outside of the integrated circuit 129, and the data Sheet having the low voltage level is boosted by the level sheeter 124 to a high voltage level.

The DAC unit 125 generates a data signal corresponding to a bit value (that is, a gray scale value) of the data Data, and supplies the generated data signal to the buffer unit 126. In fact, the DAC unit 125 generates a gray voltage corresponding to the gray value of the data, and supplies the generated gray voltage to the buffer unit 126 as a data signal.

The buffer unit 126 temporarily stores the data signals supplied from the DAC unit 125 and supplies them to i data lines D1 to Di. For this purpose, the buffer unit 126 includes i buffers 127. Each of the i buffers 127 supplies a data signal supplied thereto to the data lines D1 intrinsic Di. Here, the buffers 127 supply a data signal without a voltage drop to the data lines D1 to Di, regardless of the threshold voltage of the transistor included therein.

3 is a circuit diagram illustrating in detail the buffer illustrated in FIG. 2. 4 is a waveform diagram illustrating a method of driving the buffer shown in FIG. 3.

3 and 4, each of the buffers 127 of the present invention is positioned between the DAC unit 125 and the data line D. FIG. The buffers 127 may include a first transistor M1 installed between the first capacitor C1 and the second capacitor C2, and the voltage source Vcc, the first node N1, and the third node N3. ), The first switching unit 127a for charging the voltage corresponding to the threshold voltage of the first transistor M1 to the first capacitor C1, and the first capacitor M1 to the second capacitor C2. The second switching unit 127b for charging a voltage corresponding to the threshold voltage, the fifth transistor M5 provided between the DAC unit 125 and the second node N2, the fourth node N4, The sixth transistor M6 is disposed between the DAC units 125 and the seventh transistor M7 is disposed between the third node N3 and the base voltage source GND.

The first switching unit 127a includes a second transistor M2 and a third transistor M3. The second transistor M2 is provided between the DAC unit 125 and one side (first node N1) of the first capacitor C1. The second transistor M2 is turned on when the first control signal S1 is supplied from the outside. The third transistor M3 is provided between the other side of the first capacitor C1 (second node N2) and the data line D (third node N3). The third transistor M3 is turned on when the first control signal S1 is supplied.

The fifth transistor M5 is installed between the DAC unit 125 and the second node N2. The fifth transistor M5 is turned on when the second control signal S2 is supplied.

The first transistor M1 is provided between the first node N1 and the voltage source Vcc. The first transistor M1 is provided to be electrically connected to the third node N3. In other words, the second terminal of the first transistor M1 is connected to the voltage source Vcc, and the first terminal is connected to the third node N3. The gate terminal of the first transistor M1 is connected to the first node N1. Here, the first terminal is set to any one of the source terminal and the drain terminal, and the second terminal is set to a different terminal from the first terminal. For example, when the first terminal is selected as the source terminal, the second terminal is selected as the drain terminal. The first transistor M1 is turned on or turned off by a voltage applied to the first node N1.

The second switching unit 127b includes a fourth transistor M4. The fourth transistor M4 is installed between the third node N3 and the fourth node N4. The fourth transistor M4 is turned on when the first control signal S1 and the second control signal S2 are supplied.

The sixth transistor M6 is installed between the fourth node N4 and the DAC unit 125. The sixth transistor M6 is turned on when the third control signal S3 is supplied.

The seventh transistor M7 is provided between the third node N3 and the base voltage source GND. The seventh transistor M7 is weakly turned on by the bias voltage S4 supplied from the outside.

The first capacitor C1 is installed between the first node N1 and the second node N2. The first capacitor C1 charges a predetermined voltage in response to voltage values applied to the first node N1 and the second node N2, and supplies the charged voltage to the first transistor M1. .

The second capacitor C2 is installed between the first node N1 and the fourth node N4. The second capacitor C2 charges a predetermined voltage in response to voltage values applied to the first node N1 and the fourth node N4, and supplies the charged voltage to the first transistor M1. .

The operation of the buffer 127 will be described in detail with reference to FIG. 4. Here, the first control signal S1 to the third control signal S3 are sequentially supplied, and the bias voltage S4 is continuously supplied. First, the first control signal S1 is supplied from the outside, and the predetermined voltage Vdc is supplied from the DAC unit 125. Here, the voltage value of the first control signal S1 is set to a voltage value higher than the voltage value of the predetermined voltage Vdc.

When the first control signal S1 is supplied, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on. In addition, the seventh transistor M7 receives a bias voltage to maintain a weakly turned on state. When the second transistor M2 is turned on, a voltage of the predetermined voltage Vdc is applied to the first node N1. Then, the first transistor M1 is turned on by the voltage value applied to the first node N1. When the first transistor M1 is turned on, the voltage value of the first terminal of the first transistor M1 (that is, the third node N3) gradually increases. The voltage value of the first terminal is determined to be a voltage lower than the predetermined voltage Vdc by the threshold voltage of the first transistor M1 at a time when the current flowing through the first terminal becomes '0' (ie, Vdc-Vth). Here, since the seventh transistor M7 is turned on in a week, the current flowing to the first terminal of the first transistor M1 may be set to '0' in a short time, thereby shortening the driving time.

The voltage applied to the third node N3 is applied to the second node N2 via the third transistor M3. The voltage applied to the third node N3 is applied to the fourth node N4 via the fourth transistor M4. Here, a predetermined voltage Vdc is applied to the first node N1, and a voltage lower than the threshold voltage of the first transistor M1 at a predetermined voltage Vdc is applied to the second node N2 and the fourth node N4. Is applied. Therefore, each of the first capacitor C1 and the second capacitor C2 is charged with a voltage corresponding to the threshold voltage of the first transistor M1.

Thereafter, the second control signal S2 is supplied from the outside, and the gray voltage Vga (data signal) corresponding to the gray value is supplied from the DAC unit 125. Here, the voltage value of the second control signal S2 is set to a voltage value higher than the voltage value of the gray voltage Vga.

When the second control signal S2 is supplied, the fourth transistor M4 and the fifth transistor M5 are turned on. When the fifth transistor M5 is turned on, the gray voltage Vga is supplied to the second node N2. When the gray voltage Vga is supplied to the second node N2, the voltage of the first node N1 is also increased by the gray voltage Vga by the first capacitor C1. At this time, since the voltage corresponding to the threshold voltage of the first transistor M1 is charged in the first capacitor C1, the threshold voltage of the first transistor M1 is applied to the gradation voltage vga in the first node N1. The combined voltage value is applied.

The voltage value applied to the first node N1 is supplied to the gate terminal of the first transistor M1, thereby turning on the first transistor M1. When the first transistor M1 is turned on, the voltage value of the third node N3 gradually increases. When the current flowing in the third node N3 becomes '0', the third node N3 has the gray voltage Vga lower than the threshold voltage of the first transistor M1 by the threshold voltage of the first transistor M1. Is approved. At this time, since the seventh transistor M7 maintains the weekly turn-on state, that is, since the current of the third node N3 is supplied to the base voltage source GND via the seventh transistor M7, the third node. The voltage value of N3 rises to the gray scale voltage Vga in a short time. Thereafter, the gray voltage Vga applied to the third node N3 is supplied to the data line D. The gray voltage Vga (data signal) supplied to the data line D is supplied to the pixel 140, and accordingly, light corresponding to the gray voltage Vga is generated in the pixel 140.

On the other hand, since the fourth transistor M4 is turned on, the gray voltage Vga is supplied to the fourth node N4. In this case, since the first node N1 has a voltage value obtained by adding the gray voltage Vga and the threshold voltage of the first transistor M1, and the fourth node N4 has a gray voltage Vga, the second capacitor C2) maintains the threshold voltage of the first transistor M1.

Thereafter, the third control signal S2 is supplied from the outside, and the gray scale voltage Vga (data signal) corresponding to the gray scale value is supplied from the DAC unit 125. Here, the voltage value of the third control signal S3 is set to a voltage value higher than the voltage value of the gradation voltage Vga.

When the third control signal S3 is supplied, the sixth transistor M6 is turned on. When the sixth transistor M6 is turned on, the gray voltage Vga is supplied to the fourth node N4. When the gray voltage Vga is supplied to the fourth node N4, the voltage of the first node N1 is also increased by the gray voltage Vga by the second capacitor C2. At this time, since the voltage corresponding to the threshold voltage of the first transistor M1 is charged in the second capacitor C2, the threshold voltage of the first transistor M1 is applied to the gray level voltage Vga in the first node N1. The combined voltage value is applied.

The voltage value applied to the first node N1 is supplied to the gate terminal of the first transistor M1, thereby turning on the first transistor M1. When the first transistor M1 is turned on, the voltage value of the third node N3 gradually increases. When the current flowing in the third node N3 becomes '0', the third node N3 has the gray voltage Vga lower than the threshold voltage of the first transistor M1 by the threshold voltage of the first transistor M1. Is approved. At this time, since the seventh transistor M7 maintains the weekly turn-on state, that is, since the current of the third node N3 is supplied to the base voltage source GND via the seventh transistor M7, the third node. The voltage value of N3 rises to the gray scale voltage Vga in a short time. The gray voltage Vga applied to the third node N3 is supplied to the data line D. The gray voltage Vga (data signal) supplied to the data line D is supplied to the pixel 140, and accordingly, predetermined light corresponding to the gray voltage Vga is generated in the pixel 140.

In fact, the buffer 127 of the present invention supplies the gray scale voltage Vga (data signal) to the data line D while repeating the above-described process. In this case, the buffer 127 of the present invention can supply the grayscale voltage Vga supplied from the DAC unit 125 to the data line D without a voltage drop, thereby displaying an image having a desired luminance. Further, in the present invention, since the gray voltage Vga is supplied while the first capacitor C1 and the second capacitor C2 are alternately driven, the gray voltage Vga can be stably supplied. In addition, the buffer of the present invention may be employed in a liquid crystal display device driven in an inversion manner to alternately supply the positive and negative gradation voltages Vga to the data line D.

On the other hand, in the buffer 127 of the present invention, the seventh transistor M7 is always maintained in the weekly turn-on state by the bias voltage S4 supplied from the outside. However, if the seventh transistor M7 maintains the weekly turn-on state as described above, high power consumption may be consumed. Accordingly, in the present invention, as shown in FIG. 5, the seventh transistor is provided only when the first control signal S1, the second control signal S2, and the third control signal S3 are supplied to the gate terminal of the seventh transistor M7. The fourth control signal S4 may be supplied so that the M7 may be turned on, and the fourth control signal S4 may not be supplied so that the seventh transistor M4 may be turned off. have. Then, power consumption wasted by the seventh transistor M7 can be minimized.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the data integrated circuit and the light emitting display device using the same, the gray scale voltage supplied from the DAC unit can be transferred from the buffer unit to the data line without a voltage drop. As such, if the gray level voltage is not lost in the buffer unit, the image display unit may display an image having a desired luminance.

Claims (8)

A data integrated circuit comprising a plurality of buffers for transferring a data signal supplied from a digital-analog converter to a data line; Each of the buffers A first capacitor, a second capacitor and a voltage source; A first transistor having a second terminal connected to the voltage source, a first terminal connected to the data line, and a gate terminal connected to one side of the first capacitor and the second capacitor; A first switching unit for charging a voltage corresponding to the threshold voltage of the first transistor to the first capacitor; And a second switching unit configured to charge the second capacitor with a voltage corresponding to the threshold voltage of the first transistor. The method of claim 1, The first switching unit A second transistor disposed between one side of the first capacitor and the digital-analog converter and driven by a first control signal; And a third transistor disposed between the other side of the first capacitor and the data line and driven by the first control signal. The method of claim 2, The second switching unit And a fourth transistor provided between the other side of the second capacitor and the data line and driven by the first control signal and the second control signal. The method of claim 3, wherein A fifth transistor disposed between the other side of the first capacitor and the digital-analog converter and driven by the second control signal; And a sixth transistor disposed between the other side of the second capacitor and the digital-analog converter and driven by a third control signal. The method of claim 4, wherein And the first control signal, the second control signal, and the third control signal are sequentially supplied. The method of claim 4, wherein And a seventh transistor disposed between the data line and the base voltage source, the seventh transistor being turned on during a period in which the first to third control signals are supplied. The method of claim 5, And the digital-analog converter supplies a predetermined voltage during a period during which the first control signal is supplied, and supplies the data signal during a period during which the second control signal and the third control signal are supplied. A light emitting display device comprising the data integrated circuit according to any one of claims 1 to 7.

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