KR100629581B1 - Data integrated circuit and light emitting display using the same - Google Patents

Abstract

The present invention relates to a data integrated circuit capable of driving with a current of the present invention.

A data integrated circuit of the present invention includes a first holding latch unit for storing data supplied from the outside; A second holding latch unit for receiving and storing the data from the first holding latch unit; A first digital-analog converter for sequentially receiving some data stored in the first holding latch unit to generate a first data signal as a current; A second digital-to-analog converter for sequentially receiving some data stored in the second holding latch unit to generate a second data signal as a current; A third digital-analog converter for sequentially receiving all data stored in the second holding latch unit to generate a third data signal as a current; And an output stage including a plurality of current sinks which are first charged when the first data signal or the second data signal is supplied, and which are finally charged when the third data signal is supplied.

Description

Data integrated circuit and light emitting display using the same

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 1.

3 is a diagram illustrating an output stage illustrated in FIG. 2.

FIG. 4 is a circuit diagram illustrating an example of the sample / hold circuit shown in FIG. 3.

FIG. 5 is a diagram illustrating a second embodiment of the data integrated circuit shown in FIG. 1.

FIG. 6 is a diagram illustrating a third embodiment of the data integrated circuit shown in FIG. 1.

FIG. 7 is a diagram illustrating a fourth embodiment of the data integrated circuit shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

10: scan driver 20: data driver

30 pixel portion 40 pixel

50: timing controller 100: data integrated circuit

110,210: shift register 120,220: sampling latch

130, 131, 230, 231: holding latch unit 140, 260, 270, 280: current generating unit

134,150,234,235,236,242,244,246: switching part

142,144,146,262,264,266,272,274,276,282,284,286: DAC

160,250: output stage 170,290: reference current portion

The present invention relates to a data integrated circuit and a light emitting display using the same, and more particularly, to a data integrated circuit and a light emitting display using the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel displays, a light emitting display displays an image using a light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

The light emitting display device includes a plurality of pixels positioned at an intersection of the data lines and the scan lines. The pixels are selected when the scan signal is supplied to the scan line and charge a voltage corresponding to a predetermined voltage (data signal) supplied with data. The pixels generate light having a predetermined luminance by supplying a current corresponding to the charged voltage to the light emitting device. In this case, light of predetermined luminance emitted from each of the pixels is combined to display a predetermined image in the recovery unit.

However, the conventional pixels include a plurality of transistors, and there is a problem in that a desired image is not displayed due to variations in threshold voltages and electron mobility of the transistors. In order to overcome this problem, a method of supplying a current as a data signal has been proposed. In fact, when a current is supplied as a data signal, there is an advantage that a uniform image can be displayed regardless of threshold voltage unevenness and variation in electron mobility of transistors. Therefore, there is a demand for a data integrated circuit capable of supplying current as a data signal.

Accordingly, an object of the present invention is to provide a data integrated circuit and a light emitting display device using the same, which can be driven by a current.

In order to achieve the above object, the first aspect of the present invention includes a first holding latch unit for storing data supplied from the outside; A second holding latch unit for receiving and storing the data from the first holding latch unit; A first digital-analog converter for sequentially receiving some data stored in the first holding latch unit to generate a first data signal as a current; A second digital-to-analog converter for sequentially receiving some data stored in the second holding latch unit to generate a second data signal as a current; A third digital-analog converter for sequentially receiving all data stored in the second holding latch unit to generate a third data signal as a current; Provided is a data integrated circuit having an output stage including a plurality of current sinks which are first charged upon receiving the first data signal or the second data signal and finally charged upon receiving the third data signal.

Preferably, the data supplied from the first holding latch unit to the first digital-analog converter is different from the data supplied from the second holding latch unit to the second digital-analog converter. Some current sinks included in the output stage are primarily charged by a first data signal, and remaining current sinks included in the output stage are primarily charged by a second data signal. All current sinks included in the output stage are finally charged by the third data signal, and receive a current corresponding to the charged voltage from the pixel via the data line.

The second aspect of the present invention includes a first holding latch unit for storing data supplied from the outside; A second holding latch unit for receiving and storing the data from the first holding latch unit; A first current generator configured to control charging voltages of the first current sink units connected to the red pixel by using red data stored in the first holding latch unit and the second holding latch unit; A second current generator configured to control charging voltages of second current sink units connected to the green pixel by using green data stored in the first holding latch unit and the second holding latch unit; A third current generator configured to control charging voltages of third current sink units connected to the blue pixel by using blue data stored in the first holding latch unit and the second holding latch unit; A data integrated circuit having an output stage including the first current sinks, the second current sinks, and the third current sinks is provided.

Preferably, each of the first current generation unit, the second current generation unit, and the third current generation unit is supplied with the red data, the green data, or the blue data of the part stored in the first holding latch unit, and is the first data as the current. A first digital-analog converter for generating a signal; A second digital-analog converter configured to receive the partial red data, green data or blue data stored in the second holding latch unit to generate a second data signal as a current; And a third digital-analog converter configured to receive all red data, green data, or blue data stored in the second holding latch unit to generate a third data signal as a current. Data supplied from the first holding latch unit to the first digital-to-analog converter is different from data supplied from the second holding latch unit to the second digital-to-analog converter. Some of the first current sinks, the second current sinks, and the third current sinks are first charged when the first data signal is supplied, and the first current when the second data signal is supplied. The remaining ones of the sinks, the second current sinks and the third current sinks are first charged. When the third data signal is supplied, the first current sinks, the second current sinks, and the third current sinks are finally charged.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 7 to which a person skilled in the art may easily implement the present invention.

1 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a light emitting display device according to an exemplary embodiment of the present invention includes a pixel unit 30 including a plurality of pixels 40 connected to scan lines S1 to Sn and data lines D1 to Dm. And a scan driver 10 for driving the scan lines S1 to Sn, a data driver 20 for driving the data lines D1 to Dm, a scan driver 10 and a data driver 20 The timing control part 50 for controlling is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 which receives the scan driving control signal SCS sequentially supplies the scan signal to the scan lines S1 to Sn. That is, the scan driver 10 selects the pixels 40 to which the data signal is supplied while sequentially supplying the scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 supplied with the data driving control signal DCS receives a predetermined current (data signal) corresponding to the data from the pixel 40 selected by the scan signal. That is, the data driver 20 of the present invention is configured as a current sink type that receives a current from the pixel 40. To this end, the data driver 20 includes at least one data integrated circuit 100. The detailed configuration of the data integrated circuit 100 will be described later.

The pixel portion 30 includes pixels 40 formed at intersections of the scan lines S1 to Sn and the data lines D1 to Dm. Each of the pixels 40 receives a first power source ELVDD and a second power source ELVSS. The pixels 40 charge a predetermined voltage in response to the current sinked in the data driver 20, and the light emitting device (not shown) is supplied from the first power source ELVDD to a current corresponding to the charged voltage. The image having a predetermined brightness is displayed by supplying it to the second power supply ELVSS via the display. Here, the pixels 40 may include a red pixel having a red light emitting device (not shown) to emit red light, a green pixel having a green light emitting device (not shown) to emit green light, and a blue light. In order to emit light, it is divided into a blue pixel having a blue light emitting element (not shown).

FIG. 2 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 1. In FIG. 2, it is assumed that the data integrated circuit 100 has j channels where j is a natural number of two or more.

Referring to FIG. 2, the data integrated circuit 100 according to the first exemplary embodiment of the present invention may include a shift register unit 110, a sampling latch unit 120, a first holding latch unit 130, and a second holding latch unit. 131, a first switching unit 134, a current generating unit 140, a second switching unit 150, and an output stage 160.

The shift register unit 110 receives a source shift clock SSC and a source start pulse SSP from the timing controller 50. The shift register unit 110 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 110 includes j shift registers 1101 to 110j.

The sampling latch unit 120 sequentially stores data in response to sampling signals sequentially supplied from the shift register unit 110. Here, the sampling latch unit 120 includes j sampling latches 1201 to 120j to store j data.

The first holding latch unit 130 receives data from the sampling latch unit 120 and stores the data. The first holding latch unit 130 supplies data stored therein to the second holding latch unit 131 and the first switching unit 134. To this end, the first holding latch unit 130 includes j first holding latches 1301 to 130j.

The second holding latch unit 131 receives and stores data from the first holding latch unit 130. The second holding latch unit 131 supplies the data Data stored therein to the first switching unit 134. To this end, the second holding latch unit 131 includes j second holding latches 1311 to 131j.

The first switching unit 134 controls the connection between the first holding latch unit 130, the second holding latch unit 131, and the current generating unit 140. In practice, the first switching unit 134 may convert some of the first holding latches included in the first holding latch unit 130 into a first digital-to-analog converter (DAC) 142. Connect with. The first switching unit 134 connects some of the second holding latches included in the second holding latch unit 131 with the second DAC 144.

For example, the first switching unit 134 sequentially moves the first first holding latch 1301 to the sixth first holding latch (not shown) included in the first holding latch unit 130 to the first DAC 142. Connect with. In addition, the first switching unit 134 sequentially moves the seventh second holding latch (not shown) included in the second holding latch unit 131 to the j-th second holding latch 131j with the second DAC 144. Connect. In this case, the data supplied to the first DAC 142 and the data supplied to the second DAC 144 via the first switching unit 134 are set to different data. On the other hand, the first switching unit 134 sequentially connects the first second holding latch 1311 to the j-th second holding latch 131j with the third DAC 146.

The current generator 140 includes a first DAC 142, a second DAC 144, and a third DAC 146. The first DAC 142 receives data sequentially from the first holding latch unit 130 via the first switching unit 134. The first DAC 142 receiving the data generates a first data signal as a current and supplies the generated first data signal to the second switching unit 150.

The second DAC 144 sequentially receives data from the second holding latch unit 131 via the first switching unit 134. The second DAC 144 receiving the data generates a second data signal that is a current and supplies the generated second data signal to the second switching unit 150.

The third DAC 146 sequentially receives data from the second holding latch unit 131 via the first switching unit 134. The third DAC 146 receiving the data generates a third data signal that is a current and supplies the generated third data signal to the second switching unit 150.

The second switching unit 150 controls the connection between the current generator 140 and the output stage 160. Here, the second switching unit 150 connects some of the current sinks 1601 to 160j included in the output stage 160 to the first DAC 142 and the remaining current sinks to the second DAC 144. Connect with. For example, the second switching unit 150 sequentially connects the first current sinks 1601 to the sixth current sinks (not shown) to the first DAC 142, and the seventh current sinks (not shown). ) To the j th current sink 160j with the second DAC 144. In addition, the second switching unit 150 sequentially connects all the current sinks 1601 to 160j with the third DAC 146.

The output stage 160 includes j current sinks 1601 to 160j positioned for each channel. Here, each of the current sinks 1601 to 160j is connected to any one of the data lines D1 to Dj to receive a predetermined current from the pixel 40. In detail, each of the current sinks 1601 to 160j first charges a voltage by a first data signal or a second data signal, and finally charges a predetermined voltage by a third data signal. The current sinks 1601 to 160j charged with a predetermined voltage receive a predetermined current from the pixels 40 in response to the charged voltage. (Current Sink) Then, each of the pixels 40 may be a current sink. The voltage is charged in response to the current supplied to the 1601 to 160j, and light having a predetermined brightness is generated by supplying a current corresponding to the charged voltage to the light emitting device.

3 is a diagram illustrating the output stage 160 illustrated in FIG. 2. In FIG. 3, for convenience of description, the first current sinks 1601 to 6th current sinks 1606 are connected to the first DAC 142, and the seventh current sinks 1607 to jth current sinks ( Assume that 160j is connected to the second DAC 144.

Referring to FIG. 3, each of the current sinks 1601 to 160j includes at least two sample / hold circuits 162 to 166. Here, the current sinks 1601 to 1606 that receive the first data signal from the first DAC 142 include three sample / hold circuits 162, 163, and 164, and receive the second data signal from the second DAC 144. Current sinks 1607-160j have two sample / hold circuits 165, 166. Each of the sample / hold circuits 162 to 166 charges a predetermined voltage in response to a current supplied thereto, and receives a current corresponding to the charged voltage from the pixel 40.

4 is a diagram illustrating an example of a sample / hold circuit. In FIG. 4, the first sample / hold circuit 165 included in the j th current sink 160j will be illustrated for convenience of description.

Referring to FIG. 4, the sample / hold circuit 165 includes a first switch SW1, a second switch SW2, and a driver 1621.

The first switch SW1 is installed between the driving unit 1621 and the second switching unit 150. The first switch SW1 is turned on when the second data signal or the third data signal is supplied via the second switching unit 150.

The second switch SW2 is provided between the data line Dj and the driver 1621. The second switch SW2 is turned on when the driver 1621 receives a current from the pixel 40 via the data line Dj.

The driving unit 1621 includes a third switch SW3, a fourth switch SW4, a first capacitor C1, a second capacitor C2, a first transistor M1, and a second transistor M2.

The third switch SW3 and the fourth switch SW4 are turned on and off at the same time as the first switch SW1. When the third switch SW3 and the fourth switch SW4 are turned on, the first transistor M1 and the second transistor M2 are connected in the form of a diode. Therefore, the second data signal or the third data signal, which is a predetermined current supplied through the first switch SW1, is supplied to the base voltage source GND via the first transistor M1 and the second transistor M2. do. Then, the first capacitor C1 and the second capacitor C2 are charged with a voltage corresponding to the second data signal or the third data signal.

In fact, the first capacitor C1 and the second capacitor C2 are first charged when the second data signal is supplied and finally charged when the third data signal is supplied. When the voltage is finally charged in the first capacitor C1 and the second capacitor C2, the second switch SW2 is turned on. Then, a current corresponding to the voltage charged in the first capacitor C1 and the second capacitor C2 is supplied from the pixel 40 to the base voltage source GND via the data line Dj.

2 to 4, the operation of the data integrated circuit 100 according to an exemplary embodiment of the present invention will be described in detail. First, a sampling latch unit corresponding to sampling signals sequentially supplied from the shift register unit 110 may be used. 120 are stored. The data stored in the sampling latch unit 120 is supplied to the first holding latch unit 130.

Thereafter, the data stored in the first holding latch unit 130 is supplied to the second holding latch unit 131. In this case, the first switching unit 134 sequentially stores some data stored in the first holding latch unit 130, for example, data stored in the first first holding latch 1301 to the sixth first holding latch. 142). Then, the first DAC 142 generates a first data signal having a predetermined current by using the data supplied to the first DAC 142 and supplies the generated first data signal to the second switching unit 150.

The second switching unit 150 receiving the first data signal sequentially supplies the first data signal to the first current sinks 1601 to the sixth current sinks. Then, a predetermined voltage is precharged to the first sample / hold circuit 162 included in each of the first current sinks 1601 to 6th current sinks.

Meanwhile, after data is stored in the second holding latch unit 131, the first switching unit 134 may store some data stored in the second holding latch unit 131, for example, the seventh second holding latch to the jth second. The data stored in the holding latch 131j is sequentially supplied to the second DAC 144. The first switching unit 134 sequentially stores all data stored in the second holding latch unit 131, that is, data stored in the first second holding latch 1311 to the j-th second holding latch 131j. To (146).

The second DAC 144 sequentially receiving some data stored in the second holding latch unit 131 generates a second data signal and supplies the generated second data signal to the second switching unit 150. The third DAC 146 sequentially receiving all data stored in the second holding latch unit 131 generates a third data signal and supplies the generated third data signal to the second switching unit 150. .

The second switching unit 150 supplied with the second data signal sequentially supplies the second data signal to the seventh current sink to the jth current sink 160j. Then, a predetermined voltage is precharged in the first sample / hold circuit 165 included in each of the seventh current sink to the jth current sink 160j. The second switching unit 150 supplied with the third data signal sequentially supplies the third data signal to the first current sink to the j th current sink 160j. Then, the first sample / hold circuits 162 and 165 precharged by the first data signal or the second data signal are finally charged. At this time, since the first sample / hold circuits 162 and 165 are precharged, a desired voltage is charged in a short time when the third data signal is supplied.

Meanwhile, during the period in which the first sample / hold circuits 162 and 165 are charged by the third data signal, the first DAC 142 may store data stored in the first holding latch unit 130 different from the previously supplied data. Data) to generate a first data signal, and supply the generated first data signal to the second sample / hold circuit 163 included in each of the first current sinks 1601 to 6th current sinks. . Then, the second sample / hold circuit 163 included in each of the first current sinks 1601 to 6th current sinks is precharged.

Thereafter, the second sample / hold circuit 166 included in each of the seventh current sink to the jth current sink 160j is precharged by the second data signal supplied from the second DAC 144 during the next horizontal period. do. In addition, the second sample / hold circuits 163 and 164 included in each of the first current sinks 1601 to j-th current sinks 160j are finally formed by the third data signal supplied from the third DAC 166. Is charged.

Meanwhile, each of the first sample / hold circuits 162 and 165 included in each of the first current sink 1601 to the j th current sink 160j during the next horizontal period corresponds to the voltage charged in the previous horizontal period. A predetermined current is supplied from the pixel 40. During the next horizontal period, the third sample / hold circuit 164 included in each of the first current sinks 1601 through the sixth current sinks is precharged by the first DAC 142. In practice, the data integrated circuit 100 of the present invention is driven while repeating the above-described process.

As described above, in the present invention, each of the sample / hold circuits 162 to 166 is first charged by the first data signal or the second data signal and finally charged by the third data signal. Accordingly, the 3DAC 146 may charge the sample / hold circuits 162 to 166 to a desired voltage in a short time. Since each of the sample / hold circuits 162 to 166 is finally connected to the third DAC 146, a uniform image may be displayed in the pixel unit 30. In detail, since the DACs have a deviation of ± 3 mA, the output current values are set differently even when the same data is supplied. Thus, when the sample / hold circuits 162 to 166 are finally connected to different DACs, current deviation occurs, thus failing to display a uniform image. In order to prevent such a problem from occurring, in the integrated circuit 100 of the present invention, all the sample / hold circuits 162 to 166 are finally connected to the third DAC 146 to display a uniform image. have.

5 is a diagram illustrating a data integrated circuit according to a second embodiment of the present invention. 5, the same components as those in FIG. 2 are assigned the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 5, the data integrated circuit 100 according to the second embodiment of the present invention includes a reference current unit 170 installed to be connected to the current generation unit 140. The reference current unit 170 supplies a red reference current RR, a green reference current GR, and a blue reference current BR to the current generator 140. Here, the current values of the red reference current RR, the green reference current GR, and the blue reference current BR are set differently from each other in consideration of the white balance of the red pixel, the green pixel, and the blue pixel.

The first DAC 142, the second DAC 144, and the third DAC 146 supplied with the reference currents RR, GR, and BR receive the first data signal through the third day with reference to the reference currents RR, GR, and BR. Generate the signal. In practice, the first to third data signals supplied to the red pixel are generated corresponding to the current value of the red reference current RR. For example, the first DAC 142, the second DAC 144, and the third DAC 146 may set the current of the first data signal to the third data signal when the red reference current RR is set high for the gray value of the same data. If the value is set high and the red reference current RR is set low, the current value of the first data signal to the third data signal is set low.

The first to third data signals supplied to the green pixel are generated corresponding to the current value of the green reference current GR. For example, when the green reference current GR is set high with respect to the gray value of the same data, the first DAC 142, the second DAC 144, and the third DAC 146 have currents of the first to third data signals. If the value is set high and the green reference current GR is set low, the current value of the first data signal to the third data signal is set low.

The first to third data signals supplied to the blue pixel are generated corresponding to the current value of the blue reference current BR. For example, the first DAC 142, the second DAC 144, and the third DAC 146 may set the current of the first data signal to the third data signal when the blue reference current BR is set high with respect to the gray value of the same data. If the value is set high and the blue reference current BR is set low, the current value of the first data signal to the third data signal is set low.

6 is a diagram illustrating a data integrated circuit according to a third embodiment of the present invention.

Referring to FIG. 6, the data integrated circuit according to the third embodiment of the present invention may include a shift register 210, a sampling latch 220, a first holding latch 230, and a second holding latch 231. And first to sixth switching units 234, 235, 236, 242, 244 and 246, first to third current generators 260, 270, 280, and an output stage 250.

The shift register unit 210 receives a source shift clock SSC and a source start pulse SSP from the timing controller 50. The shift register unit 210 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 210 includes j shift registers 2101 to 210j.

The sampling latch unit 220 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register unit 210. Here, the sampling latch unit 220 includes j sampling latches 2201 to 220j to store j data.

The first holding latch unit 230 receives and stores data from the sampling latch unit 220. The first holding latch unit 230 stores data stored therein in the second holding latch unit 231, the first switching unit 234, the second switching unit 235, and the third switching unit 236. ). To this end, the first holding latch unit 230 includes j first holding latches 2301 to 230j.

The second holding latch unit 231 receives and stores data from the first holding latch unit 230. The second holding latch unit 231 supplies data stored therein to the first switching unit 234, the second switching unit 235, and the third switching unit 236. To this end, the second holding latch unit 231 includes j second holding latches 2311 to 231j.

The first switching unit 234 receives data to be supplied to the red pixel (hereinafter referred to as “red data”) from the first holding latch unit 230 and the second holding latch unit 231, and receives the supplied red data. It is supplied to the first current generator 260. Here, the first switching unit 234 supplies some red data included in the first holding latch unit 230 to the first DAC 262. The first switching unit 234 supplies some red data included in the second holding latch unit 231 to the second DAC 264.

For example, the first switching unit 234 sequentially connects the first first holding latch 2301 and the fourth first holding latch 2304 that store red data with the first DAC 262. The first switching unit 234 sequentially opens the j-second second holding latch 231j-2 with the second DAC 264 from the seventh second holding latch (not shown) that stores red data. Connect. In this case, the red data supplied to the first DAC 262 and the red data supplied to the second DAC 264 via the first switching unit 234 are set to different data. Meanwhile, the first switching unit 234 sequentially connects all the second holding latches 2311, 2314,..., 231j-2 storing red data with the third DAC 266.

The second switching unit 235 receives data to be supplied to the green pixel (hereinafter referred to as "green data") from the first holding latch unit 230 and the second holding latch unit 231, and receives the supplied green data. It is supplied to the second current generator 270. Here, the second switching unit 235 supplies some green data included in the first holding latch unit 230 to the fourth DAC 272. In addition, the second switching unit 235 supplies some green data included in the second holding latch unit 231 to the fifth DAC 274.

For example, the second switching unit 235 sequentially connects the second first holding latch 2302 and the fifth first holding latch 2305 that store the green data with the fourth DAC 272. The second switching unit 235 sequentially moves the j-th second holding latch 231j-1 to the fifth DAC 274 from the eighth second holding latch (not shown) that stores the green data. Connect. In this case, the green data supplied to the fourth DAC 272 and the green data supplied to the fifth DAC 274 via the second switching unit 235 are set to different data. Meanwhile, the second switching unit 235 sequentially connects all second holding latches 2312, 2315,..., 231j-1 storing green data with the sixth DAC 276.

The third switching unit 236 receives data to be supplied to the blue pixel from the first holding latch unit 230 and the second holding latch unit 231 (hereinafter referred to as "blue data"), and receives the supplied blue data. The third current generator 280 supplies the same. Here, the third switching unit 236 supplies some blue data included in the first holding latch unit 230 to the seventh DAC 282. In addition, the third switching unit 236 supplies some blue data included in the second holding latch unit 231 to the eighth DAC 284.

For example, the third switching unit 236 sequentially connects the third first holding latch 2303 and the sixth first holding latch 2306 with the seventh DAC 282 to store blue data. The third switching unit 236 sequentially connects the j-th second holding latch 231j to the eighth DAC 284 from the ninth second holding latch (not shown) that stores the blue data. In this case, the blue data supplied to the seventh DAC 282 and the blue data supplied to the eighth DAC 284 via the third switching unit 236 are set to different data. The third switching unit 236 sequentially connects all of the second holding latches 2313, 2316,..., 231j storing the blue data with the ninth DAC 286.

The first current generator 260 includes a first DAC 262, a second DAC 264, and a third DAC 266. The first DAC 262 sequentially receives some red data from the first holding latch unit 230 via the first switching unit 234. The first DAC 262 supplied with red data sequentially generates a first data signal as a current and supplies the generated first data signal to the fourth switching unit 242.

The second DAC 264 sequentially receives some red data from the second holding latch unit 231 via the first switching unit 234. The second DAC 264 supplied with the red data sequentially generates a second data signal as a current, and supplies the generated second data signal to the fourth switching unit 242.

The third DAC 266 sequentially receives all the red data from the second holding latch unit 231 via the first switching unit 234. The third DAC 266 supplied with the red data sequentially generates a third data signal as a current and supplies the generated third data signal to the fourth switching unit 242.

The second current generator 270 includes a fourth DAC 272, a fifth DAC 274, and a sixth DAC 276. The fourth DAC 272 sequentially receives some green data from the first holding latch unit 230 via the second switching unit 235. The fourth DAC 272 that receives the green data sequentially generates a first data signal as a current, and supplies the generated first data signal to the fifth switching unit 244.

The fifth DAC 274 sequentially receives some green data from the second holding latch unit 231 via the second switching unit 235. The fifth DAC 274 supplied with green data sequentially generates a second data signal as a current, and supplies the generated second data signal to the fifth switching unit 244.

The sixth DAC 276 sequentially receives all green data from the second holding latch unit 231 via the second switching unit 235. The sixth DAC 276 supplied with the green data sequentially generates a third data signal as a current and supplies the generated third data signal to the fifth switching unit 244.

The third current generator 280 includes a seventh DAC 282, an eighth DAC 284, and a ninth DAC 286. The seventh DAC 282 sequentially receives some blue data from the first holding latch unit 230 via the third switching unit 236. The seventh DAC 282 supplied with blue data sequentially generates a first data signal as a current, and supplies the generated first data signal to the sixth switching unit 246.

The eighth DAC 284 sequentially receives some blue data from the second holding latch unit 231 via the third switching unit 236. The eighth DAC 284 receiving the blue data sequentially generates a second data signal as a current, and supplies the generated second data signal to the sixth switching unit 246.

The ninth DAC 286 sequentially receives all blue data from the second holding latch unit 231 via the third switching unit 236. The ninth DAC 286 receiving the blue data sequentially generates a third data signal as a current and supplies the generated third data signal to the sixth switching unit 246.

The fourth switching unit 242 controls the connection between the first current generator 260 and the output stage 250. In fact, the fourth switching unit 242 is included in the output stage 250 and the first current sinking units 2501, 2504,..., 250j-2 and the first current generating unit 260 connected to the red pixel. To control connections between them. Here, the fourth switching unit 242 connects some of the first current sinks 2501, 2504,..., 250j-2 to the first DAC 262 and the remaining current sinks of the second DAC ( 264). For example, the fourth switching unit 242 sequentially connects the first first current sink 2501 and the fourth first current sink 2504 to the first DAC 262, and connects the remaining first current sinks. The second DAC 264 may be sequentially connected. In addition, the fourth switching unit 242 connects all of the first current sinking units 2501, 2504,..., 250j-2 to the third DAC 266.

The fifth switching unit 244 controls the connection between the second current generator 270 and the output stage 250. In fact, the fifth switching unit 244 is included in the output stage 250 and the second current sinking units 2502, 2505,..., 250j-1 and the second current generating unit 270 connected to the green pixel. To control connections between them. Here, the fifth switching unit 244 connects some of the second current sinks 2502, 2505,..., 250j-1 to the fourth DAC 272 and the remaining current sinks of the fifth DAC ( 274). For example, the fifth switching unit 244 sequentially connects the second second current sink 2502 and the fifth second current sink 2505 to the fourth DAC 272, and the remaining second current sinks. May be sequentially connected to the fifth DAC 274. The fifth switching unit 244 connects all of the second current sink units 2502, 2505,..., 250j-1 to the sixth DAC 276.

The sixth switching unit 246 controls the connection between the third current generator 280 and the output stage 250. In fact, the sixth switching unit 246 is included in the output stage 250 and is connected between the third current sinking units 2503, 2506,..., 250j and the third current generating unit 280 connected to the blue pixel. To control. Here, the sixth switching unit 246 connects some of the third current sinks 2503, 2506,..., 250j to the seventh DAC 282, and the remaining current sinks of the eighth DAC 284. Connect with. For example, the sixth switching unit 246 sequentially connects the third third current sink 2503 and the sixth third current sink 2506 to the seventh DAC 282, and the remaining third current sinks. Can be sequentially connected to the eighth DAC 284. The sixth switching unit 246 connects all of the third current sinking units 2503, 2506,..., 250j to the ninth DAC 286.

The output stage 250 has j current sinks 2501 to 250j positioned for each channel. Here, the current sinks 2501 to 250j may include the first current sinks 2501, 2504,..., 250j-2 connected to the red pixel, and the second current sinks 2502, 2505, connected to the green pixel. ..., 250j-1 and third current sinks 2503, 2505, ..., 250j connected to the blue pixel.

Each of the current sinks 2501 to 250j is connected to any one of the data lines D1 to Dj to receive a predetermined current from the pixel 40. In detail, each of the current sinks 2501 to 250j first charges a voltage by a first data signal or a second data signal, and finally charges a predetermined voltage by a third data signal. Each of the current sinks 2501 to 250j charged with a predetermined voltage receives a predetermined current from the pixels 40 in response to the charged voltage. (Current Sink) Then, each of the pixels 40 receives a current sink. The voltage is charged in response to the current supplied to the parts 2501 to 250j, and light of a predetermined brightness is generated by supplying a current corresponding to the charged voltage to the light emitting device. Meanwhile, the output stage 250 of the present invention is assumed to have the same structure as that of FIG. 3 for convenience of description, and detailed description thereof will be omitted.

3 and 6, the operation process will be described in detail. First, data is stored in the sampling latch unit 220 in response to the sampling signals sequentially supplied from the shift register unit 210. The data stored in the sampling latch unit 220 is supplied to the first holding latch unit 230.

All data stored in the first holding latch unit 230 are supplied to the second holding latch unit 231. Some of the red data stored in the first holding latch unit 230, for example, data stored in the first first holding latch 2301 and the fourth first holding latch 2304, may pass through the first switching unit 234. Sequentially supplied to the first DAC 262. Some data among the green data stored in the first holding latch unit 230, for example, data stored in the second first holding latch 2302 and the fifth first holding latch 2305, may be used as the second switching unit 235. Via sequentially supplied to the fourth DAC (272). Some data among the blue data stored in the second holding latch unit 230, for example, data stored in the third first holding latch 2303 and the sixth first holding latch 2306, may be used as the third switching unit 236. Via the seventh DAC (282).

The first DAC 262, which receives some red data from the first holding latch unit 230, generates a first data signal and supplies the generated first data signal to the second switching unit 242. The fourth DAC 272, which receives some green data from the first holding latch unit 230, generates a first data signal and supplies the generated first data signal to the fifth switching unit 244. The seventh DAC 282, which receives some blue data from the first holding latch unit 230, generates a first data signal and supplies the generated first data signal to the sixth switching unit 246.

The fourth switching unit 242 supplied with the first data signal supplies the first data signal to the first current sink 2501 and the fourth current sink 2504. Then, a predetermined voltage is precharged in the first sample / hold circuit 162 included in each of the first current sink 2501 and the fourth current sink 2504. The fifth switching unit 244 supplied with the first data signal supplies the first data signal to the second current sink 2502 and the fifth current sink 2505. Then, a predetermined voltage is precharged in the first sample / hold circuit 162 included in each of the second current sink 2502 and the fifth current sink 2505. The sixth switching unit 246 receiving the first data signal supplies the first data signal to the third current sink 2503 and the sixth current sink 2506. Then, a predetermined voltage is precharged in the first sample / hold circuit 162 included in each of the third current sink 2503 and the sixth current sink 2506.

On the other hand, after the data is stored in the second holding latch unit 231, the first switching unit 234 has j- from some red data included in the second holding latch unit 231, for example, the seventh second holding latch. The red data stored in the second second holding latch 231j-2 is sequentially supplied to the second DAC 264. The first switching unit 234 sequentially supplies all the red data stored in the second holding latch unit 231 to the third DAC 266.

After data is stored in the second holding latch unit 231, the second switching unit 235 may include some green data included in the second holding latch unit 231, for example, j−1th from the eighth second holding latch. The green data stored in the second holding latch 231j-1 is sequentially supplied to the fifth DAC 274. The second switching unit 235 sequentially supplies all the green data stored in the second holding latch unit 231 to the sixth DAC 276.

After data is stored in the second holding latch unit 231, the third switching unit 236 may include some blue data included in the second holding latch unit 231, for example, the j th second from the ninth second holding latch. The blue data stored in the holding latch 231j is sequentially supplied to the eighth DAC 284. The third switching unit 236 sequentially supplies all the blue data stored in the second holding latch unit 231 to the ninth DAC 286.

The second DAC 264, which receives some red data stored in the second holding latch unit 231, generates a second data signal and supplies the generated second data signal to the fourth switching unit 242. The third DAC 266, which receives all the red data stored in the second holding latch unit 231, generates a third data signal and supplies the generated third data signal to the fourth switching unit 242.

The fifth DAC 274, which receives some green data stored in the second holding latch unit 231, generates a second data signal and supplies the generated second data signal to the fifth switching unit 244. The sixth DAC 276, which receives all the green data stored in the second holding latch unit 231, generates a third data signal and supplies the generated second data signal to the fifth switching unit 244.

The eighth DAC 284, which receives some blue data stored in the second holding latch unit 231, generates a second data signal and supplies the generated second data signal to the sixth switching unit 246. The ninth DAC 286, which receives all the blue data stored in the second holding latch unit 231, generates a third data signal and supplies the generated second data signal to the sixth switching unit 246.

The fourth switching unit 242 receiving the second data signal receives the second data signal from the first current sinks (the seventh current sink to the j-2 current sink) that is not connected to the first DAC 262. Supply. Then, a predetermined voltage is precharged in the first sample / hold circuit 165 included in each of the first current sink units supplied with the second data signal. The fourth switching unit 242 supplied with the third data signal supplies the third data signal to all of the first current sink units 2501, 2504,..., 250j-2. Then, the first sample / hold circuits 162 and 165 precharged by the first data signal or the second data signal are finally charged. At this time, since the first sample / hold circuits 162 and 165 are precharged, a desired voltage is charged in a short time when the third data signal is supplied.

Meanwhile, the first DAC 262 during the period in which the first sample / hold circuits 162 and 165 included in the first current sinks 2501, 2504,..., 250j-2 are charged by the third data signal. ) Generates a first data signal using some red data stored in the first holding latch unit 230, and converts the generated first data signal into a first current sink 2501 and a fourth current sink 2504. Supply to the second sample / hold circuit 163 included in each. Then, the second sample / hold circuit 163 included in each of the first current sink 2501 and the fourth current sink 2504 is precharged.

The fifth switching unit 244 supplied with the second data signal supplies the second data signal to second current sinks (j-1 th current sink from the eighth current sink) that are not connected to the fourth DAC 272. do. Then, a predetermined voltage is precharged in the first sample / hold circuit 165 included in each of the second current sink units. The fifth switching unit 244 supplied with the third data signal supplies the third data signal to all of the second current sink units 2502, 2505,..., 250j-1. Then, the first sample / hold circuits 162 and 165 precharged by the first data signal or the second data signal are finally charged. At this time, since the first sample / hold circuits 162 and 165 are precharged, a desired voltage is charged in a short time when the third data signal is supplied.

Meanwhile, the fourth DAC 272 during the period in which the first sample / hold circuits 162 and 165 included in the second current sinks 2502, 2505,... 250j-1 are charged by the third data signal. The first data signal is generated by using some green data stored in the first holding latch unit 230, and the generated first data signal is respectively generated by the second current sink 2502 and the fifth current sink 2505. Supply to the second sample / hold circuit 163 included in. Then, the second sample / hold circuit 163 included in each of the second current sink 2502 and the fifth current sink 2505 is precharged.

The sixth switching unit 246 receiving the second data signal supplies the second data signal to the third current sinks (the ninth current sink to the jth current sink) that are not connected to the seventh DAC 282. Then, a predetermined voltage is precharged in the first sample / hold circuit 165 included in each of the third current sink units. The sixth switching unit 246 receives the third data signal and supplies the third data signal to all the third current sink units 2503, 2506,..., 250j. Then, the first sample / hold circuits 162 and 165 precharged by the first data signal or the second data signal are finally charged. At this time, since the first sample / hold circuits 162 and 165 are precharged, a desired voltage is charged in a short time when the third data signal is supplied.

On the other hand, during the period in which the first sample / hold circuits 162 and 165 included in the third current sinks 2503, 2506,. The first data signal is generated using some blue data stored in the first holding latch unit 230 and the generated first data signal is included in each of the third current sink 2503 and the sixth current sink 2506. To the second sample / hold circuit 163. Then, the second sample / hold circuit 163 included in each of the third current sink 2503 and the sixth current sink 2506 is precharged.

Thereafter, during the next horizontal period, the second DAC 144, the fifth DAC 274, and the eighth DAC 284 generate a second data signal, and include the seventh current sink to the j th current sink 250j. The two sample / hold circuit 166 is precharged. The third DAC 266, the sixth DAC 276, and the ninth DAC 286 generate a third data signal to generate the second sample / hold circuit 163 included in each of the first current sinks 2501 to 250j. 166) to finally charge.

In this case, each of the first sample / hold circuits 162 and 165 included in each of the first current sink 2501 to the j th current sink 250j corresponds to the voltage charged in the previous horizontal period. A predetermined current is supplied from. During the next horizontal period, the first DAC 262, the fourth DAC 272, and the seventh DAC 282 each include a third sample / hold included in each of the first current sink 2501 to the sixth current sink 2506. Precharge the circuit 164. In fact, the data integrated circuit 100 of the present invention shown in FIG. 6 receives a predetermined current from the pixels 40 while repeating the above-described process.

That is, the data integrated circuit according to the third embodiment of the present invention simultaneously generates data signals to be supplied to the red pixel, the green pixel, and the blue pixel. As such, when data signals to be supplied to the red pixel, the green pixel, and the blue pixel are simultaneously generated, the driving time can be shortened by about one third of the data integrated circuit according to the first embodiment of the present invention. Therefore, the data integrated circuit according to the third embodiment of the present invention can be applied to a data integrated circuit having many channels.

7 is a diagram showing a data integrated circuit according to a fourth embodiment of the present invention. 7, the same components as those in FIG. 6 are assigned the same reference numerals and detailed description thereof will be omitted.

Referring to FIG. 7, the data integrated circuit 100 according to the fourth embodiment of the present invention is connected to the first current generator 260, the second current generator 270, and the third current generator 280. The reference current unit 290 is provided. The reference current unit 290 generates a red reference current RR, a green reference current GR, and a blue reference current BR set to different current values in consideration of white balance.

The red reference current RR generated by the reference current unit 290 is supplied to the first current generator 260, and the green reference current GR is supplied to the second current generator 270. The blue reference current BR generated by the reference current unit 290 is supplied to the third current generator 280.

The first current generator 260 supplied with the red reference current RR generates the first to third data signals corresponding to the red reference current RR. For example, when the red reference current RR is set high, the first current generator 260 generates the first data signal to the third data signal having a high current value, and the red reference current RR is low. When set, the first data signal to the third data signal having a low current value are generated.

The second current generator 270 supplied with the green reference current GR generates the first to third data signals in response to the green reference current GR. For example, when the green reference current GR is set high, the second current generator 270 generates the first data signal to the third data signal having a high current value, and the green reference current GR is low. When set, the first data signal to the third data signal having a low current value are generated.

The third current generator 280 supplied with the blue reference current BR generates the first to third data signals in response to the blue reference current BR. For example, when the blue reference current BR is set high, the third current generator 280 generates the first data signal to the third data signal having a high current value, and the blue reference current GR is low. When set, the first data signal to the third data signal having a low current value are generated.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the data integrated circuit and the light emitting display device using the same according to the embodiment of the present invention, the sample / hold circuits included in the current sink are primarily charged and the first charged sample / hold circuits are finally charged. Because of the charging, the sample / hold circuits can be charged to the desired voltage quickly. In the present invention, the sample / hold circuits can be stably primary charged using data stored in two holding latches. Further, the sample / hold circuits of the present invention are finally connected to the same DAC, so that images of a uniform image can be displayed.

Claims (20)

A first holding latch unit for storing data supplied from the outside; A second holding latch unit for receiving and storing the data from the first holding latch unit; A first digital-analog converter for sequentially receiving some data stored in the first holding latch unit to generate a first data signal as a current; A second digital-to-analog converter for sequentially receiving some data stored in the second holding latch unit to generate a second data signal as a current; A third digital-analog converter for sequentially receiving all data stored in the second holding latch unit to generate a third data signal as a current; And an output stage including a plurality of current sinks which are first charged upon receiving the first data signal or a second data signal, and which are finally charged upon receiving the third data signal. The method of claim 1, And data supplied from the first holding latch unit to the first digital-analog converter and data supplied from the second holding latch unit to the second digital-analog converter are different data. The method of claim 2, Some current sinks included in the output stage are primarily charged by a first data signal, and remaining current sinks included in the output stage are primarily charged by a second data signal. The method of claim 3, wherein And all current sinks included in the output stage are finally charged by the third data signal, and receive a current corresponding to the charged voltage from the pixel via a data line. The method of claim 4, wherein Each of the current sinks supplied with the first data signal A first sample / hold circuit that receives current from the pixel corresponding to the voltage charged in the previous period; A second sample / hold circuit primarily charged by the first data signal; And a third sample / hold circuit finally charged by the third data signal. The method of claim 4, wherein Each of the current sink units supplied with the second data signal A first sample / hold circuit that receives current from the pixel corresponding to the voltage charged in the previous period; And a second sample / hold circuit that is primarily charged by the second data signal and finally charged by the third data signal. The method of claim 3, wherein A first switching unit for connecting the first holding latch unit and the second holding latch unit with the first digital-analog converter, the second digital-analog converter, and the third digital-analog converter; And a second switching unit for connecting the first digital-analog converter, the second digital-analog converter, and the third digital-analog converter to the output stage. The method of claim 1, A shift register section for generating a sampling signal sequentially; And a sampling latch unit configured to store the data in response to the sampling signal and to supply the stored data to the first holding latch unit. The method of claim 8, The red reference current, the green reference current, and the blue reference current set to different current values in consideration of white balance are supplied to the first digital-analog converter, the second digital-analog converter, and the third digital-analog converter. A data integrated circuit further comprising a reference current unit for performing. A first holding latch unit for storing data supplied from the outside; A second holding latch unit for receiving and storing the data from the first holding latch unit; A first current generator configured to control charging voltages of the first current sink units connected to the red pixel by using red data stored in the first holding latch unit and the second holding latch unit; A second current generator configured to control charging voltages of second current sink units connected to the green pixel by using green data stored in the first holding latch unit and the second holding latch unit; A third current generator configured to control charging voltages of third current sink units connected to the blue pixel by using blue data stored in the first holding latch unit and the second holding latch unit; And an output stage comprising the first current sinks, the second current sinks, and the third current sinks. The method of claim 10, Each of the first current generator, the second current generator, and the third current generator A first digital-analog converter configured to receive the partial red data, green data, or blue data stored in the first holding latch unit to generate a first data signal as a current; A second digital-analog converter configured to receive the partial red data, green data or blue data stored in the second holding latch unit to generate a second data signal as a current; And a third digital-analog converter configured to receive all red data, green data, or blue data stored in the second holding latch unit to generate a third data signal as a current. The method of claim 11, And data supplied from the first holding latch unit to the first digital-analog converter and data supplied from the second holding latch unit to the second digital-analog converter are different data. The method of claim 11, Some of the first current sinks, the second current sinks, and the third current sinks are first charged when the first data signal is supplied, and the first current when the second data signal is supplied. And the remaining ones of the sinks, the second current sinks, and the third current sinks are primarily charged. The method of claim 13, And the first current sinks, the second current sinks, and the third current sinks are finally charged when the third data signal is supplied. The method of claim 14, Each of the some sinks supplied with the first data signal A first sample / hold circuit that receives current from the red pixel, the green pixel, or the blue pixel corresponding to the voltage charged in the previous period; A second sample / hold circuit primarily charged by the first data signal; And a third sample / hold circuit finally charged by the third data signal. The method of claim 14, Each of the remaining sinks receiving the second data signal A first sample / hold circuit that receives current from the red pixel, the green pixel, or the blue pixel corresponding to the voltage charged in the previous period; And a second sample / hold circuit that is primarily charged by the second data signal and finally charged by the third data signal. The method of claim 10, A first switching unit for connecting the first holding latch unit, the second holding latch unit, and the first current generating unit; A second switching unit for connecting the first holding latch unit, the second holding latch unit, and the second current generating unit; A third switching unit for connecting the first holding latch unit, the second holding latch unit, and the third current generating unit; A fourth switching unit for connecting the first current generating unit and the first current sinking units; A fifth switching unit for connecting the second current generating unit and the second current sinking units; And a sixth switching unit for connecting the third current generating unit and the third current sinking units. The method of claim 10, A shift register section for generating a sampling signal sequentially; And a sampling latch unit configured to store the data in response to the sampling signal and to supply the stored data to the first holding latch unit. The method of claim 18, In consideration of white balance, a red reference current, a green reference current, and a blue reference current set to different current values are generated, the red reference current is supplied to the first current generator, and the green reference current is supplied to the second current generator. And a reference current unit for supplying the blue reference current to the third current generation unit. A scan driver for driving the scan lines; A data driver for driving data lines; A pixel portion including a plurality of pixels positioned to be connected to the scan lines and the data lines, 20. The light emitting display device of claim 1, wherein the data driver comprises at least one data integrated circuit according to any one of claims 1 to 19.

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