KR100685622B1 - Method of forming a contact plug in a semiconductor device - Google Patents

Method of forming a contact plug in a semiconductor device Download PDF

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KR100685622B1
KR100685622B1 KR1020010080097A KR20010080097A KR100685622B1 KR 100685622 B1 KR100685622 B1 KR 100685622B1 KR 1020010080097 A KR1020010080097 A KR 1020010080097A KR 20010080097 A KR20010080097 A KR 20010080097A KR 100685622 B1 KR100685622 B1 KR 100685622B1
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forming
conductive material
contact plug
barrier layer
contact hole
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KR1020010080097A
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KR20030049784A (en
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이진혁
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 콘택홀에 금속 장벽층을 형성한 후 금속 장벽층의 측벽에 절연막 스페이서를 형성한 상태에서 화학기상 증착법으로 전도성 물질을 증착함으로써, 콘택홀의 측벽에 형성된 절연막 스페이서에 전도성 물질이 증착되는 것을 억제하면서 콘택홀 하부의 금속 장벽층에서부터 상부 방향으로만 증착이 이루어지도록 하여 콘택 플러그에 심(Seam)이나 키 홀(Key hole)이 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법이 개시된다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device, and in particular, by depositing a conductive material by chemical vapor deposition in a state where an insulating layer spacer is formed on a sidewall of a metal barrier layer after the metal barrier layer is formed in the contact hole. While the conductive material is prevented from being deposited on the insulating layer spacer formed on the sidewalls, the deposition is performed only upward from the metal barrier layer below the contact hole, thereby preventing the formation of seams or key holes in the contact plug. A method of forming a contact plug of a semiconductor device is disclosed, which can improve process reliability and device electrical characteristics.

콘택 플러그, 금속 장벽층, 절연막 스페이서, 심, 키홀Contact Plug, Metal Barrier Layer, Insulation Spacer, Shim, Keyhole

Description

반도체 소자의 콘택 플러그 형성 방법{Method of forming a contact plug in a semiconductor device} Method of forming a contact plug in a semiconductor device             

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위한 소자의 단면도.
1A to 1F are cross-sectional views of a device for explaining a method for forming a contact plug of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 : 반도체 기판 12 : 제 1 층간 절연막11 semiconductor substrate 12 first interlayer insulating film

13 : 하부 금속 배선 14 : 제 2 층간 절연막13: lower metal wiring 14: second interlayer insulating film

14a : 콘택홀 15 : Ti막14a: contact hole 15: Ti film

16 : TiN막 17 : 금속 장벽층16 TiN film 17 metal barrier layer

18a : 산화막 18 : 절연막 스페이서18a: oxide film 18: insulating film spacer

19 : 콘택 플러그
19: contact plug

본 발명은 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 콘택 플러그에 키 홀 및 심이 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법에 관한 것이다.
The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device capable of preventing key holes and seams from being generated in a contact plug, thereby improving process reliability and device electrical characteristics. .

소자가 점점 고집적화 되어감에 따라 금속 배선은 다층 배선으로 형성되며, 상부 금속 배선과 하부 금속 배선을 전기적으로 연결시키기 위하여 층간 절연막에는 콘택홀이 형성되고, 콘택홀에는 콘택 플러그가 형성된다. As the devices are increasingly integrated, metal wirings are formed of multilayer wirings, and contact holes are formed in the interlayer insulating film and contact plugs are formed in the contact holes to electrically connect the upper metal wiring and the lower metal wiring.

콘택 플러그는 콘택홀에 매립된 전도성 물질(예를 들어, 텅스텐)로 형성되며, 전도성 물질과 층간 절연막의 계면에는 Ti막과 TiN막으로 이루어진 금속 장벽층이 형성된다. 금속 장벽층은 층간 절연막에 의해 전도성 물질이 산화되는 것을 방지함과 동시에, 전도성 물질의 금속 성분이 층간 절연막으로 확산되어 소자의 전기적 특성이 저하되는 것을 방지하는 역할을 한다. The contact plug is formed of a conductive material (eg, tungsten) embedded in the contact hole, and a metal barrier layer made of a Ti film and a TiN film is formed at an interface between the conductive material and the interlayer insulating film. The metal barrier layer prevents the conductive material from being oxidized by the interlayer insulating film, and at the same time, serves to prevent the metal component of the conductive material from being diffused into the interlayer insulating film to deteriorate the electrical characteristics of the device.

일반적으로, 콘택홀이 형성되면 콘택홀 내부에 금속 장벽층을 먼저 형성하고, 콘택홀을 전도성 물질로 매립하여 전도성 물질로 이루어진 콘택 플러그를 형성한다. 콘택 플러그를 형성하기 위한 전도성 물질은 화학기상 증착법으로 형성되며, 이로 인하여 층간 절연막의 상부에도 전도성 물질이 증착된다. 따라서, 층간 절연막 상부에 증착된 전도성 물질을 제거하면서 콘택홀에만 전도성 물질을 잔류시키기 위하여 화학적 기계적 연마를 실시한다. In general, when the contact hole is formed, a metal barrier layer is first formed in the contact hole, and the contact hole is filled with a conductive material to form a contact plug made of a conductive material. The conductive material for forming the contact plug is formed by chemical vapor deposition, thereby depositing the conductive material on top of the interlayer insulating film. Therefore, chemical mechanical polishing is performed to remove the conductive material deposited on the interlayer insulating film and to leave the conductive material only in the contact hole.

이때, 화학기상 증착법으로 전도성 물질을 증착하는 과정에서, 금속 장벽층의 저면뿐만 아니라 측벽에서도 전도성 물질의 증착이 이루어진다. 금속 장벽층의 측벽에서 증착된 전도성 물질은 콘택홀의 중심축에서 서로 맞닿는다. 이로 인하여, 콘택 플러그의 중심에는 심(Seam)이 발생되고, 콘택 플러그의 상부에는 키 홀(Key hole)이 발생되어 공정의 신뢰성 및 소자의 전기적 특성이 저하되는 문제점이 발생된다.
At this time, in the process of depositing the conductive material by chemical vapor deposition, the deposition of the conductive material is performed on the sidewalls as well as the bottom of the metal barrier layer. The conductive materials deposited on the sidewalls of the metal barrier layer abut each other at the central axis of the contact hole. As a result, a seam is generated in the center of the contact plug, and a key hole is generated in the upper portion of the contact plug, thereby degrading reliability of the process and electrical characteristics of the device.

따라서, 본 발명은 상기의 문제점을 해결하기 위하여 콘택홀에 금속 장벽층을 형성한 후 금속 장벽층의 측벽에 절연막 스페이서를 형성한 상태에서 화학기상 증착법으로 전도성 물질을 증착함으로써, 콘택홀의 측벽에 형성된 절연막 스페이서에 전도성 물질이 증착되는 것을 억제하면서 콘택홀 하부의 금속 장벽층에서부터 상부 방향으로만 증착이 이루어지도록 하여 콘택 플러그에 심이나 키 홀이 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는데 그 목적이 있다.
Therefore, the present invention is formed on the sidewall of the contact hole by depositing a conductive material by chemical vapor deposition in a state in which an insulating film spacer is formed on the sidewall of the metal barrier layer after forming a metal barrier layer in the contact hole to solve the above problems While preventing the deposition of conductive material on the insulating film spacer, the deposition is performed only from the metal barrier layer below the contact hole to the upper direction, thereby preventing the generation of seams or key holes in the contact plug, thereby improving process reliability and device electrical characteristics. It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device that can be improved.

본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법은 콘택홀에 전도성 물질을 증착하여 전도성 물질로 이루어진 콘택 플러그를 형성하는 반도체 소자의 콘택 플러그 형성 방법에 있어서, 콘택홀의 측벽에 전도성 물질의 증착을 방해하기 위하여 절연막 스페이서를 형성한 후 전도성 물질이 수직으로만 증착되도록 함으로써, 전도성 물질로 이루어진 콘택 플러그에 심이나 키 홀이 발생되는 것을 방지할 수 있는 것을 특징으로 한다.In the method of forming a contact plug of a semiconductor device according to the present invention, in the method of forming a contact plug of a semiconductor device by depositing a conductive material in a contact hole to form a contact plug made of a conductive material, preventing the deposition of the conductive material on a sidewall of the contact hole. In order to form the insulating film spacer so that the conductive material is deposited only vertically, it is possible to prevent the generation of seams or key holes in the contact plug made of the conductive material.

본 발명의 다른 실시예에 따른 반도체 소자의 콘택 플러그 형성 방법은 하부 금속 배선이 형성된 반도체 기판 상에 층간 절연막을 형성한 후 콘택홀을 형성하는 단계와, 콘택홀의 측벽 및 저면에 금속 장벽층을 형성하는 단계와, 금속 장벽층의 측벽에 절연막 스페이서를 형성하는 단계와, 전도성 물질을 증착한 후 화학적 기계적 연마를 실시하여 콘택홀에 콘택 플러그를 형성하는 단계로 이루어지는 것을 특징으로 한다. According to another aspect of the present invention, there is provided a method of forming a contact plug of a semiconductor device, forming a contact hole after forming an interlayer insulating film on a semiconductor substrate on which a lower metal wiring is formed, and forming a metal barrier layer on sidewalls and bottom surfaces of the contact hole. And forming an insulating film spacer on the sidewall of the metal barrier layer, and forming a contact plug in the contact hole by depositing a conductive material and performing chemical mechanical polishing.

상기에서, 금속 장벽층은 티타늄막 및 티타늄 질화막의 적층 구조로 형성되며, 산화막은 100 내지 1000Å의 두께로 형성된다.
In the above, the metal barrier layer is formed of a laminated structure of a titanium film and a titanium nitride film, the oxide film is formed to a thickness of 100 to 1000Å.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 더 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for describing a method for forming a contact plug of a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11) 상에 제 1 층간 절연막(12)을 형성한 후 소정 영역에 트렌치를 형성한다. 이후 트렌치에 전도성 물질을 매립하여 트렌치 구조의 하부 금속 배선(13)을 형성한다. Referring to FIG. 1A, a first interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which various elements for forming a semiconductor element are formed, and then trenches are formed in a predetermined region. Then, the conductive material is embedded in the trench to form the lower metal interconnection 13 of the trench structure.

이후, 전체 상부에 제 2 층간 절연막(14)을 형성하고, 콘택홀 마스크를 이용한 식각 공정으로 제 2 층간 절연막(14)의 소정 영역에 콘택홀(14a)을 형성한다. 이로써, 후속 공정에서 형성될 콘택 플러그를 통하여 상부 금속 배선과 전기적으로 연결될 하부 금속 배선(13)의 표면이 콘택홀(14a)을 통하여 노출된다. Subsequently, the second interlayer insulating layer 14 is formed on the entire upper portion, and the contact hole 14a is formed in a predetermined region of the second interlayer insulating layer 14 by an etching process using a contact hole mask. Thus, the surface of the lower metal wiring 13 to be electrically connected to the upper metal wiring through the contact plug to be formed in the subsequent process is exposed through the contact hole 14a.

도 1b를 참조하면, 콘택홀(14a)을 포함한 제 2 층간 절연막(14) 상부에 Ti막(15) 및 TiN막(16)을 순차적으로 형성한다. 이로써, Ti막(15)과 TiN막(16)으로 이루어진 금속 장벽층(17)이 형성된다. Referring to FIG. 1B, the Ti film 15 and the TiN film 16 are sequentially formed on the second interlayer insulating film 14 including the contact hole 14a. As a result, a metal barrier layer 17 composed of the Ti film 15 and the TiN film 16 is formed.

도 1c를 참조하면, 콘택홀(14a)을 포함한 제 2 층간 절연막(14) 상부에 산화막(18)을 형성한다. 이때, 산화막(18a)은 100 내지 1000Å의 두께로 형성된다. Referring to FIG. 1C, an oxide film 18 is formed on the second interlayer insulating film 14 including the contact hole 14a. At this time, the oxide film 18a is formed to a thickness of 100 to 1000 GPa.

도 1d를 참조하면, 전면 식각 공정을 실시하여 제 2 층간 절연막(14) 상부의 산화막 및 콘택홀(14a) 저면의 산화막을 제거하고 금속 장벽층(17)의 측벽에만 산화막을 잔류시켜, 산화막으로 이루어진 절연막 스페이서(18)를 형성한다. Referring to FIG. 1D, the entire surface etching process is performed to remove the oxide layer on the second interlayer insulating layer 14 and the oxide layer on the bottom of the contact hole 14a and to leave the oxide layer only on the sidewall of the metal barrier layer 17. The insulating film spacer 18 thus formed is formed.

도 1e를 참조하면, 화학기상 증착법으로 전도성 물질을 증착한다. 이때, 콘택홀(14a)의 측벽에 형성된 절연막 스페이서(18)에는 전도성 물질이 거의 증착되지 않으며, 콘택홀(14a) 하부의 금속 장벽층(17)에서부터 상부 방향으로만 전도성 물질의 증착이 이루어진다. 상기에서, 전도성 물질로 텅스텐을 사용할 수도 있다. Referring to FIG. 1E, the conductive material is deposited by chemical vapor deposition. At this time, the conductive material is hardly deposited on the insulating layer spacer 18 formed on the sidewall of the contact hole 14a, and the conductive material is deposited only upward from the metal barrier layer 17 under the contact hole 14a. In the above, tungsten may be used as the conductive material.

도 1f를 참조하면, 콘택홀(14a)이 충분히 매립되도록 전도성 물질을 증착한 후 화학적 기계적 연마를 실시하여 제 2 층간 절연막(14) 상부에 증착된 전도성 물질을 제거한다. 이로써, 전도성 물질은 콘택홀(14a)의 내부에만 잔류되어 전도성 물질로 이루어진 콘택 플러그(19)가 형성된다.
Referring to FIG. 1F, a conductive material is deposited to sufficiently fill the contact hole 14a, and then chemical mechanical polishing is performed to remove the conductive material deposited on the second interlayer insulating layer 14. As a result, the conductive material remains only inside the contact hole 14a to form the contact plug 19 made of the conductive material.

상술한 바와 같이, 본 발명은 콘택홀 내부에서 전도성 물질이 저면에서부터 상부 방향으로만 증착되도록 함으로써 콘택 플러그의 중심에 심이 발생되는 것을 방지하면서, 콘택 플러그의 상부에 키 홀이 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킨다.  As described above, according to the present invention, the conductive material is deposited only from the bottom to the upper direction of the inside of the contact hole, thereby preventing the core from being generated at the center of the contact plug, and preventing the key hole from being generated at the top of the contact plug. To improve the reliability and electrical properties of the device.

Claims (4)

콘택홀에 전도성 물질을 증착하여 상기 전도성 물질로 이루어진 콘택 플러그를 형성하는 반도체 소자의 콘택 플러그 형성 방법에 있어서,In the method of forming a contact plug of a semiconductor device by depositing a conductive material in a contact hole to form a contact plug made of the conductive material, 상기 콘택홀의 측벽에 전도성 물질의 증착을 방해하기 위하여 절연막 스페이서를 형성한 후 상기 전도성 물질이 수직으로만 증착되도록 함으로써, 상기 전도성 물질로 이루어진 콘택 플러그에 심이나 키 홀이 발생되는 것을 방지할 수 있는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.By forming an insulating film spacer on the sidewall of the contact hole to prevent the deposition of the conductive material, the conductive material is deposited only vertically, thereby preventing the generation of seams or key holes in the contact plug made of the conductive material. A contact plug forming method for a semiconductor device, characterized in that. 하부 금속 배선이 형성된 반도체 기판 상에 층간 절연막을 형성한 후 콘택홀을 형성하는 단계와, Forming a contact hole after forming an interlayer insulating film on a semiconductor substrate on which lower metal wirings are formed; 상기 콘택홀의 측벽 및 저면에 금속 장벽층을 형성하는 단계와,Forming a metal barrier layer on sidewalls and bottom surfaces of the contact holes; 상기 금속 장벽층의 측벽에 절연막 스페이서를 형성하는 단계와,Forming insulating film spacers on sidewalls of the metal barrier layer; 전도성 물질을 증착한 후 화학적 기계적 연마를 실시하여 상기 콘택홀에 콘택 플러그를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.Forming a contact plug in the contact hole by performing chemical mechanical polishing after depositing a conductive material. 제 2 항에 있어서,The method of claim 2, 상기 금속 장벽층은 티타늄막 및 티타늄 질화막의 적층 구조로 형성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The metal barrier layer is a contact plug forming method of a semiconductor device, characterized in that formed in a laminated structure of a titanium film and titanium nitride film. 제 2 항에 있어서,The method of claim 2, 상기 절연막은 산화막을 사용하여 100 내지 1000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.And the insulating film is formed to a thickness of 100 to 1000 Å using an oxide film.
KR1020010080097A 2001-12-17 2001-12-17 Method of forming a contact plug in a semiconductor device KR100685622B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025452A (en) * 1998-10-12 2000-05-06 윤종용 Method for manufacturing semiconductor device
KR100273989B1 (en) * 1997-11-25 2001-01-15 윤종용 Method for forming contact of semiconductor device
KR100426811B1 (en) * 2001-07-12 2004-04-08 삼성전자주식회사 Semiconductor device having SAC and Fabrication Method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273989B1 (en) * 1997-11-25 2001-01-15 윤종용 Method for forming contact of semiconductor device
KR20000025452A (en) * 1998-10-12 2000-05-06 윤종용 Method for manufacturing semiconductor device
KR100426811B1 (en) * 2001-07-12 2004-04-08 삼성전자주식회사 Semiconductor device having SAC and Fabrication Method thereof

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