KR100670227B1 - 반도체 디바이스에 구리 배선을 제조하는 방법 - Google Patents

반도체 디바이스에 구리 배선을 제조하는 방법 Download PDF

Info

Publication number
KR100670227B1
KR100670227B1 KR1020027009687A KR20027009687A KR100670227B1 KR 100670227 B1 KR100670227 B1 KR 100670227B1 KR 1020027009687 A KR1020027009687 A KR 1020027009687A KR 20027009687 A KR20027009687 A KR 20027009687A KR 100670227 B1 KR100670227 B1 KR 100670227B1
Authority
KR
South Korea
Prior art keywords
forming
copper
dielectric layer
layer
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020027009687A
Other languages
English (en)
Korean (ko)
Other versions
KR20020074216A (ko
Inventor
박스테판키타이
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20020074216A publication Critical patent/KR20020074216A/ko
Application granted granted Critical
Publication of KR100670227B1 publication Critical patent/KR100670227B1/ko
Assigned to 글로벌파운드리즈 인크. reassignment 글로벌파운드리즈 인크. 권리의 전부이전등록 Assignors: 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/058—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by depositing on sacrificial masks, e.g. using lift-off
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020027009687A 2000-01-28 2000-09-20 반도체 디바이스에 구리 배선을 제조하는 방법 Expired - Fee Related KR100670227B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/493,320 2000-01-28
US09/493,320 US6303486B1 (en) 2000-01-28 2000-01-28 Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal

Publications (2)

Publication Number Publication Date
KR20020074216A KR20020074216A (ko) 2002-09-28
KR100670227B1 true KR100670227B1 (ko) 2007-01-17

Family

ID=23959740

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027009687A Expired - Fee Related KR100670227B1 (ko) 2000-01-28 2000-09-20 반도체 디바이스에 구리 배선을 제조하는 방법

Country Status (5)

Country Link
US (1) US6303486B1 (https=)
EP (1) EP1250715A1 (https=)
JP (1) JP2003521123A (https=)
KR (1) KR100670227B1 (https=)
WO (1) WO2001056077A1 (https=)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6332900B1 (en) * 1999-02-08 2001-12-25 Wilson Greatbatch Ltd. Physical vapor deposited electrode component and method of manufacture
US6355555B1 (en) * 2000-01-28 2002-03-12 Advanced Micro Devices, Inc. Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer
US6858937B2 (en) * 2000-03-02 2005-02-22 Micron Technology, Inc. Backend metallization method and device obtained therefrom
US6635564B1 (en) * 2000-09-14 2003-10-21 Infineon Technologies Ag Semiconductor structure and method of fabrication including forming aluminum columns
US6373135B1 (en) * 2000-09-14 2002-04-16 Infineon Technologies Ag Semiconductor structure and method of fabrication
US6429118B1 (en) * 2000-09-18 2002-08-06 Taiwan Semiconductor Manufacturing Company Elimination of electrochemical deposition copper line damage for damascene processing
US6689684B1 (en) * 2001-02-15 2004-02-10 Advanced Micro Devices, Inc. Cu damascene interconnections using barrier/capping layer
US6506668B1 (en) * 2001-06-22 2003-01-14 Advanced Micro Devices, Inc. Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US6686273B2 (en) * 2001-09-26 2004-02-03 Sharp Laboratories Of America, Inc. Method of fabricating copper interconnects with very low-k inter-level insulator
US20050202667A1 (en) * 2001-12-03 2005-09-15 University Of Southern California Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates
US20080121343A1 (en) * 2003-12-31 2008-05-29 Microfabrica Inc. Electrochemical Fabrication Methods Incorporating Dielectric Materials and/or Using Dielectric Substrates
US6706629B1 (en) 2003-01-07 2004-03-16 Taiwan Semiconductor Manufacturing Company Barrier-free copper interconnect
KR100539444B1 (ko) * 2003-07-11 2005-12-27 매그나칩 반도체 유한회사 반도체 소자의 금속배선 형성방법
FR2859822B1 (fr) * 2003-09-16 2006-05-05 Commissariat Energie Atomique Structure d'interconnexion a faible constante dielectrique
KR100538379B1 (ko) * 2003-11-11 2005-12-21 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법
US20050130407A1 (en) * 2003-12-12 2005-06-16 Jui-Neng Tu Dual damascene process for forming a multi-layer low-k dielectric interconnect
US7169659B2 (en) * 2004-08-31 2007-01-30 Texas Instruments Incorporated Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
US7312146B2 (en) * 2004-09-21 2007-12-25 Applied Materials, Inc. Semiconductor device interconnect fabricating techniques
US7129127B2 (en) * 2004-09-24 2006-10-31 Texas Instruments Incorporated Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation
US7172936B2 (en) * 2004-09-24 2007-02-06 Texas Instruments Incorporated Method to selectively strain NMOS devices using a cap poly layer
KR100613346B1 (ko) * 2004-12-15 2006-08-21 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
US7422975B2 (en) * 2005-08-18 2008-09-09 Sony Corporation Composite inter-level dielectric structure for an integrated circuit
US20070194450A1 (en) 2006-02-21 2007-08-23 Tyberg Christy S BEOL compatible FET structure
US8785238B2 (en) 2010-07-01 2014-07-22 Panasonic Corporation Nonvolatile memory element and method for manufacturing same
CN103460383B (zh) 2011-04-14 2016-01-06 松下电器产业株式会社 非易失性存储元件及其制造方法
US9613852B2 (en) * 2014-03-21 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method making the same
US10629478B2 (en) 2017-08-22 2020-04-21 International Business Machines Corporation Dual-damascene formation with dielectric spacer and thin liner
US11361993B2 (en) * 2018-12-14 2022-06-14 Tokyo Electron Limited Method for inverse via patterning for back end of line dual damascene structures
US10903111B2 (en) * 2019-03-20 2021-01-26 International Business Machines Corporation Semiconductor device with linerless contacts
US11177170B2 (en) 2020-01-16 2021-11-16 International Business Machines Corporation Removal of barrier and liner layers from a bottom of a via
US11177166B2 (en) * 2020-04-17 2021-11-16 International Business Machines Corporation Etch stop layer removal for capacitance reduction in damascene top via integration
US12438084B2 (en) * 2021-12-13 2025-10-07 International Business Machines Corporation Dual-metal ultra thick metal (UTM) structure

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810332A (en) * 1988-07-21 1989-03-07 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer copper interconnect
US5177567A (en) * 1991-07-19 1993-01-05 Energy Conversion Devices, Inc. Thin-film structure for chalcogenide electrical switching devices and process therefor
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5413962A (en) * 1994-07-15 1995-05-09 United Microelectronics Corporation Multi-level conductor process in VLSI fabrication utilizing an air bridge
US5567982A (en) * 1994-09-30 1996-10-22 Bartelink; Dirk J. Air-dielectric transmission lines for integrated circuits
US5559055A (en) 1994-12-21 1996-09-24 Advanced Micro Devices, Inc. Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US6057224A (en) 1996-03-29 2000-05-02 Vlsi Technology, Inc. Methods for making semiconductor devices having air dielectric interconnect structures
US5744376A (en) * 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer
US5602053A (en) * 1996-04-08 1997-02-11 Chartered Semidconductor Manufacturing Pte, Ltd. Method of making a dual damascene antifuse structure
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
US5880018A (en) * 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
US6124189A (en) * 1997-03-14 2000-09-26 Kabushiki Kaisha Toshiba Metallization structure and method for a semiconductor device
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US5989623A (en) 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization
JP2971454B2 (ja) * 1997-08-21 1999-11-08 松下電子工業株式会社 半導体装置とその製造方法
US5969425A (en) * 1997-09-05 1999-10-19 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
US6117760A (en) * 1997-11-12 2000-09-12 Advanced Micro Devices, Inc. Method of making a high density interconnect formation
US6124198A (en) * 1998-04-22 2000-09-26 Cvc, Inc. Ultra high-speed chip interconnect using free-space dielectrics
US6147000A (en) * 1998-08-11 2000-11-14 Advanced Micro Devices, Inc. Method for forming low dielectric passivation of copper interconnects
US6057583A (en) * 1999-01-06 2000-05-02 Advanced Micro Devices, Inc. Transistor with low resistance metal source and drain vertically displaced from the channel
US6146986A (en) * 1999-01-08 2000-11-14 Lam Research Corporation Lithographic method for creating damascene metallization layers
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6107188A (en) * 1999-08-16 2000-08-22 Taiwan Semiconductor Manufacturing Company Passivation method for copper process
US6110817A (en) * 1999-08-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improvement of electromigration of copper by carbon doping

Also Published As

Publication number Publication date
JP2003521123A (ja) 2003-07-08
KR20020074216A (ko) 2002-09-28
EP1250715A1 (en) 2002-10-23
WO2001056077A1 (en) 2001-08-02
US6303486B1 (en) 2001-10-16

Similar Documents

Publication Publication Date Title
KR100670227B1 (ko) 반도체 디바이스에 구리 배선을 제조하는 방법
KR100708427B1 (ko) 희생 유전층을 이용하여 구리 배선을 제조하는 방법
KR20020070344A (ko) 식각된 낮은 유전 상수 물질들의 다공성을 막기 위한유전체 형성 방법
US6368967B1 (en) Method to control mechanical stress of copper interconnect line using post-plating copper anneal
KR100482180B1 (ko) 반도체 소자 제조방법
US6972254B1 (en) Manufacturing a conformal atomic liner layer in an integrated circuit interconnect
US6989604B1 (en) Conformal barrier liner in an integrated circuit interconnect
KR100860133B1 (ko) 이온 주입에 의한 측벽 밀도의 국부적 증가
EP1330842B1 (en) Low temperature hillock suppression method in integrated circuit interconnects
US6465345B1 (en) Prevention of inter-channel current leakage in semiconductors
WO1991010261A1 (en) Semiconductor interconnect structure utilizing a polyimide insulator
US6518648B1 (en) Superconductor barrier layer for integrated circuit interconnects
US20020127849A1 (en) Method of manufacturing dual damascene structure
US6881665B1 (en) Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist
US6649511B1 (en) Method of manufacturing a seed layer with annealed region for integrated circuit interconnects
JP4232215B2 (ja) 半導体装置の製造方法
KR100688758B1 (ko) 반도체 소자의 금속 배선용 갭필 형성 방법
US6388330B1 (en) Low dielectric constant etch stop layers in integrated circuit interconnects
KR100702802B1 (ko) 반도체 소자의 금속 배선 형성 방법
KR100621228B1 (ko) 반도체 소자의 배선 및 배선연결부 제조방법
KR20040002011A (ko) 반도체 소자의 금속배선 형성방법
KR20020078368A (ko) 무기 저유전막을 이용한 반도체 장치의 제조 방법
KR20050062070A (ko) 반도체 소자의 금속 배선 형성 방법
KR20020092570A (ko) 반도체 장치의 비아홀 형성방법

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20121226

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20131219

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20141231

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20151217

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20161220

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180111

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180111

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000