KR100664857B1 - Analysis Method of Si Defect - Google Patents
Analysis Method of Si Defect Download PDFInfo
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- KR100664857B1 KR100664857B1 KR1020040117676A KR20040117676A KR100664857B1 KR 100664857 B1 KR100664857 B1 KR 100664857B1 KR 1020040117676 A KR1020040117676 A KR 1020040117676A KR 20040117676 A KR20040117676 A KR 20040117676A KR 100664857 B1 KR100664857 B1 KR 100664857B1
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
본 발명은 웨이퍼 결함 분석 방법에 관한 것으로 특히, 확인하고자 하는 실리콘 기판의 표면에서 이물질을 제거하는 제 1공정과; 이물질이 제거된 실리콘 표면을 산화시키는 제 2공정; 및 산화된 실리콘 표면을 에칭하는 제 3공정을 포함하여 실리콘 표면의 결함부를 데코레이션하는 웨이퍼 결함 분석 방법을 제공하면, 웨이퍼의 표면을 산화시킨 후 에칭(etching)하는 과정을 통해 결함 부분을 데코레이션(decoration)시킴으로써 반도체 제작 공정 중 결정성장된 반도체 웨이퍼 표면에서 정상상태인 부분과 결함이 발생한 부분을 손쉽게 구분할 수 있게 된다.The present invention relates to a wafer defect analysis method, and in particular, the first step of removing foreign matter from the surface of the silicon substrate to be confirmed; A second step of oxidizing the silicon surface from which foreign substances have been removed; And a third step of etching the oxidized silicon surface to provide a wafer defect analysis method for decorating a defect portion of the silicon surface, the decoration of the defect portion by etching and etching the surface of the wafer. In this way, it is possible to easily distinguish between a part that is in a steady state and a part where a defect occurs on the surface of the crystal grown semiconductor wafer during the semiconductor manufacturing process.
데코레이션, etching, 산화, 웨이퍼, 결함, 분석Decoration, Etching, Oxidation, Wafers, Defects, Analysis
Description
도 1은 본 발명에 따른 웨이퍼 결함 분석을 위한 결함 데코레이션 과정의 순서 예시도1 is a flowchart illustrating a defect decoration process for wafer defect analysis according to the present invention.
도 2와 도3은 본 발명에 따른 웨이퍼 결함 분석을 위한 결함 데코레이션 과정에 의해 웨이퍼 표면에 결함 데코레이션이 이루어진 상태의 마이크로 사진 예시도Figure 2 and Figure 3 is an illustration of a micro photograph of the defect decoration on the wafer surface by a defect decoration process for wafer defect analysis according to the present invention
본 발명은 웨이퍼 결함 분석 방법에 관한 것으로 특히, 반도체 제작 공정 중 결정성장된 반도체 웨이퍼 표면 결함을 손쉽게 분석하기 위한 웨이퍼의 표면을 산화시킨 후 에칭(etching)하는 과정을 통해 결함 부분을 데코레이션(decoration)시킴으로써 반도체 웨이퍼 표면에서 정상상태인 부분과 결함이 발생한 부분을 구분시키기 위한 웨이퍼 결함 분석 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for analyzing wafer defects, and in particular, to decorate defects by oxidizing and etching the surface of the wafer for easy analysis of surface growth defects of semiconductor wafers grown during the semiconductor fabrication process. The present invention relates to a wafer defect analysis method for distinguishing between normal portions and defective portions on a semiconductor wafer surface.
일반적으로, 반도체소자의 집적도가 증가함에 따라 반도체소자가 구현되는 웨이퍼의 품질이 반도체소자의 수율과 신뢰성에 큰 영향을 끼치고 있다. 반도체 웨이퍼의 품질은 결정성장 및 웨이퍼를 제작하는 소위 웨이퍼링(wafering)의 전 과정 을 통하여 얼마나 결함이 발생하는 가에 좌우되는 것으로서, 이러한 결함은 실리콘 잉곳 성장 중에 발생하는 결정결함(crystal defect)과 외부 오염원에 의한 결함으로 크게 나눌 수 있다.In general, as the degree of integration of semiconductor devices increases, the quality of the wafer on which the semiconductor devices are implemented has a great influence on the yield and reliability of the semiconductor devices. The quality of semiconductor wafers depends on the growth of crystals and how defects occur throughout the so-called wafering process of fabricating the wafers. These defects are associated with crystal defects that occur during silicon ingot growth. It can be largely divided into defects caused by external pollutants.
웨이퍼의 결함 중에서 먼지 등의 외부 오염원(contamination)은 식각 또는 세정공정에 의하여 쉽게 제거되지만, 성장된 단결정내에 존재하는 D-디펙트, 산소석출물, 적층결함, 금속석출물 등의 결정결함(crystal defect)은 주로 단결정 성장과정 중에 발생되는 것으로서 세정공정에 의해서 제거되지 않는다.External contamination such as dust among wafer defects is easily removed by etching or cleaning process, but crystal defects such as D-defect, oxygen precipitate, lamination defect, and metal precipitate present in grown single crystal Is mainly generated during single crystal growth and is not removed by the cleaning process.
특히 이 가운데 반도체 웨이퍼의 표면결함(surface defect)으로서 마이크로피트(micro-pit)로 알려진 COP(Crystal Originated Particle)나 디-디펙트(D-Defect)는 종래의 일반적인 세정공정에 의해 제거되지 않으며, 웨이퍼의 제작과정에서 그 발생을 억제시켜야 한다.In particular, crystal originated particles (COPs) or de-defects (COPs), known as micro-pits, as surface defects of semiconductor wafers, are not removed by conventional cleaning processes. It should be suppressed in the manufacturing process of the wafer.
이러한 COP나 디-디펙트는 반도체 웨이퍼상에 반도체소자를 구현하는 과정에서도 계속 영향을 끼침으로써 반도체소자의 수율이나 신뢰성을 저하시키는 요인이 된다.Such COP or de-defect continues to influence the process of implementing a semiconductor device on a semiconductor wafer, thereby degrading the yield and reliability of the semiconductor device.
따라서 웨이퍼상에 반도체소자를 구현하기 전에 이들 결함의 정확한 분포, 밀도 및 모폴로지를 확인하는 것은 반도체소자의 수율관리 측면에서 매우 중요한 이슈가 되고 있다.Therefore, confirming the precise distribution, density and morphology of these defects before implementing the semiconductor device on the wafer has become a very important issue in terms of yield management of the semiconductor device.
종래에는 베어(bare) 웨이퍼의 표면 결정결함을 분석하기 위하여 주로 레이저 스캐터링 방법을 사용하였다. 즉, SC1(NH4OH:H2O2:H2O = 1:1:8) + HF로 된 세정제 로 베어 웨이퍼를 세정한 후, 레이저 스캐터링 입자계수기(Laser Scattering Particle Counter)를 사용하여 웨이퍼의 표면에 일정한 파장을 갖는 레이저를 주사하여 그 산란된 신호를 감지하여 웨이퍼 표면의 결함을 분석하였다.Conventionally, laser scattering is mainly used to analyze surface crystal defects of bare wafers. That is, after cleaning the bare wafer with a cleaning agent of SC1 (NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 8) + HF, using a laser scattering particle counter (Laser Scattering Particle Counter) A laser having a constant wavelength was scanned on the surface of the wafer to detect the scattered signal to analyze defects on the surface of the wafer.
그러나 상기 종래의 방법에 의하면 다음과 같은 문제점들이 있다.However, the conventional method has the following problems.
첫째, COP 등은 웨이퍼 내의 베이컨시-풍부영역(Vacancy-Rich Area)에만 나타나므로 상기 입자계수기로 얻은 COP 지도에서 베이컨시-풍부영역의 정확한 직경을 결정하여 관리해야하지만, COP 맵핑(Maping)과정에서 파티클이 재발생되기 때문에 카운팅시 이들 재 발생된 파티클도 포함되어 실질적인 COP등의 갯수 및 분포를 정확히 평가할 수 없게 된다는 문제점이 있었다.First, since COP appears only in the vacancy-rich area in the wafer, it is necessary to determine and manage the exact diameter of the vacancy-rich area in the COP map obtained by the particle counter, but the COP mapping process Since particles are regenerated at, the regenerated particles are also included in the counting, so the number and distribution of the actual COP cannot be accurately evaluated.
둘째, 종래의 입자계수기의 결함에 대한 검출한도가 0.12 μm이므로 이 이하의 크기를 갖는 COP는 검출할 수 없다. Second, since the detection limit for defects of the conventional particle counter is 0.12 μm, COP having a size smaller than this cannot be detected.
셋째, COP의 모폴로지를 확인하기 위해서는 결함의 정확한 위치를 알아야하므로 종래에는 입자계수기로 측정된 COP의 위치를 AFM(Atomic Force Microscope)과 좌표관계를 조정하여 분석하는 방법을 사용하였으나, 종래의 방법에 의해 결함의 모폴로지와 크기를 확인해 보면 AFM으로 측정된 COP의 크기가 입자계수기로 측정된 크기에 비해 더 크게 나타난다. 따라서 결함의 정확한 위치 뿐만 아니라 그 크기 및 모폴로지도 정확하지 않다는 문제점이 있었다.Third, in order to confirm the morphology of the COP, the exact position of the defect must be known. Therefore, a conventional method of analyzing the position of the COP measured by the particle counter by adjusting the coordinate relationship with the AFM (Atomic Force Microscope) was used. By checking the morphology and size of defects, the size of COP measured by AFM is larger than that measured by particle counter. Therefore, there was a problem that not only the exact position of the defect but also its size and morphology are not accurate.
따라서 종래에는 상기의 문제점으로 인하여 베어 웨이퍼의 표면 결정결함에 대한 정확한 정보를 알 수 없었기 때문에 후속공정에 의해 제조되는 반도체소자의 수율관리 뿐만 아니라, 원천적으로 베어 웨이퍼 제작시에도 결함의 발생을 억제할 수 있는 효과적인 방법도 알 수 없었다.Therefore, in the related art, since accurate information on the surface crystal defects of bare wafers cannot be known due to the above problems, not only the yield management of semiconductor devices manufactured by the subsequent process but also the generation of defects can be suppressed at the time of bare wafer fabrication. There was no known effective way.
상술한 문제점을 해소하기 위한 본 발명의 목적은 웨이퍼 결함 분석 방법에 관한 것으로 특히, 반도체 제작 공정 중 결정성장된 반도체 웨이퍼 표면 결함을 손쉽게 분석하기 위한 웨이퍼의 표면을 산화시킨 후 에칭(etching)하는 과정을 통해 결함 부분을 데코레이션(decoration)시킴으로써 반도체 웨이퍼 표면에서 정상상태인 부분과 결함이 발생한 부분을 구분시키기 위한 웨이퍼 결함 분석 방법에 관한 것이다.An object of the present invention for solving the above problems is a method of analyzing a wafer defect, in particular, the process of oxidizing and then etching the surface of the wafer for easy analysis of the surface defects of the semiconductor wafer grown in the semiconductor manufacturing process The present invention relates to a wafer defect analysis method for distinguishing between a portion in which a normal state and a portion in which a defect occurs on a surface of a semiconductor wafer by decorating a defect portion through the decoration.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 웨이퍼 결함 분석 방법의 특징은, 확인하고자 하는 실리콘 기판의 표면에서 이물질을 제거하는 제 1공정과; 이물질이 제거된 실리콘 표면을 산화시키는 제 2공정; 및 산화된 실리콘 표면을 에칭하는 제 3공정을 포함하여 실리콘 표면의 결함부를 데코레이션하는 데 있다.Features of the wafer defect analysis method according to the present invention for achieving the above object, the first step of removing foreign matter from the surface of the silicon substrate to be confirmed; A second step of oxidizing the silicon surface from which foreign substances have been removed; And a third process of etching the oxidized silicon surface to decorate the defects on the silicon surface.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 웨이퍼 결함 분석 방법의 부가적인 특징으로, 상기 제 2공정은 H202에 실리콘 기판을 일정한 시간동안 디핑하여 실리콘 표면을 산화시키는 데 있다.As an additional feature of the wafer defect analysis method according to the present invention for achieving the above object, the second step is to oxidize the silicon surface by dipping the silicon substrate in H 2 O 2 for a predetermined time.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 웨이퍼 결함 분석 방법의 부가적인 다른 특징으로, 상기 제 3공정은 임의의 혼합비 a, b, c, d, e를 갖는 aHF + bCH3COOH + cCrO3 + dCu(NO3)2 + eH2O로 혼합되어진 혼합 캐미칼에 실리콘 기 판을 일정한 시간동안 디핑하여 실리콘 표면을 에칭하는 데 있다.In another additional aspect of the wafer defect analysis method according to the present invention for achieving the above object, the third step is aHF + bCH 3 COOH + cCrO 3 having any mixing ratio a, b, c, d, e It is to etch the silicon surface by dipping the silicon substrate for a certain time in the mixed chemical mixed with + dCu (NO 3 ) 2 + eH 2 O.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 웨이퍼 결함 분석 방법의 부가적인 또 다른 특징은, 상기 제 3공정을 통해 산화막을 에칭한 실리콘 기판을 순수(Deionized Water)속에 약 15분 이상 놔두어 세척하는 제 4공정을 더 포함하는 데 있다.An additional feature of the wafer defect analysis method according to the present invention for achieving the above object is to leave the silicon substrate etched oxide film through the third process in the deionized water for about 15 minutes or more The fourth step is to further include.
본 발명의 상술한 목적과 여러 가지 장점은 이 기술 분야에 숙련된 사람들에 의해, 첨부된 도면을 참조하여 후술되는 본 발명의 바람직한 실시 예로부터 더욱 명확하게 될 것이다.The above object and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.
이하, 본 발명의 바람직한 실시 예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 웨이퍼 결함 분석을 위한 결함 데코레이션 과정의 순서 예시도이며, 도 2와 도3은 본 발명에 따른 웨이퍼 결함 분석을 위한 결함 데코레이션 과정에 의해 웨이퍼 표면에 결함 데코레이션이 이루어진 상태의 마이크로 사진 예시도이다.1 is a flowchart illustrating a defect decoration process for wafer defect analysis according to the present invention, and FIGS. 2 and 3 show defect decoration on a wafer surface by a defect decoration process for wafer defect analysis according to the present invention. It is an example of the microphotograph of the state.
본 발명에 따른 웨이퍼 결함 분석을 위한 결함 데코레이션 과정의 순서를 첨부한 도 1을 참조하여 살펴보면, 스텝 S100에서 확인하고자 하는 시편 표면에서 실리콘(Si) 이외의 이물질 또는 막질을 제거한다.Referring to FIG. 1 attached to the procedure of a defect decoration process for wafer defect analysis according to the present invention, foreign matter or film other than silicon (Si) is removed from the surface of the specimen to be checked in step S100.
이후, 스텝 S200에서는 H202에 스텝 S100의 과정을 통해 이물질이 제거되어진 시편을 일정한 시간동안 디핑(dipping)하여 시편의 표면을 산화시키게 된다.Subsequently, in step S200, the surface of the specimen is oxidized by dipping the specimen from which foreign matter is removed in H 2 O 2 through the process of step S100 for a predetermined time.
스텝 S200의 과정을 통해 표면이 산화되어진 시편을 스텝 S300에서 [aHF + bCH3COOH + cCrO3 + dCu(NO3)2 + eH2O]로 혼합되어진 혼합 캐미칼(mixing chemical)에 디핑(dipping)하여 시편의 표면에 형성되어 있는 산화막을 에칭하여 제거하게 된다.Dipping the specimen whose surface is oxidized through the process of step S200 into the mixing chemical mixed with [aHF + bCH 3 COOH + cCrO 3 + dCu (NO 3 ) 2 + eH 2 O] in step S300. The oxide film formed on the surface of the specimen is etched and removed.
이때, 스텝 S200의 과정에서 사용되는 혼합 캐미칼의 혼합식에서 사용되는 변수 a, b, c, d, e는 각 캐미칼(chemical)의 부피 비를 결정하는 상수이다.At this time, the variables a, b, c, d, and e used in the mixing formula of the mixed chemicals used in the process of step S200 are constants for determining the volume ratio of each chemical.
이후, 스텝 S400으로 진행하여 산화막을 에칭한 시편을 순수(Deionized Water)속에 약 15분 이상 놔두어 세척하게 된다.Subsequently, the process proceeds to step S400 where the specimen etched with the oxide film is left in the deionized water for about 15 minutes or longer to be washed.
이후 스텝 S500으로 진행하여 시편의 표면에 결함부에 충분한 데코레이션이 이루어졌는가를 판단하여 충분하지 않다고 판단되면 스텝 S200으로 진행하여 상술한 과정을 반복하게 된다.Subsequently, the process proceeds to step S500 to determine whether sufficient decoration is made on the defect surface on the surface of the specimen, and if it is not enough, the process proceeds to step S200 to repeat the above-described process.
이때, 스텝 S200에서 스텝 S400까지의 과정을 통해 시편의 표면에 결함부는 첨부한 도 2와 도 3에 도시되어 있는 바와 같이 데코레이션되어져 그 윤곽이 명확하게 표현된다.At this time, the defect portion on the surface of the specimen through the process from step S200 to step S400 is decorated as shown in Figs. 2 and 3 attached to the contour is clearly expressed.
이후 스텝 S600에서는 이미지 검출 가능한 관측장비를 통해 데코레이션되어 있는 시편의 표면에 결함부를 관측하여 결함 여부를 측정하게 된다.Subsequently, in step S600, the defect is observed on the surface of the specimen, which is decorated through the image detecting apparatus, and the defect is measured.
이상의 설명에서 본 발명은 특정의 실시 예와 관련하여 도시 및 설명하였지만, 특허청구범위에 의해 나타난 발명의 사상 및 영역으로부터 벗어나지 않는 한도 내에서 다양한 개조 및 변화가 가능하다는 것을 당 업계에서 통상의 지식을 가진 자라면 누구나 쉽게 알 수 있을 것이다.While the invention has been shown and described in connection with specific embodiments thereof, it is well known in the art that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.
이상에서 설명한 바와 같은 본 발명에 따른 웨이퍼 결함 분석 방법을 제공하면, 웨이퍼의 표면을 산화시킨 후 에칭(etching)하는 과정을 통해 결함 부분을 데코레이션(decoration)시킴으로써 반도체 제작 공정 중 결정성장된 반도체 웨이퍼 표면에서 정상상태인 부분과 결함이 발생한 부분을 손쉽게 구분할 수 있게 된다.According to the wafer defect analysis method according to the present invention as described above, the surface of the semiconductor wafer crystal grown during the semiconductor manufacturing process by decorating the defect portion through the process of oxidizing the wafer surface and then etching (etching) It is easy to distinguish between the normal part and the part where the defect occurred.
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