JPH11145088A - Conformity evaluating method of semiconductor wafer polishing process using silicon wafer - Google Patents

Conformity evaluating method of semiconductor wafer polishing process using silicon wafer

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Publication number
JPH11145088A
JPH11145088A JP32210897A JP32210897A JPH11145088A JP H11145088 A JPH11145088 A JP H11145088A JP 32210897 A JP32210897 A JP 32210897A JP 32210897 A JP32210897 A JP 32210897A JP H11145088 A JPH11145088 A JP H11145088A
Authority
JP
Japan
Prior art keywords
cleaning
silicon wafer
wafer
polishing
polishing process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32210897A
Other languages
Japanese (ja)
Other versions
JP3862116B2 (en
Inventor
Hisami Motoura
久実 元浦
Seiichi Shimura
誠一 志村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Electronic Metals Co Ltd filed Critical Komatsu Electronic Metals Co Ltd
Priority to JP32210897A priority Critical patent/JP3862116B2/en
Priority to TW87118458A priority patent/TW396477B/en
Publication of JPH11145088A publication Critical patent/JPH11145088A/en
Application granted granted Critical
Publication of JP3862116B2 publication Critical patent/JP3862116B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a conformity evaluating method of mirror surface polishing process which is used for improving deterioration of oxide film withstand voltage which is to be caused by defect (fine scratch) introduced in a mirror surface polishing process of a silicon wafer. SOLUTION: An evaluating method is provided with a first process S-1 performing HF cleaning to an epitaxial wafer where SC-1 cleaning is performed after mirror surface polishing process is performed or a silicon wafer obtained by an FZ method, a second process S-2 performing the SC-1 cleaning, a third process S-3 measuring LPD(Light Point Defects) existing on the surface of the silicon wafer by using a particle counter, and a fourth process S-4 estimating the quality of the mirror surface polishing process on the basis of the above measured result.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、シリコンウェーハ
を用いた半導体ウェーハの鏡面研磨加工の良否評価方法
に関する。
The present invention relates to a method for evaluating the quality of mirror polishing of a semiconductor wafer using a silicon wafer.

【0002】[0002]

【従来の技術】現在行われているシリコンウェーハの鏡
面研磨加工工程、すなわち化学研磨から鏡面研磨を経て
洗浄に至る工程の良否を、得られたシリコンウェーハに
よって評価する方法の主なものは次の通りである。 (1)化学研磨、鏡面研磨に起因する面だれ等を基準
面、焦点面からの偏差量で評価する平坦度測定。 (2)鏡面研磨工程によって導入される傷で、集光ラン
プ下において目視により確認できる傷を評価する外観検
査。 (3)鏡面研磨工程、洗浄工程を評価するものとして、
OSF検査(鏡面研磨や超音波洗浄など機械的な原因で
生じる傷等の欠陥を酸化熱処理によりOSFとして評
価)、酸化膜耐圧測定(表面の傷、歪み、表面の汚染等
の複合要素を評価)、パーティクル測定(研磨、洗浄中
に付着するごみ等を評価)、ヘイズ測定(ウェーハに集
光ランプを照射し、表面の曇りを評価)やマイクロラフ
ネス測定(研磨、洗浄中のエッチングの影響によるミク
ロなうねりを評価)。 (4)洗浄工程を評価するものとして、表面清浄度の評
価(ウェーハ表面の不純物汚染度を評価)。
2. Description of the Related Art The main method of currently performing a mirror polishing process of a silicon wafer, that is, a process from chemical polishing to cleaning through mirror polishing, using the obtained silicon wafer is as follows. It is on the street. (1) Flatness measurement for evaluating surface droop caused by chemical polishing or mirror polishing based on deviation from a reference plane and a focal plane. (2) Appearance inspection for evaluating scratches introduced in the mirror polishing step, which can be visually confirmed under a condensing lamp. (3) As for evaluating the mirror polishing step and the cleaning step,
OSF inspection (evaluation of defects such as scratches caused by mechanical causes such as mirror polishing or ultrasonic cleaning as OSF by oxidative heat treatment), oxide film breakdown voltage measurement (evaluation of complex elements such as surface scratches, distortion, surface contamination, etc.) , Particle measurement (evaluation of dust adhering during polishing and cleaning), haze measurement (irradiation of condensing lamp on wafer to evaluate surface fogging), and micro roughness measurement (microscopic measurement due to etching during polishing and cleaning) Evaluate the swell). (4) Evaluation of surface cleanliness (evaluation of the degree of impurity contamination on the wafer surface) for evaluating the cleaning step.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、シリコ
ンウェーハの平坦度、清浄度等を測定、評価するだけで
は、酸化膜耐圧の劣化を引き起こす原因となるような鏡
面研磨加工上の欠陥の有無を評価することは不可能であ
る。特に、鏡面研磨工程(研磨後の洗浄を含む)でシリ
コンウェーハに形成された微小なスクラッチは、酸化膜
耐圧を劣化させる一因となる欠陥であることがわかって
いるが、SC−1洗浄を行っても光散乱を起こさないた
め、その検出は極めて困難である。
However, merely measuring and evaluating the flatness, cleanliness, etc. of a silicon wafer can be used to evaluate the presence or absence of a defect in the mirror-polishing process that may cause deterioration of the oxide film breakdown voltage. It is impossible to do. In particular, it is known that minute scratches formed on the silicon wafer in the mirror polishing process (including cleaning after polishing) are defects that contribute to deterioration of the oxide film breakdown voltage. Since light scattering does not occur even if it is performed, its detection is extremely difficult.

【0004】本発明は上記従来の問題点に着目してなさ
れたもので、従来から検出が困難とされている研磨キズ
等の加工欠陥を簡易的に検出して評価する方法を確立
し、酸化膜耐圧の向上に寄与することができるような半
導体ウェーハ、特に、シリコンウェーハに対する研磨加
工の良否評価方法を提供することを目的としている。
The present invention has been made in view of the above-mentioned conventional problems, and has established a method for simply detecting and evaluating processing defects such as polishing flaws, which have been conventionally difficult to detect. It is an object of the present invention to provide a method for evaluating the quality of a polishing process performed on a semiconductor wafer, particularly a silicon wafer, which can contribute to an improvement in film breakdown voltage.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明に係るシリコンウェーハを用いた半導体ウェ
ーハ研磨加工の良否評価方法の第1は、鏡面研磨加工及
び洗浄処理を施したエピタキシャルウェーハまたはFZ
法によるシリコンウェーハを、HFで洗浄する第1工程
と、SC−1洗浄液で洗浄する第2工程と、前記ウェー
ハの表面で検出されるLPD(Light Point Defects) の
個数をパーティクルカウンタで測定する第3工程と、前
記測定結果に基づいて鏡面研磨加工の良否を評価する第
4工程とによって構成されていることを特徴とする。従
来から鏡面研磨加工直後にSC−1洗浄液を用いてシリ
コンウェーハを洗浄しているが、この洗浄のみではシリ
コンウェーハを鏡面研磨加工したときに形成された微小
スクラッチが光散乱しないため、パーティクルカウンタ
で検出することができない。しかし、このシリコンウェ
ーハを上記構成のようにHF洗浄すると表面の酸化物が
除かれ、更にSC−1洗浄することにより前記微小スク
ラッチがエッチングされ拡大してピット化するため、パ
ーティクルカウンタによる検出が可能となる。従って、
パーティクルカウンタでLPDの個数をカウントするこ
とにより加工欠陥の密度を把握し、鏡面研磨加工の良否
を評価することができる。
In order to achieve the above object, a first method of evaluating the quality of a semiconductor wafer polishing process using a silicon wafer according to the present invention is an epitaxial wafer which has been subjected to mirror polishing and cleaning. FZ
A first step of cleaning a silicon wafer by HF, a second step of cleaning with a SC-1 cleaning solution, and a second step of measuring the number of LPDs (Light Point Defects) detected on the surface of the wafer by a particle counter. It is characterized by comprising three steps and a fourth step of evaluating the quality of mirror polishing based on the measurement result. Conventionally, silicon wafers have been cleaned using an SC-1 cleaning solution immediately after mirror polishing, but with this cleaning alone, minute scratches formed when the silicon wafer is mirror-polished do not scatter light, so a particle counter is used. Not detectable. However, when the silicon wafer is subjected to HF cleaning as described above, the oxide on the surface is removed, and the SC-1 cleaning further etches the micro-scratch to enlarge and form pits, so that detection by a particle counter is possible. Becomes Therefore,
By counting the number of LPDs with a particle counter, the density of processing defects can be grasped, and the quality of mirror polishing can be evaluated.

【0006】また、本発明に係るシリコンウェーハを用
いた半導体ウェーハ研磨加工の良否評価方法の第2は、
鏡面研磨加工及び洗浄処理を施したCZ法によるシリコ
ンウェーハに対し、その表面で検出されるLPDの個数
をパーティクルカウンタで測定する第1工程と、前記ウ
ェーハをHFで洗浄する第2工程と、SC−1洗浄液で
洗浄する第3工程と、前記ウェーハの表面で検出される
LPDの個数をパーティクルカウンタで測定する第4工
程と、第1工程及び第4工程で測定したLPD個数の差
を算出する第5工程と、算出したLPD個数の差に基づ
いて鏡面研磨加工の良否を評価する第6工程とによって
構成されていることを特徴とする。CZ法による単結晶
シリコンのインゴットをスライスして得られたシリコン
ウェーハには、単結晶育成の過程で発生したgrown
−in欠陥が含まれており、鏡面研磨後のSC−1洗浄
でCOP(Crystal Originated Particle )によるピッ
トが発生している。そこで本方法は、第1工程でLPD
個数すなわちCOPのピット数をカウントする。このシ
リコンウェーハをHF洗浄すると表面の酸化物が除か
れ、更にSC−1洗浄することにより研磨による微小ス
クラッチがエッチングされて拡大するため、第4工程で
測定したLPD個数は微小スクラッチによるピット数と
COPによるピット数の合計となる。従って、両者の差
を求めることにより微小スクラッチによるピット数が明
らかになり、その密度から鏡面研磨加工の良否を評価す
ることができる。
A second method of evaluating the quality of a semiconductor wafer polishing process using a silicon wafer according to the present invention is as follows.
A first step of measuring, with a particle counter, the number of LPDs detected on the surface of a silicon wafer by the CZ method which has been subjected to mirror polishing and cleaning, a second step of cleaning the wafer with HF, and SC -1 The third step of cleaning with a cleaning liquid, the fourth step of measuring the number of LPDs detected on the surface of the wafer with a particle counter, and the difference between the number of LPDs measured in the first and fourth steps is calculated. The method is characterized by comprising a fifth step and a sixth step of evaluating the quality of mirror polishing based on the calculated difference in the number of LPDs. A silicon wafer obtained by slicing an ingot of single crystal silicon by the CZ method has grown generated during the process of growing a single crystal.
-In defects are included, and pits due to COP (Crystal Originated Particle) are generated in SC-1 cleaning after mirror polishing. Therefore, this method uses LPD in the first step.
The number, that is, the number of pits of the COP is counted. When this silicon wafer is subjected to HF cleaning, oxides on the surface are removed, and further SC-1 cleaning is performed to etch and expand minute scratches due to polishing. Therefore, the number of LPDs measured in the fourth step is equal to the number of pits due to minute scratches. This is the total number of pits by COP. Therefore, the number of pits due to minute scratches is clarified by calculating the difference between them, and the quality of the mirror polishing can be evaluated from the density.

【0007】[0007]

【発明の実施の形態および実施例】次に、本発明に係る
シリコンウェーハを用いた半導体ウェーハ研磨加工の良
否評価方法の実施例について図面を参照して説明する。
エピタキシャルウェーハまたはFZ法によるシリコンウ
ェーハには、CZ法によるシリコンウェーハに見られる
ようなgrown−in欠陥、特にCOPがなく、HF
洗浄とSC−1洗浄とによって鏡面研磨加工に起因する
欠陥のみが検出されるという利点がある。そこで、本評
価方法における評価手順は、図1に示すように、エピタ
キシャルウェーハまたはFZ法によるシリコンウェーハ
に、評価対象とした研磨加工ラインで鏡面研磨加工を施
し、SC−1洗浄を行った上、評価対象シリコンウェー
ハとして使用する。まず、第1工程(S−1)で評価対
象シリコンウェーハを10%のHFに5分以上浸漬して
洗浄し、次いで第2工程(S−2)でSC−1洗浄液で
約10分間洗浄する。前記HFは室温で、およびSC−
1洗浄液は70℃〜80℃の温度とする。その後、第3
工程(S−3)で評価対象シリコンウェーハの表面に発
生しているLPDの個数をパーティクルカウンタでカウ
ントする。この値が鏡面研磨加工に起因する欠陥数であ
る。その後、第4工程(S−4)で前記欠陥数から算出
した欠陥数とあらかじめ定めた許容欠陥数とを比較して
鏡面研磨加工の良否を評価する。許容欠陥数は、要求さ
れるウェーハ品質によって適宜定めても良いが、研磨加
工装置毎の相対比較をするのであれば特定する必要はな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for evaluating the quality of polishing a semiconductor wafer using a silicon wafer according to the present invention will be described with reference to the drawings.
Epitaxial wafers or silicon wafers produced by the FZ method have no grown-in defects, especially COPs, as observed in silicon wafers produced by the CZ method, and
The cleaning and the SC-1 cleaning have an advantage that only defects caused by mirror polishing are detected. Therefore, as shown in FIG. 1, the evaluation procedure in this evaluation method is to perform mirror polishing on an epitaxial wafer or a silicon wafer by the FZ method on a polishing processing line to be evaluated, and perform SC-1 cleaning. Used as a silicon wafer to be evaluated. First, in the first step (S-1), the silicon wafer to be evaluated is immersed in 10% HF for 5 minutes or more to be washed, and then in the second step (S-2), it is washed with the SC-1 cleaning solution for about 10 minutes. . The HF is at room temperature and SC-
One cleaning solution is at a temperature of 70C to 80C. Then the third
In step (S-3), the number of LPDs generated on the surface of the silicon wafer to be evaluated is counted by a particle counter. This value is the number of defects caused by mirror polishing. Then, in a fourth step (S-4), the quality of the mirror polishing is evaluated by comparing the number of defects calculated from the number of defects with a predetermined allowable number of defects. The allowable number of defects may be determined as appropriate depending on the required wafer quality, but need not be specified if a relative comparison is made for each polishing apparatus.

【0008】鏡面研磨加工工程の良否を評価する実験例
として、評価の対象とした研磨加工ラインで直径6イン
チのエピタキシャルウェーハに鏡面研磨加工を施し、本
発明の評価方法を適用してLPDの値すなわち鏡面研磨
加工に起因する欠陥数を求めた。HFの濃度は10%と
し、浸漬時間は5分、30分の2水準とした。また、H
F洗浄後に行うSC−1洗浄の時間は1分、10分の2
水準とした。なお、以下のパーティクルカウンタによる
LPD測定では、0.12μm以上のピットを対象とし
たが、これに拘束されるものではない。
[0008] As an experimental example for evaluating the quality of the mirror polishing process, an epitaxial wafer having a diameter of 6 inches is mirror-polished on a polishing line to be evaluated, and the LPD value is evaluated by applying the evaluation method of the present invention. That is, the number of defects caused by mirror polishing was obtained. The concentration of HF was set to 10%, and the immersion time was set to 5 minutes or 2/30. Also, H
The time of SC-1 cleaning performed after F cleaning is 1 minute, 10 minutes 2
Standard. In the following LPD measurement using a particle counter, pits of 0.12 μm or more were targeted, but the present invention is not limited to this.

【0009】評価対象エピタキシャルウェーハの表面を
パーティクルカウンタで測定し、LPD数を求めた。そ
して、前記LPD数とあらかじめ定めた許容LPD数と
を比較して鏡面研磨加工の良否を評価した。更に、LP
Dが認められた座標位置をSEM(走査型電子顕微
鏡)、AFM(原子間力顕微鏡)で観察した。SEMに
よる観察は加速電圧5kVで行い、その欠陥についてA
FMによる分析を行った。
The surface of the epitaxial wafer to be evaluated was measured with a particle counter, and the number of LPDs was determined. Then, the number of LPDs was compared with a predetermined allowable number of LPDs to evaluate the quality of the mirror polishing. Furthermore, LP
The coordinate position where D was recognized was observed by SEM (scanning electron microscope) and AFM (atomic force microscope). Observation by SEM was performed at an accelerating voltage of 5 kV.
Analysis by FM was performed.

【0010】HF洗浄+SC−1洗浄後にパーティクル
カウンタで検出された0.12μm以上のLPD個数を
図2に示す。なお、HF洗浄のみでは、時間にかかわら
ずLPDは検出されない。HF洗浄時間を5分から30
分に延長するとLPD個数は増加した。また、HF洗浄
時間が同じであってもSC−1洗浄時間を1分から10
分に延長するとLPD個数は増加している。これは、H
F洗浄工程では研磨スクラッチあるいは研磨キズに起因
するピット(以下HFピットという)を形成することは
できるが、LPDとして検出可能なサイズには至らず、
SC−1洗浄工程を経ることによってHFピットがエッ
チングされてLPDサイズが大きくなるからである。な
お、SEM、AFMによる観察範囲はパーティクルカウ
ンタによる観察範囲より著しく小さいが、パーティクル
カウンタで検出されたHFピットをSEM、AFM等で
観察すると、図3に示すように、HFピットの形状がC
OPと異なった、線状をしていることが分かる。
FIG. 2 shows the number of LPDs of not less than 0.12 μm detected by the particle counter after the HF cleaning + SC-1 cleaning. Note that LPD is not detected by HF cleaning alone regardless of time. HF cleaning time from 5 minutes to 30
When extended to minutes, the number of LPDs increased. Further, even if the HF cleaning time is the same, the SC-1 cleaning time is increased from 1 minute to 10 minutes.
When the number of LPDs is extended to minutes, the number of LPDs increases. This is H
In the F cleaning step, pits (hereinafter, referred to as HF pits) caused by polishing scratches or scratches can be formed, but the size does not reach a size that can be detected as LPD.
This is because the HF pits are etched and the LPD size increases through the SC-1 cleaning step. The observation range by the SEM and the AFM is significantly smaller than the observation range by the particle counter. However, when the HF pit detected by the particle counter is observed by the SEM, the AFM, or the like, as shown in FIG.
It can be seen that it has a linear shape different from the OP.

【0011】SEM観察によると、5μmを超える長さ
のHFピットは、HF洗浄時間の長さに関係なくSC−
1洗浄時間を10分とした場合に観察された。このこと
は、HFピットのサイズ(長さ)に対してSC−1洗浄
の影響が支配的であることを示している。すなわち、H
Fピットの密度の決定はHF洗浄時間に依存し、LPD
として検出可能なサイズの決定はSC−1洗浄時間に依
存する。従って、本評価方法においては10%HFによ
る洗浄時間を5分以上30分以下とし、SC−1洗浄を
10分程度行うことが望ましい。
According to SEM observation, HF pits having a length exceeding 5 μm were found to be SC-SC irrespective of the HF cleaning time.
This was observed when one washing time was 10 minutes. This indicates that the influence of SC-1 cleaning is dominant on the size (length) of the HF pit. That is, H
The determination of the density of the F pit depends on the HF cleaning time,
The determination of the size that can be detected as depends on the SC-1 wash time. Therefore, in this evaluation method, it is preferable that the cleaning time with 10% HF is set to 5 minutes or more and 30 minutes or less, and SC-1 cleaning is performed for about 10 minutes.

【0012】シリコンウェーハの鏡面研磨加工ラインの
良否を評価する場合、上記のように評価対象ラインで研
磨したエピタキシャルウェーハを用いず、CZ法による
シリコンウェーハを用いることもできるので、これにつ
いて第2実施例として説明する。CZ法によるシリコン
ウェーハを用いる場合、鏡面研磨加工直後のSC−1洗
浄によって既に検出されてくるCOPの影響を除外する
ため、図4に示すように、鏡面研磨加工に引き続いてS
C−1洗浄を行ったシリコンウェーハに、第1工程(S
−1)でパーティクルカウンタによる1回目のLPD測
定を行う。このときの測定値をLPD1とする。LPD
1に含まれる数字は主としてCOPの個数で、ウェーハ
表面に付着しているパーティクルも僅かではあるが含ま
れている。
When the quality of a mirror polishing line for a silicon wafer is evaluated, it is possible to use a silicon wafer by the CZ method instead of the epitaxial wafer polished on the line to be evaluated as described above. This will be described as an example. In the case of using a silicon wafer by the CZ method, as shown in FIG. 4, in order to exclude the influence of the COP already detected by the SC-1 cleaning immediately after the mirror polishing, as shown in FIG.
C-1 The first step (S
In the step -1), the first LPD measurement by the particle counter is performed. The measured value at this time is defined as LPD1. LPD
The number included in 1 is mainly the number of COPs, and includes a small number of particles adhering to the wafer surface.

【0013】次いで、エピタキシャルウェーハの場合と
同様に、第2工程(S−2)でHFによる洗浄および第
3工程(S−3)でSC−1洗浄液による洗浄を行い、
第4工程(S−4)でパーティクルカウンタによる2回
目のLPD測定を行う。このときの測定値をLPD2と
する。LPD2には、COP等とともに研磨加工工程で
形成されたキズあるいは微小スクラッチに起因するピッ
ト状の欠陥数が含まれている。そして、第5工程(S−
5)でLPD2からLPD1を差し引くと研磨加工に起
因する欠陥数が求められる。その後、第6工程(S−
6)で前記欠陥数とあらかじめ定めた許容欠陥数とを比
較して鏡面研磨加工の良否を評価する。勿論、相対比較
の場合は、許容欠陥数を定める必要はない。
Next, as in the case of the epitaxial wafer, cleaning with HF in the second step (S-2) and cleaning with the SC-1 cleaning liquid in the third step (S-3) are performed.
In a fourth step (S-4), a second LPD measurement is performed by a particle counter. The measured value at this time is LPD2. The LPD 2 includes the number of pit-like defects caused by scratches or minute scratches formed in the polishing process together with the COP and the like. Then, the fifth step (S-
By subtracting LPD1 from LPD2 in 5), the number of defects caused by polishing is obtained. Then, the sixth step (S-
In 6), the quality of the mirror polishing is evaluated by comparing the number of defects with a predetermined allowable number of defects. Of course, in the case of relative comparison, it is not necessary to determine the allowable number of defects.

【0014】図5は、本発明を適用した結果の一例であ
る。研磨加工A、B、及びCのいずれであっても、HF
洗浄+SC−1洗浄を施さねばLPD数は、2×102
個程度の同一値を示したが、HF洗浄+SC−1洗浄を
施すことにより研磨加工装置間の加工差が明らかにな
る。
FIG. 5 shows an example of the result of applying the present invention. In any of the polishing processes A, B and C, HF
If cleaning + SC-1 cleaning is not performed, the number of LPDs is 2 × 10 2
Although about the same value was shown, by performing HF cleaning + SC-1 cleaning, a processing difference between polishing apparatuses becomes clear.

【0015】[0015]

【発明の効果】以上説明したように本発明によれば、従
来から検出が困難とされていた半導体ウェーハ、特に、
シリコンウェーハの鏡面研磨加工に起因する微小欠陥を
簡易的に検出し、その結果に基づいて鏡面研磨加工工程
の良否を評価することができるようになる。そして、評
価結果に基づいて鏡面研磨加工工程の改善を行うことに
より、シリコンウェーハの酸化膜耐圧を向上させること
ができる。
As described above, according to the present invention, a semiconductor wafer which has conventionally been difficult to detect, particularly,
It is possible to easily detect minute defects caused by mirror polishing of a silicon wafer and evaluate the quality of the mirror polishing process based on the result. By improving the mirror polishing process based on the evaluation result, the oxide film breakdown voltage of the silicon wafer can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例の評価手順を示す工程図で
ある。
FIG. 1 is a process chart showing an evaluation procedure of a first embodiment of the present invention.

【図2】検出したLPD個数をHF及びSC−1の洗浄
条件別に示した図である。
FIG. 2 is a diagram showing the number of detected LPDs according to cleaning conditions of HF and SC-1.

【図3】LPDをAFMで観察した画像の一例を示す図
である。
FIG. 3 is a diagram illustrating an example of an image obtained by observing an LPD with an AFM.

【図4】本発明の第2実施例の評価手順を示す工程図で
ある。
FIG. 4 is a process chart showing an evaluation procedure according to a second embodiment of the present invention.

【図5】HF洗浄+SC−1洗浄を施さない場合のとき
と、施した場合のときのLPD数を示す図である。
FIG. 5 is a diagram showing LPD numbers when HF cleaning + SC-1 cleaning is not performed and when HF cleaning + SC-1 cleaning is performed.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 鏡面研磨加工及び洗浄処理を施したエピ
タキシャルウェーハまたはFZ法によるシリコンウェー
ハを、HFで洗浄する第1工程と、SC−1洗浄液で洗
浄する第2工程と、前記ウェーハの表面で検出されるL
PD(Light Point Defects) の個数をパーティクルカウ
ンタで測定する第3工程と、前記測定結果に基づいて鏡
面研磨加工の良否を評価する第4工程とによって構成さ
れていることを特徴とするシリコンウェーハを用いた半
導体ウェーハ研磨加工の良否評価方法。
1. A first step of cleaning an epitaxial wafer or a silicon wafer by the FZ method, which has been subjected to mirror polishing and cleaning processing, with HF, a second step of cleaning with an SC-1 cleaning liquid, L to be detected
A silicon wafer comprising a third step of measuring the number of PDs (Light Point Defects) with a particle counter and a fourth step of evaluating the quality of mirror polishing based on the measurement result. The quality evaluation method of the used semiconductor wafer polishing process.
【請求項2】 鏡面研磨加工及び洗浄処理を施したCZ
法によるシリコンウェーハに対し、その表面で検出され
るLPDの個数をパーティクルカウンタで測定する第1
工程と、前記ウェーハをHFで洗浄する第2工程と、S
C−1洗浄液で洗浄する第3工程と、前記ウェーハの表
面で検出されるLPDの個数をパーティクルカウンタで
測定する第4工程と、第1工程及び第4工程で測定した
LPD個数の差を算出する第5工程と、算出したLPD
個数の差に基づいて鏡面研磨加工の良否を評価する第6
工程とによって構成されていることを特徴とするシリコ
ンウェーハを用いた半導体ウェーハ研磨加工の良否評価
方法。
2. CZ subjected to mirror polishing and cleaning
Measurement of the number of LPDs detected on the surface of a silicon wafer by a particle counter
A second step of cleaning the wafer with HF;
C-1 The third step of cleaning with a cleaning liquid, the fourth step of measuring the number of LPDs detected on the surface of the wafer with a particle counter, and calculating the difference between the number of LPDs measured in the first and fourth steps. And the calculated LPD
The sixth to evaluate the quality of mirror polishing based on the difference in number
And a semiconductor wafer polishing process using a silicon wafer.
JP32210897A 1997-11-07 1997-11-07 Quality evaluation method of semiconductor wafer polishing using silicon wafer Expired - Lifetime JP3862116B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP32210897A JP3862116B2 (en) 1997-11-07 1997-11-07 Quality evaluation method of semiconductor wafer polishing using silicon wafer
TW87118458A TW396477B (en) 1997-11-07 1998-11-05 Conformity evaluating method of semiconductor wafer polishing process using silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32210897A JP3862116B2 (en) 1997-11-07 1997-11-07 Quality evaluation method of semiconductor wafer polishing using silicon wafer

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Publication Number Publication Date
JPH11145088A true JPH11145088A (en) 1999-05-28
JP3862116B2 JP3862116B2 (en) 2006-12-27

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Country Status (2)

Country Link
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Publication number Priority date Publication date Assignee Title
JP2001196339A (en) * 2000-01-11 2001-07-19 Ind Technol Res Inst Method for on-line cleaning after cmp
KR100571571B1 (en) * 2000-09-04 2006-04-14 주식회사 실트론 Defect Evaluation Method of SOH Wafer Using Ultrasonic Microscopy
JP2007150153A (en) * 2005-11-30 2007-06-14 Sumco Corp Manufacturing method of semiconductor substrate and quality evaluation method
US20080057324A1 (en) * 2006-09-06 2008-03-06 Sumco Corporation Epitaxial wafer and method of producing same
US9340900B2 (en) * 2006-09-06 2016-05-17 Sumco Corporation Epitaxial wafer and method of producing same
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