KR100657787B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

In the method of manufacturing a semiconductor device, a space between a buffer oxide layer pattern and a first hard mask layer pattern exposing a semiconductor substrate and a preliminary device isolation layer filling a trench below the patterns are formed. A portion of the first hard mask layer pattern is etched to expose the upper sidewall of the preliminary device isolation layer to convert the first hard mask layer pattern into a second hard mask layer pattern. Line width of the protruding portion of the preliminary isolation layer is etched by etching the upper sidewall of the protruding preliminary isolation layer using a sacrificial layer pattern formed on an upper surface of the preliminary isolation layer protruding on the second hard mask layer pattern as an etching mask. This reduced device isolation film is formed. Accordingly, by increasing the width between the device isolation layers protruding on the substrate, it is possible to reduce voids that may occur in the material film formed between the device isolation layers.

Description

METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

1 to 16 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 110 buffer oxide film

110a: buffer oxide film pattern 120: hard mask film

120a: first hard mask film pattern 120b: second hard mask film pattern

130 trench 140 insulating film for device isolation film

150: preliminary isolation layer 152: first isolation layer

154: second device isolation layer 156: third device isolation layer

160: sacrificial film 160a: sacrificial film pattern

162 tunnel oxide film 170 first polysilicon film

170a: polysilicon film pattern 184: dielectric film

188: second polysilicon film V: void

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device and a method of manufacturing a nonvolatile memory device using the same.

In the manufacturing process of the semiconductor device, an element isolation film is formed in the device isolation region so as to electrically separate each device formed on the semiconductor substrate. Conventionally, the device isolation layer is formed by a local oxidation (LOCOS) process. However, in recent years, as the degree of integration of devices increases, a gate oxide pattern and a hard mask layer pattern exposing the device isolation region are formed on the semiconductor substrate, and the trench is formed by etching the semiconductor substrate of the device isolation region. The device isolation layer is formed by an STI process of filling an insulating material in a trench.

Here, since the trench is narrower from the top to the bottom, the width of the device isolation layer formed by filling the trench is also narrowed toward the bottom. Therefore, the space between the device isolation films is wider from the top to the bottom, unlike the width of the device isolation film.

Therefore, when the floating gate of the nonvolatile memory device is formed by using the device isolation film, the width of the space between the device isolation films is formed to be narrower in the upper part than the lower part, so that the conductive gate floating formed between the device isolation films is formed. There is a problem that voids occur in the film.

Therefore, in order to minimize voids that may occur in the material film formed between the device isolation layers, it is necessary to widen the width of the upper space of the device isolation layer exposed on the substrate.

An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device for widening the width between the device isolation film.

In order to achieve the above object, a method of fabricating a semiconductor device according to an embodiment of the present invention may provide a trench by etching a substrate using a buffer oxide layer pattern and a first hard mask layer pattern sequentially formed on a semiconductor substrate as an etching mask. To form. A space between the buffer oxide layer pattern and the first hard mask layer pattern and a preliminary device isolation layer filling the trench are formed. A portion of the first hard mask layer pattern is etched to expose the upper sidewall of the preliminary device isolation layer, and the first hard mask layer pattern is converted into a second hard mask layer pattern while openings are formed between the preliminary device isolation layers. . A sacrificial layer pattern is formed on an upper surface of the preliminary device isolation layer protruding from the second hard mask layer pattern. The upper sidewall of the protruding preliminary isolation layer is etched using the sacrificial layer pattern as an etching mask to form a first isolation layer having a reduced line width of the protruding portion of the preliminary isolation layer.

In addition, the sacrificial layer pattern and the second hard mask layer pattern are removed to expose the buffer oxide layer pattern. The second device isolation layer may be formed by performing a cleaning process on the substrate to which the buffer oxide layer pattern is exposed, thereby removing the buffer oxide layer pattern and reducing the line width of the protruding portion of the first device isolation layer exposed on the substrate. A tunnel oxide film is formed on the substrate exposed between the second device isolation layers. A first polysilicon film is formed on the tunnel oxide film and the second device isolation film so as to fill the space between the second device isolation film. The first polysilicon layer is polished until the upper surface of the second device isolation layer is exposed to form a polysilicon layer pattern in the space between the second device isolation layers. A portion of the protruding portion of the second device isolation film exposed on the substrate is removed to form a third device isolation film. A dielectric layer is continuously formed on the top and sidewalls of the polysilicon layer pattern and the top surface of the third device isolation layer. A second polysilicon layer is formed on the dielectric layer so as to fill a space between the dielectric layers on the sidewall of the polysilicon layer pattern.

According to one embodiment of the present invention as described above, by increasing the width between the device isolation film protruding on the substrate it can reduce the voids that can be generated in the polysilicon film formed between the device isolation film. Therefore, a non-volatile memory device having excellent electrical characteristics can be manufactured by improving the performance and characteristics of the polysilicon film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 16 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a buffer oxide film 110 and a hard mask film 120 are sequentially formed on a semiconductor substrate 100. Specifically, the buffer oxide film 110 and the hard mask film 120 may be formed by various methods. According to the present embodiment, the buffer oxide film 110 may be a dry oxidation method or a wet oxidation method at a temperature of 750 to 900 ° C. It can be formed by an oxidation method. In this case, the buffer oxide film 110 may have various thicknesses in consideration of the characteristics and the performance of the semiconductor device.

The hard mask layer 120 may be formed using low pressure chemical vapor deposition (LP-CVD). In this case, the thickness of the hard mask layer 120 is a process condition so that the upper portion of the preliminary device isolation layer protrudes higher than the surface of the substrate 100 when the hard mask layer pattern is removed after the formation of the subsequent preliminary device isolation layer. The thickness of the hard mask layer 120 may be determined according to the determination. According to the present embodiment, the hard mask film 120 has a thickness of 2500 to 3200 Å. The hard mask layer 120 may be formed of various insulating materials. Examples of the hard mask film 120 include a silicon nitride film (SiN), a silicon oxynitride film (SiON), and the like.

Meanwhile, the cleaning process may be performed before forming the buffer oxide film 110. The cleaning process is carried out by sequentially using hydrofluoric acid (DHF) and SC-1 (NH 4 OH / H 2 O 2 / H 2 O) solution H 2 O: HF mixed in a ratio of 50: 1 to 100: 1, or NH4F: HF is 4 The mixed solution mixed at 1: 1 to 7: 1 is carried out by sequentially using the BOE (Buffered Oxide Etchant) diluted in H2O at a ratio of 1: 100 to 1: 300 and the SC-1 solution.

Although not shown, a photoresist (not shown) is coated on the hard mask layer 120, and then a photoresist pattern (not shown) is formed by performing an exposure and development process using a photo mask (not shown). Form.

Referring to FIG. 2, the hard mask layer 120 and the buffer oxide layer 110 are sequentially etched using the photoresist pattern as an etching mask. The buffer oxide layer pattern 110a and the first hard mask layer pattern 120a exposing the substrate 100 are sequentially formed on the substrate 100 by the etching process. The stacked structure including the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a may have a slope in which line width increases as the substrate 100 is adjacent to the substrate 100. When the etching process is performed on the hard mask layer 120 and the buffer oxide layer 110, the etching process is performed on the hard mask layer 120 and the buffer oxide layer 110 as the time for performing the etching process elapses. This is because the amount to be reduced. Therefore, the line width of the stacked structure including the buffer oxide film pattern 110a and the first hard mask film pattern 120a is increased, thereby making the width between the stacked structures relatively narrow.

Referring to FIG. 3, a trench 130 is formed in the substrate 100 by etching the substrate 100 exposed by the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a. In this case, in the process of forming the trench 130, an oxidation process may be performed to remove damage generated on the sidewalls and the bottom surface of the trench 130 by the etching process. The oxidation process may be carried out by a dry oxidation method at a temperature of 1000 to 1150 ℃.

Here, the trench 130 has a shape that becomes narrower from the top to the bottom. This is because the amount of etching of the substrate 100 decreases from top to bottom. In this case, the sidewalls of the trench 130 are in contact with the sidewalls of the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a. Thus, the trench 130 and the buffer oxide layer pattern 110a and the first sidewall are in contact with each other. The width between the hard mask film patterns 120a is narrowed as a whole.

Referring to FIG. 4, an upper surface of the first hard mask layer pattern 120a and the space between the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a and the trench 130 are filled. An insulating layer 140 for forming an isolation layer is formed on the sidewalls and the bottom of the trench 130. In this case, the insulating film 140 for the device isolation layer may be gap-filled to prevent voids from occurring in the trench 130. Here, the device isolation layer 140 may be formed by various methods, and according to the present embodiment, the device isolation layer 140 may be formed of an oxide layer using high density plasma (HDP). Can be. Thus, the insulating layer 140 for the device isolation layer may be a silicon oxide (SiO 2) or the like.

Referring to FIG. 5, the insulating layer 140 for the device isolation layer is polished until the top surface of the first hard mask layer pattern is exposed. As a result, a space between the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a and the preliminary isolation layer 150 filling the trench 130 are formed. Examples of the polishing process include a chemical mechanical polishing (CMP) process, an advanced chemical etching (ACE) process, and the like. Here, the line width of the preliminary device isolation layer 150 decreases from top to bottom. This is because the width between the trench 130 and the buffer oxide layer pattern 110a and the first hard mask layer pattern 120a becomes narrower from the top to the bottom.

In addition, after the polishing process, a cleaning process using BOE or HF may be further performed to remove the insulating layer 140 for the device isolation layer that may remain on the exposed upper surface of the first hard mask layer pattern 120a. It can be carried out.

On the other hand, if the upper portion of the first hard mask layer pattern 120a is excessively removed in the polishing process, the height of the preliminary device isolation layer 150 is lowered. This also affects the height of the polysilicon film for floating gate to be formed in a subsequent step. Therefore, the polishing process time is appropriately adjusted so that the height of the preliminary device isolation layer 150 is not lowered.

Referring to FIG. 6, a portion of the first hard mask layer pattern 120a is etched to expose the upper sidewall of the preliminary isolation layer 150. Thus, the first hard mask layer pattern 120a is converted into the second hard mask layer pattern 120b while the opening 145 is formed between the preliminary device isolation layers 150. As a result, a portion of the preliminary device isolation layer 150 protrudes from the second hard mask layer pattern 120b. The etching process for the first hard mask layer pattern 120a is wet etching using an etchant containing phosphoric acid (H 3 PO 4).

Referring to FIG. 7, the second hard mask layer pattern 120b and the protruding portion may be filled to fill a space between the upper sidewalls of the protruding preliminary isolation layer 150 (hereinafter, referred to as an “opening portion 145”). A sacrificial layer 160 is formed of an insulating material on the preliminary device isolation layer 150. In the process of forming the sacrificial layer 160, a void V is generated in the opening 145. This is because the upper portion of the opening 145 is narrower than the lower portion.

As such, since the voids V are formed in the openings 145, the thickness of the sacrificial layer 160 formed in the openings 145 is formed on the upper surface of the protruding preliminary isolation layer 150. The thickness of the sacrificial layer 160 is relatively thin.

The sacrificial layer 160 may be formed of a nitride layer using a high density plasma (HDP). Examples of the sacrificial layer 160 include a silicon nitride layer (SiN), a silicon oxynitride layer (SiON), and the like. In this case, the sacrificial layer 160 may be made of an insulating material having the same etching line ratio as that of the hard mask layer 120 in order to simultaneously remove the second hard mask layer pattern 120b and the subsequent sacrificial layer pattern. .

Referring to FIG. 8, the sacrificial layer 160 is partially etched to expose the voids V. Referring to FIG. Thus, the sacrificial layer 160 formed in the opening 145 is removed and a portion of the sacrificial layer 160 formed on the upper surface of the protruding preliminary isolation layer 150 is etched to form a sacrificial layer pattern 160a. To form. As a result, the upper sidewall of the preliminary device isolation layer 150 may be exposed on the second hard mask layer pattern 120b by exposing the opening 145.

Specifically, the etching process for the sacrificial layer 160 is wet etching using an etchant containing phosphoric acid (H 3 PO 4). In the etching process, the sacrificial layer pattern 160a is formed on the upper surface of the protruding preliminary isolation layer 150. As described above, the sacrificial layer 160 is formed in the opening 145. As the void V is generated, the thickness of the sacrificial layer 160 formed on the upper surface of the protruding preliminary isolation layer 150 is relatively larger than the thickness of the sacrificial layer 160 formed on the opening 145. Since the sacrificial layer 160 formed in the opening 145 is removed, a portion of the sacrificial layer 160 formed on the upper surface of the protruding preliminary isolation layer 150 remains. .

Referring to FIG. 9, the upper sidewall of the protruding preliminary isolation layer 150 is etched using the sacrificial layer pattern 160a as an etch mask. The etching process is performed by a wet etching process. The etchant used in the wet etching process is performed using hydrofluoric acid (DHF) and SC-1 (NH4OH / H2O2 / H2O) solution.

As a result, the first device isolation layer 152 having a reduced line width of the protruding portion of the preliminary device isolation layer 150 is formed. Accordingly, the width between the upper sidewalls of the protruding first device isolation layer 152 becomes relatively wider. Therefore, in the subsequent process, when the polysilicon film for the floating gate is formed in the space between the first device isolation layers, it is possible to prevent the generation of voids unlike in the prior art.

Referring to FIG. 10, the sacrificial layer pattern 160a and the second hard mask layer pattern 120b on the protruding first device isolation layer 152 are etched and removed. As a result, the buffer oxide layer pattern 110a is exposed on the substrate 100.

The sacrificial layer pattern 160a and the second hard mask layer pattern 120b may be formed of an insulating material having the same etching selectivity as the sacrificial layer 160 and the first hard mask layer pattern 120a. Therefore, an etchant (eg, an etchant including phosphoric acid (H 3 PO 4)) used in the sacrificial layer 160 and the first hard mask layer pattern 120a may be simultaneously etched. Therefore, the process time for removing the sacrificial layer pattern 160a and the second hard mask layer pattern 120b can be shortened.

Referring to FIG. 11, a cleaning process is performed on the entire structure in which the buffer oxide layer pattern 110a is exposed. In this case, the substrate 100 is used as an etching barrier film. Here, the cleaning process is performed using HF or BOE solution, and the cleaning process time is adjusted until the protruding portion of the first device isolation layer 152 has a set width. Specifically, the cleaning process is dipping in a container filled with HF or BOE solution and washed with DI water, and then using DI water by dipping the substrate 100 again in a container filled with SC-1 to remove particles. To clean. By the cleaning process, the buffer oxide layer pattern 110a is removed and the top and sidewalls of the protruding portion of the first device isolation layer 152 are etched at the same ratio as the buffer oxide layer pattern 110a. As a result, a second device isolation layer 154 having a reduced line width of the protruding portion of the first device isolation layer 152 exposed on the substrate 100 is formed.

Therefore, the protruding portion of the second device isolation layer 154 is narrow in width. In this case, as the width of the protruding portion of the second device isolation layer 154 is narrowed, the spacing between subsequent floating gates can be further narrowed, thereby improving coupling ratio and integration degree of the floating gate.

Referring to FIG. 12, a tunnel oxide layer 162 is formed on the substrate 100 exposed between the second device isolation layers 154. In this case, the tunnel oxide film 162 is formed by a wet oxidation process at a temperature of 750 to 800 ℃. Thereafter, annealing is performed for 20 to 30 minutes in a nitrogen atmosphere at a temperature of 900 to 910 ° C. to minimize the density of interfacial defects between the tunnel oxide film 162 and the substrate 100.

Referring to FIG. 13, a first polysilicon layer 170 is formed on the second isolation layer 154 and the tunnel oxide layer 162 to fill a space between the second isolation layer 154. Here, the first polysilicon film 170 is used to form a floating gate in the nonvolatile memory device. In detail, the first polysilicon layer 170 may be formed by a low pressure chemical vapor deposition (LP-CVD) method using any one of SiH 4 or Si 2 H 6 and PH 3 gas as a source gas.

Referring to FIG. 14, the first polysilicon layer 170 is polished until the top surface of the second device isolation layer 154 is exposed. As a result, the first polysilicon layer 170 is isolated by the protruding portion of the second isolation layer 154, and the polysilicon layer pattern 170a is formed between the protruding portions of the second isolation layer 154. do. Thus, the polysilicon layer pattern 170a is isolated on the protruding portion of the second isolation layer 154 to form a floating gate of the nonvolatile memory device. Here, chemical mechanical polishing etc. are mentioned as an example of the said grinding | polishing process.

Referring to FIG. 15, a portion of the protruding portion of the second device isolation layer 154 exposed on the substrate 100 is removed to form a third device isolation layer 156. Specifically, the protruding portion of the exposed second device isolation layer 154 is removed by a cleaning process. The cleaning process is carried out using HF or BOE. As a result, the coupling ratio may be further improved by exposing sidewalls of the polysilicon layer pattern 170a to secure the surface area of the floating gate.

Referring to FIG. 16, a dielectric film 184 is continuously formed on an upper surface and a sidewall of the polysilicon layer pattern 170a and an upper surface of the third device isolation layer 156. Next, a second polysilicon film 188 is formed on the dielectric film 184. Here, the second polysilicon film 188 is used to form a control gate in the nonvolatile memory device.

In detail, the dielectric layer 184 may have an ONO structure in which a lower oxide layer (SiO 2), a silicon nitride layer (Si 3 N 4), and an upper oxide layer (SiO 2) are sequentially stacked. In this case, the lower and upper oxide layers may be formed of a hot temperature oxide (HTO) film formed by using DCS (SiH 2 Cl 2) and N 2 O gas having excellent internal pressure and TDDB (Time Dependent Dielectric Breakdown) characteristics as a source gas. The silicon nitride film may be formed by LP-CVD using DCS (SiH 2 Cl 2) and NH 3 gas at a temperature of 650 to 800 ° C. and a low pressure of 1 to 3 Torr. After the dielectric film 184 is formed in the ONO structure, steam anneal may be performed by a wet oxidation method at a temperature of 750 to 800 ° C. in order to improve the interfacial properties between the films. On the other hand, the lower oxide film, silicon nitride film and the upper oxide film is deposited to a thickness corresponding to the device characteristics, each process is performed without a time delay (No time delay) to prevent contamination by natural oxide film or impurities.

Subsequently, although not shown, the third polysilicon layer 188 and the dielectric layer 184 are sequentially patterned to form a control gate of the nonvolatile memory device.

According to a preferred embodiment of the present invention as described above, by increasing the width between the device isolation film exposed on the substrate it can reduce the voids that can be generated in the conductive film for the floating gate formed between the device isolation film. . Therefore, the non-volatile memory device having excellent electrical characteristics can be manufactured by improving the performance and characteristics of the floating silicon polysilicon film.

Although described above with reference to the preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

Forming a trench by etching the substrate using a buffer oxide pattern and a first hard mask layer pattern sequentially formed on a semiconductor substrate as an etching mask; Forming a preliminary isolation layer filling the trench and a space between the buffer oxide layer pattern and the first hard mask layer pattern; A portion of the first hard mask layer pattern is etched to expose the upper sidewall of the preliminary device isolation layer, and the first hard mask layer pattern is converted into a second hard mask layer pattern while openings are formed between the preliminary device isolation layers. step; Forming a sacrificial layer pattern on an upper surface of the preliminary device isolation layer protruding from the second hard mask layer pattern; And Forming a first device isolation layer having a reduced line width of a protruding portion of the preliminary device isolation layer by etching the upper sidewall of the preliminary device isolation layer using the sacrificial layer pattern as an etching mask. Method of manufacturing the device. The method of claim 1, wherein the buffer oxide film pattern and the first hard mask film pattern, Sequentially forming a buffer oxide film and a hard mask film on the substrate; And And etching the portions of the hard mask film and the buffer oxide film sequentially. The method of claim 1, wherein the forming of the preliminary device isolation layer comprises: Forming an insulating film for a device isolation layer on the first hard mask layer pattern to fill the trench and the space between the buffer oxide layer pattern and the first hard mask layer pattern; And And polishing the insulating film for the device isolation film until the upper surface of the first hard mask film pattern is exposed. The method of claim 1, wherein the forming of the sacrificial layer pattern comprises: Forming a sacrificial layer formed on the second hard mask layer pattern and the preliminary device isolation layer to fill the opening and having voids formed in the opening; And And partially etching the sacrificial layer so that the voids are exposed. The method of claim 4, wherein the etching is a wet etching process. The method of claim 1, wherein the first hard mask layer pattern and the sacrificial layer pattern are made of an insulating material having the same etching selectivity. 2. The method of claim 1, wherein the first hard mask film pattern is made of silicon nitride. The method of claim 1, wherein the sacrificial layer pattern is made of silicon nitride. The method of claim 1, wherein after the first device isolation layer is formed, Exposing the buffer oxide layer pattern by removing the sacrificial layer pattern and the second hard mask layer pattern; And Performing a cleaning process on the substrate to which the buffer oxide layer pattern is exposed to form a second device isolation layer having a reduced line width of the protruding portion of the first device isolation layer exposed on the substrate while removing the buffer oxide layer pattern; A method of manufacturing a semiconductor device, further comprising. The method of claim 9, further comprising: forming a tunnel oxide film on the substrate exposed between the second device isolation layers; Forming a first polysilicon film on the tunnel oxide film and the second device isolation film to fill a space between the second device isolation film; Polishing the first polysilicon layer until the top surface of the second isolation layer is exposed to form a polysilicon layer pattern in a space between the second isolation layers; Removing a portion of the protruding portion of the second device isolation film exposed on the substrate to form a third device isolation film; Continuously forming a dielectric film on an upper surface and a sidewall of the polysilicon layer pattern and an upper surface of the third device isolation layer; And forming a second polysilicon film on the dielectric film so as to fill a space between the dielectric films on the sidewalls of the polysilicon film pattern.

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