KR100655810B1 - 메모리를 구비한 반도체 장치 - Google Patents
메모리를 구비한 반도체 장치 Download PDFInfo
- Publication number
- KR100655810B1 KR100655810B1 KR1020010052457A KR20010052457A KR100655810B1 KR 100655810 B1 KR100655810 B1 KR 100655810B1 KR 1020010052457 A KR1020010052457 A KR 1020010052457A KR 20010052457 A KR20010052457 A KR 20010052457A KR 100655810 B1 KR100655810 B1 KR 100655810B1
- Authority
- KR
- South Korea
- Prior art keywords
- precharge
- memory cell
- word lines
- word line
- output
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (7)
- 소정의 모드로 선택되는 복수의 워드선을 시분할로 프리차지하는 것을 특징으로 하는 반도체 장치.
- 소정의 모드로 선택되는 복수의 워드선을 그룹으로 나누고, 그룹마다 행하는 워드선 프리차지를 시분할로 하는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,외부로부터 공급되는 하나의 프리차지 명령으로 어느 하나의 그룹을 선택하여 워드선을 프리차지하는 것을 특징으로 하는 반도체 장치.
- 제2항 또는 제3항에 있어서,동일 그룹의 워드선을 동시에 프리차지하는 것을 특징으로 하는 반도체 장치.
- 복수의 메모리 셀 어레이와,복수의 메모리 셀 어레이의 워드선을 메모리 어레이마다 시분할로 프리차지 하는 프리차지 컨트롤러를 구비하는 것을 특징으로 하는 반도체 장치.
- 제5항에 있어서,상기 프리차지 컨트롤러는 하나의 메모리 셀 어레이를 선택하고, 선택한 메모리 셀 어레이의 워드선을 한번에 프리차지하기 위한 신호를 생성하는 회로를 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항 또는 제2항에 있어서,상기 소정의 모드는 시험 모드인 것을 특징으로 하는 반도체 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000264357A JP2002074991A (ja) | 2000-08-31 | 2000-08-31 | メモリを有する半導体装置 |
JPJP-P-2000-00264357 | 2000-08-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020018107A KR20020018107A (ko) | 2002-03-07 |
KR100655810B1 true KR100655810B1 (ko) | 2006-12-12 |
Family
ID=18751786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010052457A KR100655810B1 (ko) | 2000-08-31 | 2001-08-29 | 메모리를 구비한 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6473347B2 (ko) |
JP (1) | JP2002074991A (ko) |
KR (1) | KR100655810B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998047246A1 (fr) * | 1997-04-17 | 1998-10-22 | Ntt Mobile Communications Network Inc. | Station de base de systeme de communications mobiles |
US6480419B2 (en) * | 2001-02-22 | 2002-11-12 | Samsung Electronics Co., Ltd. | Bit line setup and discharge circuit for programming non-volatile memory |
US7124260B2 (en) * | 2002-08-26 | 2006-10-17 | Micron Technology, Inc. | Modified persistent auto precharge command protocol system and method for memory devices |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH073754B2 (ja) * | 1988-03-08 | 1995-01-18 | 三菱電機株式会社 | 半導体記憶装置 |
KR950014099B1 (ko) * | 1992-06-12 | 1995-11-21 | 가부시기가이샤 도시바 | 반도체 기억장치 |
US5619460A (en) * | 1995-06-07 | 1997-04-08 | International Business Machines Corporation | Method of testing a random access memory |
US5615164A (en) * | 1995-06-07 | 1997-03-25 | International Business Machines Corporation | Latched row decoder for a random access memory |
-
2000
- 2000-08-31 JP JP2000264357A patent/JP2002074991A/ja active Pending
-
2001
- 2001-08-15 US US09/929,354 patent/US6473347B2/en not_active Expired - Lifetime
- 2001-08-29 KR KR1020010052457A patent/KR100655810B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20020018107A (ko) | 2002-03-07 |
JP2002074991A (ja) | 2002-03-15 |
US6473347B2 (en) | 2002-10-29 |
US20020024847A1 (en) | 2002-02-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5325325A (en) | Semiconductor memory device capable of initializing storage data | |
US7502273B2 (en) | Two-port SRAM with a high speed sensing scheme | |
US7675801B2 (en) | Semiconductor memory device and refresh method for the same | |
US6504783B2 (en) | Semiconductor device having early operation high voltage generator and high voltage supplying method therefor | |
US5969995A (en) | Static semiconductor memory device having active mode and sleep mode | |
US5818790A (en) | Method for driving word lines in semiconductor memory device | |
US6510094B2 (en) | Method and apparatus for refreshing semiconductor memory | |
US6631092B2 (en) | Semiconductor memory device capable of imposing large stress on transistor | |
US6195300B1 (en) | CBR refresh control for the redundancy array | |
US7505339B2 (en) | Static semiconductor memory device allowing simultaneous writing of data into a plurality of memory cells | |
KR100368105B1 (ko) | 반도체메모리장치 | |
US6917538B2 (en) | Static semiconductor memory device and method of controlling the same | |
KR100655810B1 (ko) | 메모리를 구비한 반도체 장치 | |
US6469947B2 (en) | Semiconductor memory device having regions with independent word lines alternately selected for refresh operation | |
JP4541385B2 (ja) | 半導体装置 | |
US20240096398A1 (en) | Memory device and precharging method thereof | |
KR100477824B1 (ko) | 반도체 메모리 소자 | |
KR100247648B1 (ko) | 로오 디코더 회로 | |
KR100558569B1 (ko) | 전력소모를 줄이기 위한 에스램 | |
US5578942A (en) | Super VCC detection circuit | |
KR100629693B1 (ko) | 반도체 메모리 소자의 컬럼 리던던시 회로 | |
CN112786090A (zh) | 储存器写入装置及方法 | |
KR20050113303A (ko) | 반도체 메모리 장치의 서브 워드 라인 드라이버 | |
KR20040006112A (ko) | 트윈 셀 구조의 리프레쉬 타입 반도체 메모리 장치 | |
KR20040008015A (ko) | 반도체 메모리 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121121 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131118 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141120 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20151118 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20161123 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20171117 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |