KR100654056B1 - Image sensor and method for manufacturing the same - Google Patents

Abstract

An image sensor is provided to prevent the entire area of a photodiode from being decreased while preventing electrons from being lost through the sidewall of a trench, by forming a P^+ epi layer in an isolated type within a trench so that the P^+ epi layer functions as an isolation layer and an N channel stop layer simultaneously and by forming a second P^- epi layer that surrounds the P^+ epi layer and has the same density as the first P^- epi layer so that a N^- diffusion layer for a photodiode is diffused to the second P^- epi layer. A first epi layer of a first conductivity type is formed on a substrate(110). A second epi layer of the first conductivity type is formed in a predetermined depth in the first epi layer. A third epi layer of the first conductivity type is formed in the first epi layer so as to surround the second epi layer, having a density lower than that of the second epi layer. A first diffusion layer for a photodiode is formed in the first and third epi layers to be aligned with one side of the second epi layer, having a second conductivity type. The third epi layer has the same doping density as the first epi layer.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing a portion of a unit pixel of a CMOS image sensor according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the related art shown in FIG. 1.

3 is a cross-sectional view illustrating a portion of a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10, 110: substrate

111: first P ^- epi layer

12, 112: pad oxide film

13, 113: pad nitride film

14, 114: trench

15, 115: rounding oxide film

117: 2nd P ^- epi layer

118: P ⁺ epi layer

20, 119: gate insulating film

21, 120: gate conductive film

22, 121: gate electrode

23, 123: spacer

125: N ^- diffusion layer

27, 127: P ⁺ diffusion layer

The present invention relates to an image sensor and a method for manufacturing the same, and more particularly, to a complementary metal-oxide-semiconductor (CMOS) image sensor and a method for manufacturing the same.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and a charge coupled device (CCD) is a charge in which individual metal oxide silicon (MOS) capacitors are in close proximity to each other. A carrier is a device in which a carrier is stored and transferred to a capacitor. A CMOS (Complementary Metal-Oxide-Semiconductor) image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. It is a device that adopts switching method that makes MOS transistor as many as (pixel) number and uses it to detect output sequentially.

In general, a unit pixel of a CMOS image sensor includes one photo diode and a plurality of MOS transistors, and the MOS transistors control photo-generated charges focused on the photo diodes PD. Do it. In such a CMOS image sensor, all electrons generated through light incident on a photodiode have to be converted into an electronic signal to have good image characteristics.

However, when the STI (Shallow Trench Isolation) process is applied in forming the isolation layer for defining the active region and the field region in manufacturing the CMOS image sensor, a large amount of defects generated in the sidewall of the isolation layer isolated from the trench ( Defect) consumes some of the electrons generated in the photodiode, reducing the light efficiency of the image sensor.

Accordingly, in order to solve this problem, in the related art, a channel stop layer (CST) is formed on the interface with the sidewall of the device isolation layer to prevent electrons from being lost through the sidewall of the device isolation layer. The problem is that the area of the photodiode is reduced. Therefore, the optical characteristic of the image sensor is lowered.

1 is a cross-sectional view illustrating a portion of a unit pixel of a CMOS image sensor according to the related art. Here, as an example, a photodiode having a PN junction structure will be described.

First, Referring to Figure 1, CMOS image sensor according to the prior art P ^- epitaxial layer isolation film 19, 11 is locally formed within the growth of the P-type semiconductor substrate (10, P_Sub) and a device isolation film (19 N-channel stop layer 17 formed so as to surround the N-channel stop layer 17, an N ^- diffusion layer 25 for photodiode formed on the substrate 10 and aligned on one side of the N-channel stop layer 17, and N ^- diffusion layer (25) P ⁺ diffusion layer 27 formed on the upper surface. The P ⁺ diffusion layer 27 is formed to prevent dark current flowing into the photodiode.

Accordingly, the photodiode of the CMOS image sensor according to the prior art has an area equal to the width W of the N ⁻ diffusion layer 25. As a result, the area loss occurs as much as the width of the N-channel stop layer 17 in the photodiode.

In particular, the device isolation layer 19 is formed by applying an STI process and has an isolated form in the trench.

In addition, the CMOS image sensor according to the related art further includes a gate electrode 22 for a transistor formed on the P ⁻ epi layer 11 exposed to one side of the N ⁻ diffusion layer 25. Here, only the gate electrode of the transfer transistor is shown for convenience of description, and the gate electrode 22 has a structure in which the gate insulating film 20 and the gate conductive film 21 are laminated in the same manner as the gate electrode of a general transistor, and both sides thereof. Spacers 23 are formed in the wall.

2A to 2E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the related art shown in FIG. 1.

First, as shown in FIG. 2A, after epitaxially growing a P ⁻ epitaxial layer 11 on the P ^- type substrate 10, a trench 14 having an STI structure is formed in the P ⁻ epitaxial layer 11. .

For example, P ^- and then in turn deposit the epi layer 11, the pad oxide film 12 and a pad nitride layer (13) to, by performing the STI etch process etching a portion of the pad nitride layer 13 and pad oxide film 12 The trench 14 is formed.

Next, as shown in FIG. 2B, a thermal oxidation process is performed to form a rounding oxide film 15 along the inner surface of the trench 14. This is to cure a defect of the substrate 10 during the STI etching process for forming the trench 14.

Subsequently, an ion implantation process 16 is performed to form the N channel stop layer 17 with a predetermined thickness along the interface between the trench 14 and the P ⁻ epi layer 11.

Subsequently, as shown in FIG. 2C, an HDP (High Density Plasma) oxide film (not shown) for device isolation is deposited to fill the trench 14 (see FIG. 2B).

Subsequently, the pad nitride layer 13 (see FIG. 2B) is removed through a wet etching process using a phosphoric acid solution (H ₃ PO ₄ ), and the pad oxide layer 12 (see FIG. 2B) is removed through a wet etching process using a hydrofluoric acid solution. do.

Subsequently, the HDP oxide film is planarized through a chemical mechanical polishing (CMP) process to form an isolation layer 19 isolated in the trench 14.

Subsequently, as illustrated in FIG. 2D, a plurality of transistor gate electrodes 22 are formed on the P ⁻ epi layer 11 on which the device isolation film 19 is formed so as to be spaced apart from the device isolation film 19 by a predetermined distance. Here, only the gate electrode of the transfer transistor is shown for convenience of description. For example, the gate electrode 22 is formed by sequentially depositing the gate insulating film 20 and the gate conductive film 21 and then etching them.

Subsequently, an insulating film for a spacer is deposited along the stepped portion of the P ⁻ epi layer 11 including the gate electrode 22, followed by dry etching to form spacers 23 on both sidewalls of the gate electrode 22.

Subsequently, as shown in FIG. 2E, a mask process and an ion implantation process are performed to form a photodiode N ^- diffusion layer 25 in the P ^- epi layer 11 between the N channel stop layer 17 and the gate electrode 22. To form.

Subsequently, a mask process and an ion implantation process are performed to form a P ⁺ diffusion layer 27 on the upper surface of the N ⁻ diffusion layer 25.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, while preventing electrons from being lost through the sidewall of the device isolation film having an isolated structure in the trench, while reducing the total area of the photodiode. An object thereof is to provide an image sensor and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a first epitaxial layer of a first conductivity type formed on an upper surface of a substrate, and a second epitaxial layer of the first conductivity type formed at a predetermined depth in the first epitaxial layer. And a third epi layer of the first conductivity type formed at a concentration lower than the second epi layer in the first epi layer to surround the second epi layer, and the first epi layer to be aligned with one side of the second epi layer. An image sensor including a first diffusion layer for a photoconductor of a second conductivity type formed in a first and a third epitaxial layer is provided.

Preferably, the second epitaxial layer is formed to have a doping concentration of at least 10 ¹⁹ atoms / cm 3 or more.

Preferably, the second epilayer has an isolated form in the trench of the STI structure.

Preferably, the third epi layer has the same doping concentration as the first epi layer.

According to another aspect of the present invention, there is provided a substrate on which a first epitaxial layer of a first conductivity type is formed, and etching the first epitaxial layer to a predetermined depth in the first epitaxial layer. Forming a trench, growing a second epitaxial layer of the first conductivity type along an inner surface of the trench, and having a higher concentration than the second epitaxial layer on the second epitaxial layer so that the trench is embedded Growing a third epitaxial layer of the first conductivity type, forming a gate electrode for the transistor on the first epitaxial layer to be spaced apart from the third epitaxial layer, and And forming a first diffusion layer for the photodiode in the first and second epitaxial layers between the three epitaxial layers.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3 is a cross-sectional view illustrating a portion of a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention. Here, as an example, a photodiode having a PN junction structure will be described.

First, referring to FIG. 3, a CMOS image sensor according to an exemplary embodiment of the present invention may include a P ⁻ epi layer 111 (hereinafter, referred to as a first P ⁻ epi layer) formed on a P ^- type semiconductor substrate 110 (P_Sub). , the 1 ^P-epi layer is formed to a predetermined depth in a (111) P ⁺ epitaxial layer 118, and the 1 P so as to surround the P ⁺ epitaxial layer ⁽¹¹⁸⁾ in the epitaxial layer (111) P ⁺ epitaxial layer (118 ) formed at a lower concentration than the P ^- epitaxial layer (117; hereinafter, a 2 ^P-epi layer quot;) and, P ⁺ epitaxial layer 118, the first and the 2 P to be aligned to one side ^of-the epilayer ( N ^- diffusion layer 125 for photodiodes formed in 111 and 117. As a result, a PN junction photodiode having a laminated structure of the first P ^- epitaxial layer 111 / N ^- diffusion layer 125 is formed.

In addition, the N ⁻ diffusion layer 125 further includes a P ⁺ diffusion layer 127 formed on the upper surface. The P ⁺ diffusion layer 127 is formed to prevent dark current flowing into the photodiode, and is preferably formed at a higher concentration than the second P ⁻ epi layer 117.

In particular, the P ⁺ epi layer 118 is formed by injecting B ₂ H ₆ , SiH ₄ and HCl to have a Boron doping concentration of at least 10 ¹⁹ atoms / cm 3 or more.

P ⁺ epi layer 118 has an isolated shape within the trench of the STI structure. Here, the trench in which the P ⁺ epi layer 118 is embedded is formed deeper than the trench 14 formed to form the device isolation layer, as shown in FIG. 2A. This is to improve device isolation characteristics with the P ⁺ epi layer 118.

Here, the second P ⁻ epi layer 117 is formed to have the same boron doping concentration as the first P ⁻ epi layer 111. Therefore, since the photodiode, that is, the N ^- diffusion layer 125 is formed to be diffused to the second P ^- epi layer 117, the total area of the photodiode can be increased.

As described above, conventionally, an N channel stop layer 17 (see FIG. 1) is formed to prevent electrons from being lost through the sidewall of the isolation layer 19 (see FIG. 1) isolated in the STI trench. The total area of the photodiode is reduced due to the formation of the channel stop layer 17.

Accordingly, in the embodiment of the present invention, the P ⁺ epi layer 118 simultaneously performs the functions of the device isolation layer and the N chatty stop layer, and the first P ⁻ epitaxial layer 111 to surround the P ⁺ epi layer 118. The second P ⁻ epitaxial layer 117 is formed at the same concentration as) so that the N ⁻ diffusion layer 125 is diffused to the second P ⁻ epitaxial layer 117.

Through this, the width W ′ of the overall photodiode is equal to the width W ₁ of the second P ⁻ epilayer 117 corresponding to one side of the P ⁺ epilayer 118 to the existing photodiode width W. Has an added value. Thus, the total area of the photodiode can be increased while preventing electrons from being lost through the trench sidewalls.

In addition, the CMOS image sensor according to the embodiment of the present invention further includes a transistor gate electrode 121 formed on the first P ⁻ epi layer 111 exposed to one side of the N ⁻ diffusion layer 125. Here, only the gate electrode of the transfer transistor is shown for convenience of description, and the gate electrode 121 has a structure in which the gate insulating film 119 and the gate conductive film 120 are stacked in the same manner as the gate electrode of the general transistor, and both sides thereof. Spacers 123 are formed in the wall.

Hereinafter, a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4A to 4F.

4A to 4F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention illustrated in FIG. 3, and a photo diode having a PN junction structure will be described as an example, as illustrated in FIG. 3.

First, as shown in FIG. 4A, after epitaxially growing the P ⁻ epitaxial layer 111 on the P ^- type substrate 110 (P_Sub), the P ⁻ epitaxial layer 111 may be applied to the P ⁻ epitaxial layer 111 (hereinafter, referred to as a first step). P ^- forming the trench 114 of the STI structure in the term epitaxial layer).

For example, after the pad oxide film 112 and the pad nitride film 113 are sequentially deposited on the first P ⁻ epi layer 111, a portion of the pad nitride film 113 and the pad oxide film 112 may be removed by performing an STI etching process. It is etched to form the trench 114.

Preferably, during the STI etching process, any one of Cl ₂ , HBr, and F-based etching gases is used to etch more deeply in the depth direction than the width of the trench 114. As a result, the trench 114 is formed deeper by a certain depth h than in the conventional FIG. 1A. This is to deepen the depth of the trench 114 to further improve device isolation characteristics.

Subsequently, as shown in FIG. 4B, a thermal oxidation process is performed to form a rounded oxide film 115 along the inner surface of the trench 114. This is to cure a defect formed in the substrate 110 during the STI etching process for forming the trench 114.

Subsequently, as shown in FIG. 4C, a wet etching process using a hydrofluoric acid solution is performed to remove the rounding oxide film 115 (see FIG. 4B). This is to expose silicon (Si) in the subsequent epitaxy process.

Subsequently, the P ^- epitaxial layer 117 (hereinafter, referred to as a second thickness) has a predetermined thickness along the inner surface of the trench 114 (see FIG. 4B) using a selective epitaxial growth (SEG) process as a first epitaxy process. P ^- epilayer). For example, the 2 P ^- epitaxial layer 117 is formed by implanting B ₂ H _6, SiH ₄ and HCl at a temperature of 700 ~ 1100 ℃. Preferably, the second P ⁻ epi layer 117 is formed to have the same boron concentration as the first P ⁻ epi layer 111.

Subsequently, as shown in FIG. 4D, the second P ⁻ epi layer 117 on the second P ⁻ epi layer 117 so that the trench 114 (see FIG. 4 b) is embedded using the SEG in the second epitaxy process. To grow a higher concentration of P ⁺ epilayer 118). For example, P ⁺ epi layer 118 is formed by injecting B ₂ H ₆ , SiH ₄ and HCl at a temperature of 700 ~ 1100 ℃. Preferably, the P ⁺ epi layer 118 is formed to have a boron concentration of at least 10 ¹⁹ atoms / cm 3 or more.

Here, the P ⁺ epi layer 118 functions as the N isolation layer 19 as well as the device isolation layer 19 illustrated in FIG. 2C. Accordingly, as described above, the ion implantation process for forming the N channel stop layer 17, the HDP oxide deposition process for forming the device isolation layer 19, the CMP process, and the like can be omitted.

Subsequently, as shown in FIG. 4E, the pad nitride layer 113 (refer to FIG. 4D) is removed through a wet etching process using a phosphoric acid solution (H ₃ PO ₄ ), and the pad oxide layer is wetted through a wet etching process using a hydrofluoric acid solution. (112, see FIG. 4D).

Subsequently, the plurality of transistor gate electrodes 121 are formed on the first P ⁻ epi layer 111 to be spaced apart from the second P ⁻ epi layer 117 by a predetermined distance. Here, only the gate electrode of the transfer transistor is shown for convenience of description. For example, the gate electrode 121 is formed by sequentially depositing the gate insulating layer 119 and the gate conductive layer 120, and then dry etching the gate insulating layer 119.

Subsequently, an insulating film for a spacer is deposited along the step of the upper part of the entire structure including the gate electrode 121, and then the dry etching is performed to form spacers 123 on both sidewalls of the gate electrode 121.

Subsequently, as shown in FIG. 4F, a mask process and an ion implantation process are performed to form photodiodes in the first and second P ⁻ epi layers 111 and 117 between the P ⁺ epi layer 118 and the gate electrode 121. N ^- diffusion layer 125 is formed.

In this case, the N ⁻ diffusion layer 125 is formed to diffuse to the second P ⁻ epi layer 117 between the P ⁺ epi layer 118 and the first P ⁻ epi layer 111. Accordingly, the photodiode secures an area increased by the width of the second P ⁻ epi layer 117 between the P ⁺ epi layer 118 and the first P ⁻ epi layer 111. Therefore, the total area of the photodiode can be increased to improve the optical characteristics of the image sensor.

Subsequently, a mask process and an ion implantation process are performed to form a P ⁺ diffusion layer 127 on the top surface of the N ⁻ diffusion layer 125. At this time, the P ⁺ diffusion layer 127 is formed to block the flow of the dark current formed by the light incident to the photodiode from the outside.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the P ⁺ epi layer is formed in an isolated form in the trench, and the first P is formed so as to surround the P ⁺ epi layer by simultaneously performing the functions of the device isolation layer and the N chatty stop layer. ^- the photodiode while preventing the electrons are lost by the trench side wall by making formed diffuses far epitaxial ^layer is diffused claim 2 ^P-N for forming an epi-layer photodiode ^- Part 2 P at the same concentration and epitaxial layer The total area can be prevented from decreasing.

Claims (15)

A first epitaxial layer of a first conductivity type formed on the substrate; A second epitaxial layer of the first conductivity type formed at a predetermined depth in the first epitaxial layer; A third epi layer of the first conductivity type formed in the first epi layer at a lower concentration than the second epi layer to surround the second epi layer; The first diffusion layer for the second conductivity type photodiode formed in the first and third epitaxial layers to be aligned on one side of the second epitaxial layer. Image sensor comprising a. The method of claim 1, And the second epitaxial layer has a doping concentration of at least 10 ¹⁹ atoms / cm 3 or more. The method of claim 2, And the second epitaxial layer has an isolated shape within the trench of the STI structure. The method according to any one of claims 1 to 3, And the third epitaxial layer has the same doping concentration as the first epitaxial layer. The method of claim 4, wherein And a second diffusion layer of the first conductivity type formed on an upper surface of the first diffusion layer for the photodiode. The method of claim 5, The second diffusion layer is formed at a higher concentration than the third epi layer. Providing a substrate having a first epitaxial layer of a first conductivity type; Etching the first epitaxial layer to a predetermined depth to form a trench in the first epitaxial layer; Growing a second epitaxial layer of the first conductivity type along an inner surface of the trench; Growing a third epitaxial layer of the first conductivity type on the second epitaxial layer at a higher concentration than the second epitaxial layer so that the trench is buried; Forming a gate electrode for a transistor on the first epitaxial layer to be spaced apart from the third epitaxial layer by a predetermined distance; And Forming a first diffusion layer for a photodiode in the first and second epitaxial layers between the gate electrode and the third epitaxial layer. Image sensor manufacturing method comprising a. The method of claim 7, wherein And the second epitaxial layer is formed at the same concentration as the first epitaxial layer. The method of claim 8, The second epitaxial layer is formed using a selective epitaxial growth method. The method according to claim 8 or 9, The second epitaxial layer is formed by injecting B ₂ H ₆ , SiH ₄ and HCl at a temperature of 700 ~ 1100 ℃. The method of claim 7, wherein And the third epitaxial layer is formed to have a concentration of at least 10 ¹⁹ atoms / cm 3 or more. The method of claim 11, And the third epitaxial layer is formed using a selective epitaxial growth method. The method according to claim 11 or 12, The third epitaxial layer is formed by injecting B ₂ H ₆ , SiH ₄ and HCl at a temperature of 700 ~ 1100 ℃. The method according to any one of claims 7, 8, 9, 11 and 12, after the trench is formed, Forming a rounding oxide film along an inner surface of the trench to cure a defect in the substrate on which the trench is formed; And Removing the rounding oxide to expose the substrate at the bottom of the trench Image sensor manufacturing method further comprising. The method of claim 14, Removing the rounding oxide film is an image sensor manufacturing method using a hydrofluoric acid solution.

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