KR20070034884A - CMOS image sensor manufacturing method - Google Patents

Abstract

The present invention is to provide a method of manufacturing a CMOS (Complementary Metal Oxide Semiconductor) image sensor that can improve the light focusing efficiency of the photodiode while preventing a dark current. Etching a portion to form a plurality of trenches, forming a liner insulating film to cover the trench, removing the liner insulating film in the pixel region, and forming an inner surface of the trench in the pixel region. Growing a channel stop layer, forming a plurality of device isolation layers filling the trench, forming a gate electrode for a transistor on the substrate on which the device isolation layer is formed, and forming the gate electrode and the channel. Forming a photodiode in said substrate between stop layers; It provides a CMOS image sensor manufacturing method.

CMOS, image sensor, channel stop layer, dark current, light focusing, single crystal silicon.

Description

CMOS image sensor manufacturing method {METHOD FOR MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR}

1 is a cross-sectional view showing a portion of a unit pixel of a CMOS image sensor formed to solve a dark current according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

-Explanation of symbols for the main parts of the drawings-

110 substrate 111 pad oxide film

112: pad nitride film 113a, 113b: trench

115: liner oxide film 116: photosensitive film pattern

118: channel stop layer 120: screen oxide film

122: isolation layer 123: transfer gate electrode

124: spacer 125: photodiode

127: floating diffusion region 128: epi layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS metal image sensor, and more particularly, to a method for forming a channel stop layer of a CMOS image sensor.

The CMOS metal sensor is a device widely used in mobile phones, cameras for personal computers (PCs), and electronic devices. CMOS image sensor is simpler to drive than CCD (Charge Coupled Device), which is used as an image sensor, and it is possible to integrate a signal processing circuit into one chip so that a system on chip (SOC) is possible. Allows the module to be miniaturized.

In addition, since the conventional set-up CMOS technology can be used interchangeably, it has many advantages, such as lowering the manufacturing cost.

One of the most important parts of this CMOS image sensor is the prevention of dark current. In particular, junction leakage due to defects in the depletion region of the photodiode may cause deterioration of image quality and distortion of the CMOS image sensor. That is, photodiodes must generate current by receiving light of different intrinsic wavelengths, and photoelectric defects cause dark current regardless of the presence or absence of light, thereby creating false information.

Typically, photodiodes are formed adjacent to device isolation trenches (herein referred to as STI trenches) due to device construction. Since the STI trench is formed by etching a substrate made of silicon, a number of defects are caused in the trench interface portion, and these defects cause dark current. Therefore, in order to solve the dark current caused by the defect of the trench interface, a protective film surrounding the trench is conventionally formed through an ion implantation process after the trench is formed.

1 is a cross-sectional view showing a portion of a unit pixel of a CMOS image sensor formed to solve a dark current according to the prior art.

Referring to FIG. 1, a device isolation film 12 is locally formed on a high concentration P-type substrate 10 (P-Sub), and a gate on which a transfer transistor gate electrode 15 is formed below the substrate 10. It is formed in a structure including an insulating film 13 and spacers 16 formed on both side walls thereof.

In addition, the P-type (P ⁺ ) epi region 20 and the low concentration of the N-type (N ⁻ ) photodiode 18 are implanted into the substrate 10 aligned with one side of the gate electrode 15. And through a thermal diffusion process. On the other hand, a high concentration N-type (N ⁺ ) floating diffusion region 19 is formed in the substrate 10 aligned on the other side of the gate electrode 15.

In particular, the channel stop layer 11 surrounding the photodiode 18 and the device isolation layer 12 adjacent to the photodiode 18 is thickly formed through a separate ion implantation process after forming the STI trench for forming the device isolation layer 12.

However, when the channel stop layer 11 is formed through a separate ion implantation process as described above, a dark current occurs. That is, in the ion implantation process, ions are implanted into the substrate 10 with a constant kinetic energy, and defects are generated in the substrate 10 by the ions having such kinetic energy. In this case, the generated defect may cause a dark current of the image sensor.

In addition, when the channel stop layer 11 is formed through a separate ion implantation process as described above, it is difficult to surround the STI trenches shallowly during the ion implantation process, and thus the thickness of the channel stop layer 11 becomes very thick. Therefore, the area of the adjacent photodiode 18 is relatively reduced to reduce the light focusing efficiency of the photodiode. This, in turn, degrades the performance and yield of the CMOS image sensor.

The present invention proposed to solve the problems of the prior art as described above, an object of the present invention to provide a CMOS image sensor manufacturing method that can improve the light focusing efficiency of the photodiode while preventing dark current (Dark current).

According to an aspect of the present invention, there is provided a method of forming a plurality of trenches by etching a portion of a substrate having a pixel region and a peripheral region, forming a liner insulating layer to surround the trench, and Removing the liner insulating layer in the pixel region, growing a channel stop layer along the inner surface of the trench in the pixel region, forming a plurality of device isolation layers to fill the trench, and And forming a gate electrode for a transistor on the substrate on which the separator is formed, and forming a photodiode on the substrate between the gate electrode and the channel stop layer.

The present invention described above uses a single crystal silicon layer formed by the silicon epitaxial growth method as a channel stop layer to cover the trenches of the pixel region, thereby forming a channel stop layer without requiring a separate ion implantation process to provide a dark current. Not only can it be effectively prevented, but the light focusing efficiency of the photodiode can be improved.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

2A to 2G are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention. For convenience of description, only the region where the gate for the photodiode and the transfer transistor are to be formed will be described. Hereinafter, 'A' represents a pixel region including a photodiode, and 'B' represents a peripheral region.

First, as illustrated in FIG. 2A, the pad oxide layer 111 and the pad nitride layer 112 are deposited on the substrate 110 on which the pixel region A and the peripheral region B are defined. In this case, the substrate 110 has a structure in which a low concentration P-type epi layer (P ^- epi, not shown) is formed on a high concentration of P-type silicon.

Subsequently, a plurality of trenches 113a and 113b are formed in the substrate 110 by performing a shallow trench isolation (STI) etching process. For example, a mask process and an etching process are performed to form a predetermined photoresist pattern (not shown) on the pad nitride film 112. Next, the pad nitride layer 112 is etched by performing an etching process using a photoresist pattern, and the pad oxide layer 111 and a part of the substrate 110 are etched using the etched pad nitride layer 112 as a mask. As a result, first and second trenches 113a and 113b are formed in the substrate 110 of the pixel region A and the peripheral region B, respectively. Then, the photoresist pattern is removed through a photoresist strip process. The pad oxide layer 111 may be etched using the photoresist pattern.

Subsequently, although not shown in the drawing, an ATC (After Treatment Chamber) process is performed. In the ATC process, a very weak plasma is formed by using CF ₄ gas and O ₂ gas, and thus, the roughness of the substrate 110 in which debris and damage, such as polymer, on the substrate 110 is generated ( to improve roughness.

Subsequently, as illustrated in FIG. 2B, an oxidation process is performed to form a liner oxide film 115 covering the first and second trenches 113a and 113b (see FIG. 2A). In this case, the liner oxide layer 115 is formed to have a thickness of 100 to 400 kV in the exposed substrate 110 due to the formation of the first and second trenches 113a and 113b.

Here, the liner oxide layer 115 is formed using O ₂ gas at a high temperature of 900 ° C. or higher for rounding corner portions of the first and second trenches 113a and 113b and curing of etch damage.

Subsequently, as illustrated in FIG. 2C, a photosensitive film pattern 116 having a structure of opening the first trench 113a (see FIG. 2A) is formed. For example, after the photoresist film (not shown) is applied over the entire structure of FIG. 2B, the photoresist pattern 116 is formed by performing exposure and development processes.

Subsequently, a liner oxide film 115 (see FIG. 2B) surrounding the first trench 113a is removed by performing a cleaning process using a mixed solution of NH ₄ F / H ₂ O ₂ / H ₂ O with BOE (Buffered Oxide Etchant). .

Subsequently, as illustrated in FIG. 2D, the pad oxide layer 111 exposed on the upper portion of the first trench 113a is removed using a diluted HF solution. At the same time, the thickness of the liner oxide film 115 surrounding the second trench 113b (see FIG. 2A) is slightly reduced.

Next, the channel stop layer 118 is formed by growing a single crystal silicon layer using a selective epitaxial growth method (hereinafter, referred to as SEG). Here, SEG uses DCS (SiH ₂ Cl ₂ ) or Si ₂ H ₆ as a silicon source gas and a mixed gas of H ₂ / HCl as a reaction gas. In addition, in forming a single crystal silicon layer using SEG, a thermal process using H ₂ may be performed at a temperature of 900 ° C. or higher for at least 10 seconds, and doping of impurities may be performed. Preferably, the channel stop layer 118 is formed by injecting boron or phosphorus to grow the doped single crystal silicon layer.

At this time, in the case of SEG, since the growth proceeds in the direction of the silicon crystal, stable thickness and doping concentration can be obtained not only at the bottom of the trenches 113a and 113b but also in the lateral direction. As a result, not only the defect of the substrate 110 may be prevented by ion implantation, but also the channel stop layer 118 having a thin thickness and a uniform doping concentration of impurities may be formed. Therefore, it is possible to prevent the area of the subsequent photodiode 125 (see FIG. 2G) from decreasing due to the increase in the thickness of the channel stop layer 118.

On the other hand, the channel stop layer 118 may be formed to a thickness of 10 to 2000Å by allowing the doping concentration of impurities to increase in proportion to the growth thickness of the single crystal silicon layer. For example, from the surface of the first trench 113a (see FIG. 2A) to a thickness of 50 GPa, an impurity, i.e., boron-doped single crystal silicon layer is grown. At a thickness of 50 μs to 150 μs, the single crystal silicon layer was grown with boron concentration of 1E18 to 1E19 (atoms / cm 3), and at 150 to 300 μm thickness of single crystal with boron concentration of 1E19 to 1E21 (atoms / cm 3) The silicon layer is grown. This is to form a single crystalline silicon layer in which impurities are uniformly doped, that is to say defect-free.

Subsequently, as shown in FIG. 2E, an oxidation process is performed to form the screen oxide film 120 on the surface of the channel stop layer 118 where the silicon is exposed. Preferably, the screen oxide film 120 is formed to a thickness of 20 ~ 400Å. This is not only to protect the channel stop layer 118 from plasma damage occurring during subsequent deposition of a high density plasma (HDP) oxide film for device isolation, but also to alleviate stress.

Subsequently, as shown in FIG. 2F, an HDP oxide film is deposited as an insulating film for device isolation so that the first and second trenches 113a and 113b are buried. Then, the device isolation film 122 is formed by planarizing it through a chemical mechanical polishing (CMP) process.

Subsequently, the pad nitride layer 112 (see FIG. 2E) is removed through a wet etching process using phosphoric acid (H ₃ PO ₄ ).

Subsequently, as illustrated in FIG. 2G, the transfer gate electrode 123, the photodiode 125, and the like are formed according to a conventional CMOS image sensor manufacturing process. Specifically, after the transfer gate electrode 123 having the spacers 124 is formed on both side walls of the pad oxide film 111, which also functions as a gate insulating film, the transfer gate electrode is performed by performing a mask process and an ion implantation process. The photodiode 125 is formed on the substrate 110 between the 123 and the channel stop layer 118. For example, an N-diffusion layer is formed. Then, a high concentration N ⁺ floating diffusion region 127 is formed on one side substrate 110 of the transfer gate electrode 123 to be spaced apart from the photodiode 125 by a mask process and an ion implantation process. The P-type epitaxial layer 128 is formed on the top 125. As a result, the photodiode functions as a pin diode of the PNP type (P type substrate 110 / N ^- photo diode 125 / P type epi layer 128).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by using the single crystal silicon layer formed by the silicon epitaxial growth method so as to cover the trench of the pixel region as the channel stop layer, the channel stop layer is not required. It is possible to effectively prevent the dark current by forming a. In addition, since the channel stop layer formed by the silicon epitaxial growth method is thin so that the area of the adjacent photodiode is not reduced, the light focusing efficiency of the photodiode can be improved.

Therefore, the effect that can improve the performance and yield of the image sensor occurs.

Claims (11)

Etching a portion of the substrate having a pixel region and a peripheral region to form a plurality of trenches; Forming a liner insulating film to cover the trench; Removing the liner insulating layer in the pixel area; Growing a channel stop layer along the inner surface of the trench in the pixel region; Forming a plurality of device isolation layers to fill the trenches; Forming a gate electrode for a transistor on the substrate on which the device isolation film is formed; And Forming a photodiode on the substrate between the gate electrode and the channel stop layer CMOS image sensor manufacturing method comprising a. The method of claim 1, The forming of the channel stop layer may include forming a single crystal silicon layer using a selective epitaxial growth method. The method of claim 2, The selective epitaxial growth method is a method of manufacturing a CMOS image sensor using DCS (SiH ₂ Cl ₂ ) or Si ₂ H ₆ as a silicon source gas and a mixed gas of H ₂ / HCl as a reaction gas. The method of claim 2 or 3, And a thermal process using H ₂ for at least 10 seconds at a temperature of at least 900 ° C. when forming the single crystal silicon layer using the selective epitaxial growth method. The method of claim 2 or 3, And doping impurities into the single crystal silicon layer when the single crystal silicon layer is formed using the selective epitaxial growth method. The method of claim 5, And a doping concentration of the impurity is increased in proportion to the growth thickness of the single crystal silicon layer when the impurity is doped into the single crystal silicon layer. The method according to any one of claims 1 to 3, And forming a screen insulating layer on the surface of the channel stop layer after the channel stop layer is formed. The method of claim 1, wherein the forming of the trench comprises: Depositing a pad oxide film and a pad nitride film on the substrate; And Etching the pad nitride layer, and then etching the pad oxide layer and a portion of the substrate using the etched pad nitride layer as a mask CMOS image sensor manufacturing method comprising a. The method according to any one of claims 1 to 3, And the liner insulating layer is formed using O ₂ gas at a temperature of at least 900 ° C. for rounding the upper corner portion of the trench. The method of claim 9, Removing the liner insulating film is a CMOS image sensor manufacturing method performing a cleaning process using a mixture of NH ₄ F / H ₂ O ₂ / H ₂ O. The method of claim 9, After forming the trench, the CMOS image sensor manufacturing method further comprising the step of performing an ATC process.

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