KR20100050331A - Image sensor and fabricating method thereof - Google Patents

Abstract

PURPOSE: An image sensor and a manufacturing method thereof are provided to suppress a crosstalk inside a pixel by forming a deep device isolation region on the lower side of the device isolation pattern. CONSTITUTION: A photo diode is formed on a semiconductor substrate. A device isolation pattern(120) is formed on a semiconductor substrate around the photo diode. A device isolation region(110) is formed on the lower side of the device isolation pattern. The device isolation region includes a p type impurity.

Description

Image sensor and fabrication method thereof

Embodiments relate to an image sensor and a method of manufacturing the same.

Recently, a CMOS (Complementary Metal Oxide Silicon) image sensor has attracted attention as a next generation image sensor for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages, such as a low power consumption, a simple manufacturing process according to a few photoprocess steps, by using CMOS manufacturing technology.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

In the manufacture of CMOS image sensors, image characteristics are an important factor in determining the quality of a product. One of the important issues in determining image characteristics is the problem that light absorbed by photodiodes in a pixel is transferred to other transistors when converted to electrons, resulting in crosstalk. As a result, the leakage current of the photodiode increases and the dark current of the CMOS image sensor increases due to the mistransmitted electrons, thereby degrading the image quality.

Embodiments provide an image sensor and a method of manufacturing the same to form a deep device isolation region under the device isolation pattern to enhance electrical device isolation within the pixel.

The embodiment provides an image sensor and a method of manufacturing the same, in which impurities are deeply injected under the device isolation pattern several times to prevent electrons generated in the photodiode from escaping to another transistor.

The image sensor according to the embodiment includes a semiconductor substrate on which a photodiode is formed, a device isolation pattern formed on the semiconductor substrate around the photodiode, and a device isolation region formed under the device isolation pattern.

According to at least one example embodiment, a method of manufacturing an image sensor includes: forming a trench in a semiconductor substrate, forming impurity implantation regions in at least two different depths under the trench, and annealing the semiconductor substrate to form the impurity implantation regions. Forming diffused device isolation regions connected to each other and forming a device isolation pattern embedded in the trench.

The method of manufacturing an image sensor according to the embodiment may include forming a trench in a semiconductor substrate, forming a device isolation pattern buried in the trench, and forming impurity implantation regions in at least two different depths under the trench. Annealing the semiconductor substrate to form an isolation region in which the impurity implantation regions are diffused and connected to each other, and connected to a P-type impurity implantation region under the semiconductor substrate; and forming a photodiode in the semiconductor substrate. Steps.

The image sensor according to the embodiment forms a deep device isolation region under the device isolation pattern so that electrons of each photodiode cannot be transferred to other transistors in the pixel, thereby suppressing crosstalk in the pixel and improving image quality. Mass-produced image sensor products.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 is a cross-sectional view illustrating an image sensor according to an embodiment.

Image sensors are classified into 3T, 4T, and 5T types according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

As shown in FIG. 1, a P-type epitaxial layer 103 is formed on the P ++ type semiconductor substrate 101. In addition, the device isolation pattern 120 is formed to distinguish the active region from the semiconductor substrate having the active region.

The device isolation pattern 120 may include a trench T in the semiconductor substrate and may be formed of an oxide layer embedded in the trench T.

The gate electrode 153 is formed on the portion of the epi layer 103 via the gate insulating layer 151, and the insulating layer sidewall 155 is formed on both sides of the gate electrode 153.

In addition, an n-type diffusion region 165 and a P0 type diffusion region 163 are formed in the epitaxial layer 103 of the photodiode region PD.

Here, the P0 diffusion region 163 is formed on the n-type diffusion region 165. In addition, the source / drain regions 161 are formed with a high concentration n-type diffusion region n + and a low concentration n-type diffusion region n−.

A device isolation region 110 is formed below the device isolation pattern 120 to be connected to the P ++ type semiconductor substrate 101. The device isolation region 110 is formed by ion implantation of P-type impurities.

In particular, the device isolation region 110 may improve electrical device isolation between photodiodes, thereby forming a boundary between the P0 type diffusion region 163 of the device isolation layer 120 and the photodiode and the device isolation layer 120 and the photo. The dark current generated at the boundary of the n-type diffusion region 165 of the diode can be blocked to suppress crosstalk.

2 is a flowchart illustrating a process of forming an isolation region according to an embodiment, and FIGS. 3 to 8 are cross-sectional views of an image sensor according to the flowchart of FIG. 2.

First, a P ++ type impurity may be implanted into the semiconductor substrate to form a P ++ type semiconductor substrate 101. The P-type epitaxial layer 103 is formed on the P ++ type semiconductor substrate 101.

2 and 3, a pad oxide film 181a and a pad nitride film 183a are sequentially formed on the P-type epitaxial layer 103.

The pad oxide layer 181a may be formed by a CVD process or a thermal oxidation process.

The pad nitride layer 183a may be formed through a CVD process such as low pressure CVD (LPCVD).

The pad oxide layer 181a may also serve as a buffer layer to prevent nitrogen components of the pad nitride layer 120 from penetrating into the semiconductor substrate.

The pad oxide layer 181a and the pad nitride layer 183a are patterned to form a pad oxide layer pattern 181 on the P-type epitaxial layer 103 and a pad nitride layer pattern 183 on the pad oxide layer pattern 181. Form.

The semiconductor substrate is etched using the pad oxide layer pattern 181 and the pad nitride layer pattern 183 as an etch mask to form a predetermined trench T in the P-type epitaxial layer 103 as shown in FIG. 4.

The trench T includes trenches around the photodiode.

2 and 4, an oxide film 105 is formed along the inner wall of the trench T. As shown in FIG. The oxide layer 105 covers the damaged trench T through an etching process and then improves a buried property of the device isolation pattern.

2 and 5, P-type impurities are implanted into the trench T using the pad oxide layer pattern 181 and the pad nitride layer pattern 183 as an ion implantation mask.

The P-type impurity forms an impurity implantation region in the semiconductor substrate at the bottom surface of the trench T.

Such impurity implantation is performed at least twice, and here three times.

The first impurity implantation region 111 is formed near the bottom surface of the trench T. The second impurity implantation region 113 is formed under the first impurity implantation region 111. The third impurity implantation region 115 is formed under the second impurity implantation region 113.

The first to third impurity implantation regions 111, 113, and 115 are stacked in a direction perpendicular to the substrate.

The first to third impurity implantation regions 111, 113, and 115 may be formed using the same P-type impurity, and may be formed using different ion implantation energies.

For example, the first impurity implantation region 111 may form a P-type impurity with an ion implantation energy of 80 to 120 keV, and the second impurity implantation region 113 may form a P-type impurity with an ion implantation energy of 300 to 400 keV. The third impurity implantation region 115 may form a P-type impurity at 600 to 800 keV.

For example, when the boron ion 11B + is respectively implanted with the aforementioned ion implantation energy, the first impurity implantation region 111 is 0.26 to 0.37 μm from the substrate surface, and the second impurity implantation region 113 is the substrate. The third impurity implantation region 115 may be 1.33 to 1.45 μm from the surface of the substrate.

Since the ion implantation energy of each ion implantation region is different in the first to third impurity implantation regions 111, 113, and 115, the first to third impurity implantation regions 111, 113, and 115 are spaced apart from each other. Can be formed.

2 and 6, the device isolation region 110 is formed by annealing the semiconductor substrate into which the impurities are injected.

The annealing process may be carried out at a temperature of 950 ~ 1150 ℃, for 4 hours to 7 hours, in a nitrogen gas atmosphere.

In other words, the first to third impurity implantation regions 111, 113, and 115 are implanted with impurities by annealing, so that P-type impurities are implanted between the trench T and the P ++ type semiconductor substrate 101. The region 11 is formed.

The first to third impurity implantation regions 111, 113, and 115 spaced apart from each other may be diffused through an annealing process to form a P-type device isolation region 110 connected to each other.

The device isolation region 110 may be connected to the bottom surface of the trench T, and may be connected to the P ++ type semiconductor substrate 101 below to surround the photodiode region with a P-type impurity region.

As a result, the device isolation region 110 may improve electrical device isolation between photodiodes, thereby forming a boundary between the device isolation pattern 120 and the photodiode of the P0 type diffusion region 163 and the device isolation pattern 120. By blocking the dark current generated at the boundary of the n-type diffusion region 165 of the photodiode, it is possible to suppress crosstalk.

As shown in FIGS. 2, 7 and 8, a trench filling material is deposited on the entire surface of the structure including the trench T to fill the trench T to fill the pad nitride layer pattern 183. A covering device isolation film 120a is formed.

Here, the device isolation film 120a is deposited by an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method, and a trench filling material filling the trench 111 may use O ₃ -TEOS (tetraetylorthosilicate). Can be.

Subsequently, using the pad nitride layer pattern 183 as an etch stop layer, the device isolation layer 120a is chemically mechanically polished (CMP) and polished until the pad nitride layer pattern 183 is exposed, thereby polishing the device in the trench T. An isolation pattern 120 may be formed.

Thereafter, the pad oxide layer pattern 181 and the pad nitride layer pattern 183 may be removed.

9 is a flowchart illustrating a method of forming a device isolation region according to another exemplary embodiment.

As shown in FIG. 9, a trench is formed in the semiconductor substrate, and the oxide substrate on which the trench is formed is oxidized to form an oxide film along the inner wall of the trench.

An isolation layer is formed on the entire structure including the trench, and the isolation layer is polished to form an isolation pattern formed in the trench.

After the device isolation pattern is formed, P-type impurities are implanted with different ion implantation energies so that a first impurity implantation region, a second impurity implantation region, and a third impurity implantation region are sequentially formed below the device isolation pattern.

Thereafter, the first to third impurity implantation regions are diffused through annealing to form device isolation regions connected to each other.

The device isolation region is formed under the device isolation pattern around the photodiode and is connected to a P ++ type semiconductor substrate. When the light absorbed by the photodiode is converted into electrons, the electrons are prevented from being crossed to another transistor and crosstalk is generated. That is, to form an electrically perfect device isolation region around the photodiode.

As mentioned above, the present invention has been described in detail through specific embodiments, which are intended to specifically describe the present invention, and the method of forming a semiconductor device according to the present invention is not limited thereto. It is apparent that modifications and improvements are possible to those skilled in the art.

1 is a cross-sectional view illustrating an image sensor according to an embodiment.

2 is a flowchart illustrating a process of forming a device isolation region according to an embodiment.

3 to 8 are cross-sectional views of the image sensor according to the flowchart of FIG. 2.

9 is a flowchart illustrating a method of forming a device isolation region according to another exemplary embodiment.

Claims (10)

A semiconductor substrate on which a photodiode is formed; An isolation pattern formed on the semiconductor substrate around the photodiode; And And an element isolation region formed under the element isolation pattern. The method of claim 1, And the device isolation region comprises a p-type impurity. The method of claim 1, And the device isolation region is connected to a P-type impurity implantation region under the photodiode. Forming a trench in the semiconductor substrate; Forming impurity implantation regions in at least two locations having different depths under the trench; Annealing the semiconductor substrate to form the device isolation region in which the impurity implantation regions are diffused to be connected to each other; And Forming a device isolation pattern embedded in the trench. The method of claim 4, wherein After forming the device isolation pattern embedded in the trench, And forming a photodiode on the semiconductor substrate. The method of claim 4, wherein Forming the impurity implantation regions; Forming a first impurity implantation region by implanting P-type impurity at an ion implantation energy of 80 to 120 keV around the trench; Forming a second impurity implantation region by implanting P-type impurity at 300 to 400 keV ion implantation energy under the first impurity implantation region; And And forming a third impurity implantation region by implanting P-type impurity at 600 to 800 keV ion implantation energy under the second impurity implantation region. The method of claim 4, wherein The process of annealing the semiconductor substrate is at a temperature of 950 ~ 1150 ℃, the manufacturing method of the image sensor performed in a nitrogen gas atmosphere. The method of claim 4, wherein In the forming of the device isolation region, And the device isolation region is connected to a P-type impurity implantation region under the semiconductor substrate. Forming a trench in the semiconductor substrate; Forming a device isolation pattern buried in the trench; Forming impurity implantation regions in at least two locations having different depths under the trench; Annealing the semiconductor substrate to form an isolation region in which the impurity implantation regions are diffused and connected to each other and connected to the P-type impurity implantation region under the semiconductor substrate; And And forming a photodiode on the semiconductor substrate. The method of claim 9, Forming the impurity implantation regions; Forming a first impurity implantation region by implanting P-type impurity at an ion implantation energy of 80 to 120 keV around the trench; Forming a second impurity implantation region by implanting P-type impurity at 300 to 400 keV ion implantation energy under the first impurity implantation region; And And forming a third impurity implantation region by implanting P-type impurity at 600 to 800 keV ion implantation energy under the second impurity implantation region.

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