KR101241473B1 - Semiconductor device and method of semiconductor - Google Patents

Abstract

Disclosed are a semiconductor device and a method of manufacturing the same. A method of manufacturing a semiconductor device includes forming a first sub epitaxial layer of a first conductivity type on a substrate of a first conductivity type; Implanting impurities of a first conductivity type into the first sub epitaxial layer to form a first injection region; Forming a second sub epi layer of a first conductivity type on the first sub epi layer; Implanting impurities of a first conductivity type into the second sub epitaxial layer to form a second implantation region; And heat treating the first injection region and the second injection region to form an isolation region.

Description

Semiconductor device and manufacturing method of semiconductor device {SEMICONDUCTOR DEVICE AND METHOD OF SEMICONDUCTOR}

The embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

Recently, CMOS image sensors have attracted attention as next generation image sensors. The CMOS image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as a peripheral circuit to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby outputting each unit pixel by the MOS transistors. It is a device that employs a switching method that detects sequentially. That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

CMOS image sensor has advantages such as low power consumption, simple manufacturing process according to few photo process steps because of CMOS technology. In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into an image sensor chip, the CMOS image sensor has an advantage of miniaturization of a product. Therefore, CMOS image sensors are now widely used in various application areas such as digital still cameras, digital video cameras, and the like.

Embodiments provide a semiconductor device and a method for manufacturing a semiconductor device having high full well capacitor performance and suppressing low illumination noise.

A method of manufacturing a semiconductor device according to an embodiment includes forming a first sub epitaxial layer of a first conductivity type on a substrate of a first conductivity type; Implanting impurities of a first conductivity type into the first sub epitaxial layer to form a first injection region; Forming a second sub epi layer of a first conductivity type on the first sub epi layer; Implanting impurities of a first conductivity type into the second sub epitaxial layer to form a second implantation region; And heat treating the first injection region and the second injection region to form an isolation region.

In an embodiment, a semiconductor device may include a substrate of a first conductivity type; An epitaxial layer of a first conductivity type disposed on the substrate of the first conductivity type; And an isolation region formed in the epitaxial layer, in contact with the substrate of the first conductivity type, and implanted with impurities of the first conductivity type.

In the method of manufacturing a semiconductor device according to the embodiment, a plurality of sub epi layers and a plurality of injection regions may be alternately formed to form an isolation region having a uniform width according to depth.

Accordingly, the photodiode or the like can be effectively separated from other semiconductor devices by the device isolation region having a thin width. Therefore, the manufacturing method of the semiconductor device according to the embodiment may have an improved degree of integration.

In addition, in the method of manufacturing a semiconductor device according to the embodiment, the device isolation region is formed by using an impurity of a conductive type (eg, a first conductive type) such as an epitaxial layer. In this case, as the device isolation region is formed without a shallow trench isolation (STI) structure and an N-channel field stop ion implantation, impurities of a first conductivity type diffuse into a region of a second conductivity type of a photodiode. The phenomenon can be suppressed as much as possible. Therefore, the size of an element such as a photodiode can be maximized.

Accordingly, the method of manufacturing a semiconductor device according to the embodiment can maximize the area of a photodiode or the like and can provide a semiconductor device having improved full well capacitor performance.

In addition, the device isolation region is formed through impurity implantation / diffusion, not an STI process, which is a physical device isolation method. Thus, defects generated in the etching process for forming the STI structure can be reduced. For this reason, the semiconductor device according to the embodiment can significantly suppress low illumination noise.

In addition, the isolation region may be in direct contact with the substrate of the first conductivity type. Therefore, the device isolation region can effectively block noise such as electrical crosstalk introduced from adjacent pixels. That is, the noise may be removed by flowing through the semiconductor substrate through the device isolation region.

1 to 8 are cross-sectional views illustrating a method of manufacturing the image sensor according to the first embodiment.
9 is a circuit diagram showing an image sensor according to the first embodiment.
10 is a diagram illustrating an image sensor according to a first embodiment.
11 to 14 are cross-sectional views illustrating a method of manufacturing the image sensor according to the second embodiment.

In the description of the embodiments, in the case where each substrate, pattern, region or layer is described as being formed "on" or "under" of each substrate, pattern, region or layer, "On" and "under" include both being formed "directly" or "indirectly" through other components. In addition, the upper or lower reference of each component is described with reference to the drawings. In addition, the size of each component in the drawings may be exaggerated for the sake of explanation and does not mean a size actually applied.

1 to 8 are cross-sectional views illustrating a method of manufacturing the image sensor according to the first embodiment. 9 is a circuit diagram showing an image sensor according to the first embodiment. 10 is a diagram illustrating an image sensor according to a first embodiment.

Referring to FIG. 1, a first sub epitaxial layer 210 of a first conductivity type is formed on a semiconductor substrate 100 of a first conductivity type. The semiconductor substrate 100 has a plate shape and is made of silicon. The semiconductor substrate 100 includes a high concentration of impurities of a first conductivity type. For example, the semiconductor substrate 100 may include a high concentration of p-type impurities. Indium, gallium, boron, aluminum, etc. are mentioned as an example of the said p-type impurity.

The first sub epitaxial layer 210 is formed by an epitaxial process. Accordingly, the first sub epi layer 210 may have the same crystal structure as the semiconductor substrate 100. For example, the first sub epitaxial layer 210 may be formed by growing silicon on an upper surface of the semiconductor substrate 100 in the same crystal structure as the semiconductor substrate 100.

The thickness T1 of the first sub epitaxial layer 210 may be about 1.5 μm to about 2 μm.

The first sub epitaxial layer 210 may include impurities of the first conductivity type at a lower concentration than the semiconductor substrate 100. In more detail, the first sub epitaxial layer 210 may include the p-type impurity at a lower concentration than the semiconductor substrate 100.

Referring to FIG. 2, impurities of a first conductivity type are selectively implanted into the first sub epi layer 210 to form a first injection region 310. The first injection region 310 is formed on the first sub epi layer 210. The first injection region 310 may surround the region where the photodiode PD is to be formed when viewed from the top side.

Referring to FIG. 3, after the first injection region 310 is formed, a second sub epi layer 220 is formed on the first sub epi layer 210. The second sub epi layer 220 is formed by an epitaxial process at the same concentration as the first sub epi layer 210. Accordingly, the second sub epi layer 220 may have the same crystal structure as the first sub epi layer 210 and the semiconductor substrate 100. For example, the second sub epi layer 220 may be formed by growing silicon in the same crystal structure as the first sub epi layer 210 and the semiconductor substrate 100.

The thickness T2 of the second sub epitaxial layer 220 may be about 0.5 μm to about 1.5 μm.

Referring to FIG. 4, impurities of a first conductivity type may be selectively injected into the second sub epitaxial layer 220 to form a second injection region 320, and the second injection region 320 may be formed in the second sub epi layer 220. It may be injected at the same concentration as the first injection region 310 or may be injected at a higher concentration. The second injection region 320 may correspond to the first injection region 310. That is, the second injection region 320 may be formed at a position corresponding to the first injection region 310. Therefore, when viewed from the top side, the second injection region 320 may surround the region where the photodiode PD is to be formed.

Referring to FIG. 5, after the second injection region 320 is formed, a third sub epi layer 230 is formed on the second sub epi layer 220. The third sub epi layer 230 is formed by an epitaxial process at the same concentration as the first sub epi layer 210. Accordingly, the third sub epi layer 230 may have the same crystal structure as the second sub epi layer 220. For example, the third sub epi layer 230 may be formed by growing silicon in the same crystal structure as the second sub epi layer 220.

The thickness T3 of the third sub epi layer 230 may be about 0.5 μm to about 1.5 μm.

Referring to FIG. 6, impurities of the first conductivity type are selectively implanted into the third sub epitaxial layer 230 to form a third injection region 330, and the third injection region 330 may be formed of the third conductive epitaxial layer 230. Impurities may be implanted at the same concentration or higher concentration than that of the first injection region 310. The third injection region 330 may correspond to the second injection region 320. That is, the third injection region 330 may be formed at a position corresponding to the second injection region 320. Therefore, when viewed from the top side, the third injection region 330 may surround the region where the photodiode PD is to be formed.

The third injection region 330 may be formed in the middle portion of the third sub epi layer 230.

As described above, in the present exemplary embodiment, the first sub epi layer 210, the second sub epi layer 220, the third sub epi layer 230, the first injection region 310, and the second implantation. It is described that region 320 and the third injection region 330 are formed. However, the present invention is not limited thereto, and one or more sub epi layers and injection regions may be further formed on the third sub epi layer 230. For example, the number of sub epi layers 210, 220, 230... May be three to ten, and the injection regions 310 in each epi layer 210, 220, 230. , 320, 330 ...) may be formed, respectively.

Referring to FIG. 7, the sub epi layers 210, 220, 230... Form one epi layer 200. After the epi layer 200 is formed, the injection regions 310, 320, 330... Are heat treated. For example, the semiconductor substrate 100 on which the epi layer 200 is formed may be heat treated at a temperature of about 600 ° C. to about 850 ° C. for about 30 seconds to 10 minutes.

Accordingly, the second conductivity type impurities implanted into the injection regions 310, 320, 330... Are diffused. Accordingly, the device isolation region 300 is formed in the epi layer 200. The device region DR is defined by the device isolation region 300. The device isolation region 300 surrounds the device region DR.

That is, by the heat treatment process, the injection regions 310, 320, 330... Are expanded and overlap each other to form the device isolation region 300.

As such, the sub epi layers 210, 220, 230... And the injection regions 310, 320, 330... Are alternately formed. Accordingly, the device isolation region 300 may be formed in the epi layer 200 to a desired depth.

Referring to FIG. 8, a first conductive impurity and a second conductive impurity are implanted into the device isolation region 300 at different depths to form a photodiode PD. The first conductivity type impurity is implanted into the epi layer 200 at a shallow depth, and the second conductivity type impurity is formed at a deep depth in the epi layer 200.

That is, the photodiode PD includes a first conductivity type region 410 and a second conductivity type region 420. The first conductivity type region 410 is disposed adjacent to the top surface of the epi layer 200, and the second conductivity type region 420 is disposed below the first conductivity type region 410. .

A plurality of insulating layers and metal wires may be further formed on the epi layer 200. In addition, the image sensor according to the embodiment may further include a plurality of transistors in addition to the photodiode PD.

For example, referring to FIG. 9, the image sensor according to the embodiment may transfer and / or transfer charges stored in the photodiode PD and the photodiode PD to configure one pixel Pi and P. FIG. It may include a transfer transistor Tx, a reset transistor Rx, a select transistor Sx, and an access transistor Ax that controls an output or the like.

The transfer transistor Tx and the reset transistor Rx are connected in series to the photodiode PD. The source of the transfer transistor Tx is connected to the photodiode PD, and the drain 430 of the transfer transistor Tx is connected to the source of the reset transistor Sx. A power supply voltage Vdd is applied to the drain 430 of the reset transistor Sx.

The drain 430 of the transfer transistor Tx serves as a floating diffusion (FD). The floating diffusion layer FD is connected to the gate of the select transistor Sx. The select transistor Sx and the access transistor Ax are connected in series. That is, the source of the select transistor Sx and the drain 430 of the access transistor Ax are connected to each other. The power supply voltage Vdd is applied to the drain 430 of the access transistor Ax and the source of the reset transistor Rx. The drain 430 of the select transistor Sx corresponds to an output terminal Out, and a select signal Row is applied to a gate of the select transistor Sx.

The operation of the pixel P of the image sensor having the above-described structure will be briefly described. First, the reset transistor Rx is turned on to make the potential of the floating diffusion layer FD equal to the power supply voltage Vdd, and then the reset transistor Rx is turned off. Let's do it. This operation is defined as a reset operation.

When external light is incident on the photodiode PD, electron-hole pairs (EHP) are generated in the photodiode PD and signal charges are accumulated in the photodiode PD. Subsequently, as the transfer transistor Tx is turned on, the signal charges accumulated in the photodiode PD are output to the floating diffusion layer FD and stored in the floating diffusion layer FD. Accordingly, the potential of the floating diffusion layer FD is changed in proportion to the charge amount of the charge output from the photodiode PD, thereby changing the potential of the gate of the access transistor Ax. At this time, when the select transistor Sx is turned on by the selection signal Row, data is output to the output terminal Out. After the data is output, the pixel P again performs a reset operation. The pixel P repeats these processes to convert light into an electrical signal and outputs the light.

In addition, as shown in FIG. 10, the device isolation region 300 may surround the photodiode PD. In more detail, the device isolation region 300 may surround only the photodiode PD. Alternatively, the device isolation region 300 may surround not only the photodiode PD but also the transistors.

In addition, unlike FIG. 10, the device isolation region 300 may have a closed loop shape.

In the method of manufacturing the image sensor according to the embodiment, a plurality of sub epi layers 210, 220, 230... And a plurality of injection regions 310, 320, 330. Accordingly, the width of the device isolation region 300 may be uniform depending on the depth. In addition, the device isolation region 300 may be formed to a desired depth in the epi layer 200.

Accordingly, the photodiode PD may be effectively separated from other semiconductor devices by the device isolation region 300 having a thin width. Therefore, the manufacturing method of the image sensor according to the embodiment may have an improved degree of integration as compared to the device isolation layer of the STI structure which is a general device isolation method.

In addition, in the method of manufacturing the image sensor according to the embodiment, the device isolation region 300 having a thin width is formed by using the same conductivity type (eg, the first conductivity type) as the epi layer 200. . Accordingly, the phenomenon in which the impurities of the first conductivity type diffuse into the region 420 of the second conductivity type of the photodiode PD may be suppressed. Therefore, the size of the photodiode PD can be maximized.

In the conventional device isolation method, since the device isolation film is formed by the STI method, additional N-channel field stop ions (first conductivity type) are implanted, so that the first conductivity type impurities are the second conductivity type of the photodiode PD. The diffusion into the region 420 may be allowed, which may cause a loss of the full well capacitor.

However, the method of manufacturing the image sensor according to the embodiment may form the device isolation region 300 to maximize the area of the photodiode PD and provide an image sensor having improved full well coffee sheet performance. Can be.

11 to 14 are cross-sectional views illustrating a method of manufacturing the image sensor according to the second embodiment. In this embodiment, reference is made to the image sensor described above and a method of manufacturing the same. That is, the foregoing description of the image sensor and its manufacturing method may be essentially combined with the description of the present image sensor and its manufacturing method, except for the changed part.

Referring to FIG. 11, a first sub epitaxial layer 210 of a first conductivity type is formed on a semiconductor substrate 100 of a first conductivity type. The thickness T4 of the first sub epi layer 210 may be about 0.5 μm to about 1.5 μm.

The first sub epitaxial layer 211 may be directly formed on an upper surface of the semiconductor substrate 100. That is, the first sub epitaxial layer 211 may be formed by growing silicon on the upper surface of the semiconductor substrate 100 by an epitaxial process.

Thereafter, a first conductivity type impurity is selectively injected into the first sub epitaxial layer 211 to form a first injection region 310. The first injection region 310 is formed in the middle portion of the first sub epi layer 211. The first injection region 310 may surround the region where the photodiode PD is to be formed when viewed from the top side.

Referring to FIG. 12, after the first injection region 310 is formed, a second sub epi layer 220 is formed on the first sub epi layer 211. The second sub epitaxial layer 220 is formed by an epitaxial process. Accordingly, the second sub epi layer 220 may have the same crystal structure as the first sub epi layer 211 and the semiconductor substrate 100. For example, the second sub epi layer 220 may be formed by growing silicon in the same crystal structure as the first sub epi layer 211 and the semiconductor substrate 100.

The thickness T5 of the second sub epi layer 220 may be about 0.5 μm to about 1.5 μm.

Thereafter, a first conductivity type impurity is selectively injected into the second sub epitaxial layer 220 to form a second injection region 320. The second injection region 320 may correspond to the first injection region 310. That is, the second injection region 320 may be formed at a position corresponding to the first injection region 310. Therefore, when viewed from the top side, the second injection region 320 may surround the region where the photodiode PD is to be formed.

Referring to FIG. 13, on the second sub epi layer 220, a third sub epi layer, a third injection region 330, a fourth sub epi layer, a fourth injection region 340, and a fifth The sub epi layer, the fifth injection region 350, the sixth sub epi layer and the sixth injection region 360 are formed.

Referring to FIG. 12, the first to sixth sub epi layers 211, 220... Form an epi layer 201. In addition, the first to sixth injection regions 310... 360 are heat treated, and an isolation region 301 is formed.

The isolation region 301 may be in direct contact with the semiconductor substrate 100. That is, the device isolation region 301 may be in direct contact with the top surface of the semiconductor substrate 100. The device isolation region 301 may pass through the epitaxial layer 201.

Accordingly, the device isolation region 301 may effectively isolate the photodiode PD. That is, the device isolation region 301 may efficiently separate the photodiode PD from an element such as an adjacent photodiode PD.

Accordingly, the device isolation region 301 can effectively block noise such as crosstalk from adjacent devices.

Thus, the image sensor according to the embodiment may have improved sensitivity.

In addition, the features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (13)

Forming a first sub epitaxial layer of a first conductivity type on a substrate of a first conductivity type;
Implanting impurities of a first conductivity type into the first sub epitaxial layer to form a first injection region;
Forming a second sub epi layer of a first conductivity type on the first sub epi layer;
Implanting impurities of a first conductivity type into the second sub epitaxial layer to form a second implantation region; And
Heat treating the first injection region and the second injection region to form an isolation region;
And forming a photodiode positioned within the device region defined by the device isolation region and surrounded by the device isolation region. The method of claim 1, wherein the first injection region and the second injection region are formed at positions corresponding to each other. The method of claim 1, wherein the device isolation region is in direct contact with the substrate of the first conductivity type. The method of claim 1,
After the step of implanting the first conductivity type impurities in the second sub epitaxial layer to form a second injection region,
Forming a third sub epi layer of a first conductivity type on the second sub epi layer; And
And injecting impurities of a first conductivity type into the third sub epitaxial layer to form a third injection region. The method of claim 4, wherein the concentration of the first conductivity type impurities in the second sub epi layer and the third sub epi layer is the same as the concentration of the first conductivity type impurities in the first sub epi layer. The method of claim 1, wherein the concentration of the first conductivity type impurity implanted in the second implantation region is equal to or greater than the concentration of the first conductivity type impurity implanted in the first implantation region. The method of claim 4, wherein in the forming of the device isolation region,
And manufacturing the first injection region, the second injection region, and the third injection region. delete The method of claim 1, wherein the first conductivity type is p-type. A substrate of a first conductivity type;
An epitaxial layer of a first conductivity type disposed on the first conductivity type substrate.
Epi layer of the second conductivity type disposed on the epi layer of the first conductivity type
An epitaxial layer of a third conductivity type disposed on the epitaxial layer of the second conductivity type; And
An isolation region formed in the first to third epitaxial layers, in contact with the substrate of the first conductivity type, and implanted with impurities of the first conductivity type; And
And a photodiode disposed within the device region defined by the device isolation region, wherein the photodiode is surrounded by the device isolation region. delete delete The semiconductor device of claim 10, wherein the first conductivity type is p-type.

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