CN112397539B - Image sensor and method for manufacturing the same - Google Patents
Image sensor and method for manufacturing the same Download PDFInfo
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- CN112397539B CN112397539B CN202011269572.1A CN202011269572A CN112397539B CN 112397539 B CN112397539 B CN 112397539B CN 202011269572 A CN202011269572 A CN 202011269572A CN 112397539 B CN112397539 B CN 112397539B
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- 229910052751 metal Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Abstract
The invention provides an image sensor and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate; etching the substrate to form isolation trenches between adjacent pixel units; performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and ions in the first type well region form PN junctions; the isolation layer fills the isolation trench. The isolation between the pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed by ion implantation, PN junctions are formed in the peripheral substrate of the isolation trenches, carriers generated by defects near the isolation trenches are prevented from freely entering the reading area and the photosensitive area, dark current is reduced, good electrical and optical isolation effects are achieved, the area of the isolation areas is reduced, and the chip area utilization rate of the image sensor is improved.
Description
Technical Field
The invention belongs to the field of image sensors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
The vertical charge transfer image sensor (VPS, vertically charge transferring Pixel Sensors) is a three-dimensional image sensor based on a standard flash memory technology, or a semiconductor image sensor based on a floating gate structure array, namely, pixel units forming the image sensor based on a floating gate (FloatingGate, FG) structure, and continuous detection and imaging of optical signals are realized by converting the intensity of the optical signals sensed by each pixel unit into the quantity of electrons injected onto a floating gate layer of the pixel unit. The pixel has the characteristics of high pixel density, small pixel size and the like, and the working principle is that the voltage generated by photo-generated electrons of the photosensitive region is coupled to the floating gate, so that the threshold voltage of a transistor of the reading region is changed, and the image recognition is realized. In practical applications, vertical charge transfer image sensors have problems of large dark current and optical crosstalk between pixels.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, which can reduce dark current and improve optical crosstalk between pixels of the image sensor.
The invention provides a manufacturing method of an image sensor, which comprises the following steps:
providing a substrate having opposite first and second surfaces; a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate;
etching the substrate to form isolation trenches between adjacent pixel units;
performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and the ions in the first type well region form PN junctions in the peripheral substrate of the isolation trench;
and forming an isolation layer, wherein the isolation layer fills the isolation trench.
Further, in the ion implantation, the ion implantation inclination angle range is: 7-45 degrees.
Further, in the ion implantation, the implantation energy of the ions is in the range of 5keV to 45keV, and the implantation dosage of the ions is in the range of 5×10 14 ions/cm 2 ～1×10 16 ions/cm 2 。
Further, before the etching the substrate to form the isolation trench, the method further comprises:
forming shallow trench isolations which are distributed in the substrate at intervals, wherein the shallow trench isolations extend from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is positioned between adjacent pixel units and/or between the photosensitive area and the reading area.
And forming the isolation groove after forming the shallow groove isolation, wherein the isolation groove penetrates through part of the thickness of the substrate from the first surface along the thickness direction of the substrate and stops on the shallow groove isolation.
Further, in the ion region of the second type implanted into the peripheral substrate of the isolation trench, the ion concentrations of the second type are substantially equal at a position equal from the center line of the isolation trench.
The present invention also provides an image sensor including:
a substrate having opposed first and second surfaces; a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate;
an isolation trench penetrating at least a portion of the thickness of the substrate, the isolation trench being located between adjacent ones of the pixel cells;
an isolation layer filled in the isolation trench;
and the PN junction is formed in the peripheral substrate of the isolation groove, and is formed by the ions of the second type injected into the peripheral substrate of the isolation groove and the ions in the first type well region.
Further, each pixel unit comprises a photosensitive region and a reading region, and the isolation trench is further positioned between the photosensitive region and the reading region.
Further, shallow trench isolations are distributed in the substrate at intervals, and extend from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is positioned between adjacent pixel units and/or between the photosensitive area and the reading area; the isolation trench extends from the first surface into the substrate along the thickness direction of the substrate, and is in isolation communication with the shallow trench.
Further, in the ion region of the second type implanted into the peripheral substrate of the isolation trench, the ion concentrations of the second type are substantially equal at a position equal from the center line of the isolation trench.
Further, a gate dielectric layer, a floating gate layer, a dielectric stack layer and a control gate layer are sequentially laminated on the second surface of the substrate; the part of the floating gate layer right below the photosensitive area is integrally arranged with the part right below the reading area, and the part of the control gate layer right below the photosensitive area is isolated from the part right below the reading area.
Further, ion concentrations of the second type are substantially equal at a position equal from a center line of the isolation trench in implanting the ion region of the second type in the first type well region of the peripheral substrate of the isolation trench.
Further, in a cross section perpendicular to the substrate, the isolation trench has a cross-sectional width of 0.08 to 0.3 μm.
Further, the second type of ions includes N-type P ions, N-type As ions, or P-type B ions;
when the second type of ions is N-type P ions, implanting depth at the periphery of the isolation trench is
When the second type of ions is N-type As ions, implanting depth at the periphery of the isolation trench is
When the second type of ions is P-type B ions, implanting depth at the periphery of the isolation trench is
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an image sensor and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate; etching the substrate to form isolation trenches between adjacent pixel units; performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and the ions in the first type well region form PN junctions in the peripheral substrate of the isolation trench; and forming an isolation layer, wherein the isolation layer fills the isolation trench. The isolation trenches are typically deep and the isolation layer located in the isolation trenches serves as isolation, known as Deep Trench Isolation (DTI). The isolation between the pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed by ion implantation, PN junctions are formed in the peripheral substrate of the isolation trenches, carriers generated by defects near the Deep Trench Isolation (DTI) are prevented from freely entering a reading area and a photosensitive area, good electrical and optical isolation effects are achieved while dark current is reduced, and on the section perpendicular to the substrate, the sectional area of an isolation area formed by the PN junctions in the peripheral substrate of the isolation trenches and the isolation layer in the isolation trenches is smaller than the sectional area of the isolation area formed only by ion implantation, so that effective isolation is achieved, the area of the isolation area is reduced, and the chip area utilization rate of the image sensor is improved.
Drawings
FIG. 1 is a flow chart of a method for fabricating an image sensor according to an embodiment of the invention;
fig. 2 to 5 are schematic views illustrating steps of a method for manufacturing an image sensor according to an embodiment of the invention.
Wherein, the reference numerals are as follows:
10-a substrate; 11-a first type well region; 12-isolation trenches; 13-PN junction; 14-isolating layer; 15-shallow trench isolation; 16-a read zone; 17-a photosensitive region; 21-gate dielectric layer; 22-a floating gate layer; a 23-dielectric stack; 24-a control gate layer; 25-a bonding layer; 26-a second region; 27-a first region; 30-slide wafer.
Detailed Description
The embodiment of the invention provides an image sensor and a manufacturing method thereof. The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.
An embodiment of the present invention provides a method for manufacturing an image sensor, as shown in fig. 1, including:
providing a substrate, wherein a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate;
etching the substrate to form isolation trenches between adjacent pixel units;
performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and the ions in the first type well region form PN junctions in the peripheral substrate of the isolation trench;
and forming an isolation layer, wherein the isolation layer fills the isolation trench.
The following describes an image sensor and a method for manufacturing the same in detail with reference to fig. 2 to 4.
As shown in fig. 2, a substrate 10 is provided, and a plurality of pixel units are distributed on the substrate 10, and the pixel units are located in a first type well region 11 in the substrate 10. Each of the pixel cells includes a photosensitive region 17 and a reading region 16. When light irradiates onto the photosensitive region 17, photo-generated carriers are generated in the photosensitive region 17 and reflected as a potential change on the floating gate layer 22, which, after being coupled to the reading region 16, changes the magnitude of the reading current of the reading region 16, so that the light intensity is read out from the reading region 16.
It should be noted that the boundary of the first type well region 11 is not necessarily the same boundary as the substrate 10, that is, the first type well region 11 may be a certain area in the substrate 10, and the range of the first type well region 11 may not end at the boundary of the substrate 10.
Forming shallow trench isolation 15, the substrate 10 having opposite first surfaces f 1 And a second surface f 2 The shallow trench isolations 15 are spaced apart within the substrate 10, the shallow trench isolations 15 being formed from the second surface f 2 Extending into the substrate 10 along the thickness direction of the substrate 10, the shallow trench isolation 15 is located between adjacent pixel units and/or between the photosensitive region 17 and the reading region 16. The material of the shallow trench isolation 15 is, for example, silicon oxide. Alternatively, ions can be used between the photosensitive region 17 and the reading region 16The implantation mode is used for isolation.
As shown in fig. 3, the substrate 10 is etched to form isolation trenches 12 between adjacent pixel cells. The isolation trench 12 is formed from the first surface f 1 The substrate 10 penetrating a part of the thickness in the thickness direction of the substrate 10 stops on the shallow trench isolation 15. The isolation function is performed in a direction perpendicular to the substrate, and optical crosstalk between pixel units is prevented. After the shallow trench isolation 15 is formed, the isolation trench 12 is formed, and the shallow trench isolation 15 is used as an etching stop structure of the isolation trench 12, so that damage to pixels in the etching process can be prevented. Specifically, the damage of the etching process to the gate dielectric layer 21 can be prevented, so that the integrity of the gate dielectric layer 21 is ensured, and the imaging quality is improved.
As shown in fig. 3 and 4, a second type ion implantation is performed on the periphery substrate 10 of the isolation trench 12, and a PN junction 13 is formed between the second type ion and the ions in the first type well region in the periphery substrate 10 of the isolation trench 12. In an embodiment, the first type well region 11 in the substrate 10, for example, a P-type well region, performs N-type ion implantation on the peripheral substrate 10 of the isolation trench 12 to form a PN junction 13. In another embodiment, the first type well region 11 in the substrate 10, for example, an N type well region, performs P type ion implantation on the peripheral substrate 10 of the isolation trench 12 to form a PN junction 13. That is, the first type well region 11 is a P type well region, and the second type ions are N type ions; the first type well region 11 is an N type well region, and the second type ions are P type ions.
In the ion implantation, the ion implantation inclination angle α ranges from the vertical direction perpendicular to the surface of the substrate 10 to: 7-45 degrees. Exemplary, in the ion implantation, the implantation energy of the ions ranges from 5keV to 45keV, and the implantation dosage of the ions ranges from 5X 10 14 ions/cm 2 ～1×10 16 ions/cm 2 . Ion implantation may be accomplished by moving the ion implantation source horizontally/vertically and/or rotating the wafer.
The implantation energy range of the ions is preferably 10keV,20keV,25keV,30keV,35keV.
The implantation ions are preferably N-type P (phosphorus) ions, and the implantation depth is the following in the periphery of the isolation trench 12(angstrom), preferably +.>
The implanted ions may also preferably be N-type As (arsenic) ions implanted to a depth of about the periphery of the isolation trench 12(angstrom), preferably +.>
The implanted ions may also preferably be P-type B (boron) ions implanted at a depth of the isolation trench 12 around the periphery(angstrom), preferably +.>
Since the ion implantation process is performed after the isolation trench 12 is formed, a better isolation effect can be achieved by using a smaller ion implantation intensity and depth, so that the ion implantation depth in the embodiment can be a significant feature different from the prior art.
Next, an isolation layer 14 is formed, the isolation layer 14 filling the isolation trench 12. The isolation layer 14 includes: metal or silicide, such as tungsten or silicon oxide. The isolation trenches 12 are typically deep and the isolation layer 14 located in the isolation trenches 12 serves as isolation, referred to as deep trench isolation (DTI, deep trench isolation). The isolation layer 14 may be formed using chemical vapor deposition, plasma enhanced chemical vapor deposition, or high density plasma chemical vapor deposition. Specifically, the isolation layer 14 fills the isolation trench 12 and covers the first surface f of the substrate 10 1 Planarizing the spacer layer 14 by a Chemical Mechanical Polishing (CMP) process, preferably, such that the top surface of the spacer layer 14 and the first surface f of the substrate 10 1 Flush.
In the manufacturing method of the image sensor of the embodiment, isolation between pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed by ion implantation, PN junctions are formed in the peripheral substrate of the isolation trenches, carriers generated by defects near the Deep Trench Isolation (DTI) are prevented from freely entering a reading area and a photosensitive area, dark current is reduced, good electrical and optical isolation effects are achieved, and on a section perpendicular to the substrate, the sectional area of an isolation area formed by the PN junctions in the peripheral substrate of the isolation trenches and isolation layers in the isolation trenches is smaller than the sectional area of the isolation area formed by ion implantation alone, so that effective isolation is achieved, the area of the isolation area is reduced, and the chip area utilization rate of the image sensor is improved.
Compared with the method for manufacturing the image sensor by only forming the isolation region through ion implantation, in the method for manufacturing the image sensor of the embodiment, isolation between the pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed through ion implantation, the ion implantation of the embodiment requires smaller energy, the area of the PN junction formed around the substrate of the isolation trench can be changed through adjusting the ion implantation angle and the energy, and the isolation layer is filled in the isolation trench after ion implantation is finished, so that good optical isolation between pixels is achieved. In addition, in this embodiment, the PN junction is formed with the well region of the pixel by performing ion implantation on the sidewall of the isolation trench 12, so that the original structure of the pixel is utilized, and the process is simplified.
As shown in fig. 4, the present invention further provides an image sensor, including:
a substrate 10, the substrate 10 having opposing first and second surfaces; a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region 11 in the substrate;
an isolation trench 12, the isolation trench 12 penetrating at least a part of the thickness of the substrate 10, the isolation trench 12 being located between adjacent pixel cells;
an isolation layer 14, the isolation layer 14 being filled in the isolation trench 12;
a PN junction 13, the PN junction 13 is formed in the peripheral substrate 10 of the isolation trench 12.
Specifically, each of the pixel units includes a photosensitive region 17 and a reading region 16. The substrate 10 has an opposite first surface f 1 And a second surface f 2 . Shallow Trench Isolations (STI) 15 are spaced apart within the substrate 10, the shallow trench isolations 15 being formed from the second surface f 2 Extending into the substrate 10 along the thickness direction of the substrate 10, the shallow trench isolation 15 is located between adjacent pixel units and/or between the photosensitive region 17 and the reading region 16. The material of the shallow trench isolation 15 is, for example, silicon oxide. The isolation trench 12 is formed from the first surface f 1 Extending into the substrate 10 along the thickness direction of the substrate, the isolation trenches 12 are communicated with the shallow trench isolation 15, and jointly act as isolation in the direction perpendicular to the substrate to prevent optical crosstalk between pixel units.
Fig. 5 shows a partial schematic view of the isolation trench 12 and the PN junction 13, the isolation layer 14 not being shown for clarity of view. As shown in fig. 5, the center line (symmetry axis) of the isolation trench 12 is AA', and the PN junction 13 is a circular ring or a square ring in a plan view. Ion concentrations of the second type are substantially equal at equal locations from a center line AA' of the isolation trench 12 within ion regions of the second type implanted into the periphery substrate of the isolation trench 12. For example, a distance r between a line segment BB 'perpendicular to the substrate direction and a center line AA' in the PN junction 13; line segment BB 'is centered about centerline AA' and the concentration of the second type of ion is substantially equal throughout the annulus formed by the circle. It should be understood that substantially equal means that, because in industrial production, no process can be made absolutely equal under the same conditions, but that, because the same or similar process conditions are employed, the ion concentrations can be made substantially equal. In addition, if the second type of ion implantation is performed before the isolation trench 12 is formed, this technical effect cannot be achieved, since the ion implantation is gradually attenuated as the thickness of the substrate increases, and even with the multiple ion implantation, the uniformity of the ion implantation in the present embodiment cannot be achieved. The uniformity and consistency of ion implantation in this embodiment also bring improvement to the consistency of device performance, and improve the isolation effect at the same time.
Alternatively, the isolation trench 12 may extend through the substrate 10, and the isolation trench 12 is located between adjacent pixel units and directly separates two pixels, where there is no shallow trench isolation 15 between the two pixels.
The isolation trench 12 may be formed after the shallow trench isolation 15 is formed, and the shallow trench isolation 15 is used as an etching stop structure of the isolation trench 12, so that damage to the pixel in the etching process can be prevented. Specifically, the damage of the etching process to the gate dielectric layer 21 can be prevented, so that the integrity of the gate dielectric layer 21 is ensured, and the imaging quality is improved.
The first surface f 1 A second surface f of the substrate 10 for receiving incident light for the image sensor 2 A gate dielectric layer 21, a floating gate layer 22, a dielectric stack 23 and a control gate layer 24 are sequentially stacked on one side. To facilitate process operations, the image sensor may be bonded to wafer 30 through bonding layer 25. Wafer 30 may be a carrier wafer that is temporarily bonded to provide support. Wafer 30 may also be a device wafer, such as a logic wafer.
The substrate 10 is, for example, a silicon substrate; specifically, the material thereof may be selected from single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon On Insulator (SOI), or the like. The material of the gate dielectric layer 21 may be an oxide, such as silicon dioxide. The floating gate layer 22 and the control gate layer 24 may be made of polysilicon. The dielectric stack 23 may be a silicon oxide-silicon Nitride-oxide (ONO) stack. Circuit structures, such as stacked dielectric layers in which interconnect vias may be disposed and wiring layers in which structures such as metal lines, contact pads (pads) may be disposed may also be included on the control gate layer 24, and may be located between the control gate layer 24 and the bonding layer 25, not shown.
In each pixel unit, the photosensitive area 17 and the floating gate layer 22 area corresponding to the right lower part of the reading area 16 are connected and integrally arranged; when light irradiates onto the photosensitive region 17, photo-generated carriers are generated in the photosensitive region 17 and reflected as a potential change on the floating gate layer 22, which, after being coupled to the reading region 16, changes the magnitude of the reading current in the reading region 16, so that the light intensity is read out from the reading region. The read region 16 may be connected to pixel circuits for sensing voltage changes caused by charges stored in the read region 16. The pixel circuit includes, for example, a reset transistor, a sense transistor, an address transistor, and the like. The pixel circuit is utilized on the one hand to write a reset data value into the image sensor pixel to reset the read area and on the other hand to read out data from the image sensor pixel through the pixel circuit, the data corresponding to a portion of the captured image.
Each of the pixel cells includes a photosensitive region 17 and a reading region 16. The floating gate layer 22 and the control gate layer 24 have a first region 27 corresponding to the photosensitive region 17, and the floating gate layer 22 and the control gate layer 24 have a second region 26 corresponding to the read region 16.
The floating gate layer 22 and the control gate layer 24 have regions corresponding to the photosensitive region 17 and the read region 16, respectively, referring to functional and/or positional correspondence; specifically, the photosensitive region 17 and the first region 27 are the same structure as that in one photoelectric conversion transistor. The first region 27 is located directly below the photosensitive region 17 (first surface f 1 At the upper and second surfaces f 2 Below is arrangedAzimuth), the second region 26 is located directly below the read zone 16.
In one embodiment, the photosensitive region 17 includes a photosensitive element (e.g., photodiode PD), and the photosensitive element of the photosensitive region 17 generates photogenerated carriers under the influence of light. In another embodiment, in the photosensitive region 17, a first photodiode and a second photodiode are stacked and distributed in the thickness direction of the substrate 10, the first photodiode being located above the second photodiode. In the photosensitive region 17, vertical charge transfer regions are distributed on one side of the first photodiodes and the second photodiodes, which are stacked and distributed, close to the shallow trench isolation 15. The read region 16 is connected to pixel circuitry for sensing voltage variations caused by charges in the read region.
It can be appreciated that the image sensor provided by the embodiment of the present invention may be a VPS structure based on a flash memory process. In a VPS structure based on a flash memory process, the photosensitive region 17 and the read region 16 are separated by a Shallow Trench Isolation (STI) 15. The portion of the floating gate layer 22 directly below the photosensitive region 17 is integrally provided with the portion directly below the reading region 16, and the portion of the control gate layer 24 directly below the photosensitive region 17 is provided separately from the portion directly below the reading region 16. The photosensitive region 17 and the floating gate layer 22 region respectively corresponding to the right lower part of the reading region 16 are integrally arranged, so that the photosensitive region 17 can generate voltage coupling action on the reading region 16 when the photosensitive region 17 generates photo-generated carriers through irradiation of incident light; the control gate layers 24 respectively corresponding to the right under the photosensitive region 17 and the reading region 16 are isolated from each other to apply voltages respectively, thereby realizing gate control.
The first surface f 1 The image sensor so prepared has a backside illuminated (Back Side Illumination, BSI) structure for the surface of the image sensor that receives incident light. As can be appreciated, with the first surface f 1 As the surface for receiving the incident light, the influence of the circuit structure, the control gate layer 24, the dielectric stack 23, the floating gate layer 22, the gate dielectric layer 21 and other structures on the incident light is avoided, and the photon receiving quantity is increased.
The image sensor manufactured by the embodiment of the invention comprises an array of pixel units of the image sensor. The pixel cells in an image sensor may include a photosensitive element such as a photodiode that converts incident light into electrons. The image sensor may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). In high-end devices, the image sensor may have tens of millions of pixels.
In summary, the image sensor and the manufacturing method thereof provided by the invention comprise: providing a substrate, wherein a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate; etching the substrate to form isolation trenches between adjacent pixel units; performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and the ions in the first type well region form PN junctions in the peripheral substrate of the isolation trench; and forming an isolation layer, wherein the isolation layer fills the isolation trench. The isolation trenches are typically deep and the isolation layer located in the isolation trenches serves as isolation, known as Deep Trench Isolation (DTI). The isolation between the pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed by ion implantation, PN junctions are formed in the peripheral substrate of the isolation trenches, carriers generated by defects near the Deep Trench Isolation (DTI) are prevented from freely entering a reading area and a photosensitive area, good electrical and optical isolation effects are achieved while dark current is reduced, and on the section perpendicular to the substrate, the sectional area of an isolation area formed by the PN junctions in the peripheral substrate of the isolation trenches and the isolation layer in the isolation trenches is smaller than the sectional area of the isolation area formed only by ion implantation, so that effective isolation is achieved, the area of the isolation area is reduced, and the chip area utilization rate of the image sensor is improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since the device corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (13)
1. A method for manufacturing an image sensor, comprising:
providing a substrate having opposite first and second surfaces; a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate;
etching the substrate to form isolation trenches between adjacent pixel units;
performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and the ions in the first type well region form PN junction isolation in the peripheral substrate of the isolation trench;
forming an isolation layer, wherein the isolation layer fills the isolation trench;
wherein the second type of ions comprises N-type P ions, N-type As ions or P-type B ions; when the second type of ions is N-type P ions, implanting depth at the periphery of the isolation trench isWhen the second type ion is N type As ion, the implantation depth is +.>When the second type of ions is P-type B ions, implanting depth is +.>
2. The method of manufacturing an image sensor according to claim 1, wherein in the ion implantation, the ion implantation inclination angle range is: 7-45 degrees.
3. The method of manufacturing an image sensor according to claim 1, wherein in the ion implantation, an implantation energy of the ions is in a range of 5keV to 45keV, and an implantation dose of the ions is in a range of 5 x 10 14 ions/cm 2 ～1×10 16 ions/cm 2 。
4. The method of manufacturing an image sensor according to claim 1, wherein each of the pixel units includes a photosensitive region and a reading region; before etching the substrate to form the isolation trench, the method further comprises:
forming shallow trench isolations which are distributed in the substrate at intervals, wherein the shallow trench isolations extend from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is positioned between adjacent pixel units and/or between the photosensitive area and the reading area.
5. The method of manufacturing an image sensor according to claim 4, wherein the isolation trench is formed after the shallow trench isolation is formed, and the isolation trench stops on the shallow trench isolation from the first surface through a part of the thickness of the substrate in the thickness direction of the substrate.
6. The method of manufacturing an image sensor according to claim 1, wherein ion concentrations of the second type are substantially equal at a position equal from a center line of the isolation trench in an ion region of the second type implanted into a peripheral substrate of the isolation trench.
7. An image sensor, comprising:
a substrate having opposed first and second surfaces; a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate;
an isolation trench penetrating at least a portion of the thickness of the substrate, the isolation trench being located between adjacent ones of the pixel cells;
an isolation layer filled in the isolation trench;
PN junction isolation formed in the periphery substrate of the isolation trench, the PN junction isolation being formed by ions of a second type implanted in the periphery substrate of the isolation trench and ions in the first type well region;
wherein the second type of ions comprises N-type P ions, N-type As ions or P-type B ions; when the second type of ions is N-type P ions, implanting depth at the periphery of the isolation trench isWhen the second type ion is N type As ion, the implantation depth is +.>When the second type of ions is P-type B ions, implanting depth is +.>
8. The image sensor of claim 7, wherein each of the pixel cells includes a photosensitive region and a read region, the isolation trench further being located between the photosensitive region and the read region.
9. The image sensor as in claim 8,
shallow trench isolations are distributed in the substrate at intervals, and extend from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is positioned between adjacent pixel units and/or between the photosensitive area and the reading area;
the isolation trench extends from the first surface into the substrate along the thickness direction of the substrate, and is in isolation communication with the shallow trench.
10. The image sensor of claim 7, wherein the concentration of ions of the second type is substantially equal at a location equal from a centerline of the isolation trench within the ion region of the second type implanted into the perimeter substrate of the isolation trench.
11. The image sensor of claim 8, wherein the second surface of the substrate is laminated with a gate dielectric layer, a floating gate layer, a dielectric stack, and a control gate layer in that order; the part of the floating gate layer right below the photosensitive area is integrally arranged with the part right below the reading area, and the part of the control gate layer right below the photosensitive area is isolated from the part right below the reading area.
12. The image sensor of claim 10, wherein ion concentrations of the second type are substantially equal at equal locations from a centerline of the isolation trench within ion regions of the second type implanted in the first type well region surrounding a substrate of the isolation trench.
13. The image sensor of claim 7, wherein the isolation trench has a cross-sectional width of 0.08 to 0.3 microns in a cross-section perpendicular to the substrate.
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