KR100997353B1 - Image Sensor and Method for Manufacturing thereof - Google Patents

Abstract

In another aspect, a method of manufacturing an image sensor includes: forming a semiconductor substrate including a readout circuit; Forming an interlayer insulating film including a plurality of wirings on the semiconductor substrate; Forming a via hole penetrating the interlayer insulating film to expose the interconnection; Forming a metal layer on the interlayer insulating layer so that the via holes are gap-filled; Performing a CMP process on the metal layer to form a via contact having a dishing region formed on a surface thereof; Removing the interlayer insulating film including a portion of the via contact in which the dishing region is formed, in a horizontal direction to form an interlayer insulating layer and a metal contact having a flat surface; And forming an image detector on the interlayer insulating layer including the metal contact.

Image sensor, 3D image sensor, photodiode

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is divided into a charge coupled device (CCD) and a CMOS image sensor (CIS). do.

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

However, in the case of wafer-to-wafer bonding, the bonding surface of the wafer is not uniform, and thus the bonding force may decrease. Since the wiring for connecting the photodiode and the circuit region is exposed to the surface of the interlayer insulating film, the interlayer insulating film has a nonuniform surface profile, and thus the bonding force with the photodiode formed on the interlayer insulating film may be reduced. . In addition, the photodiode and the interlayer insulating layer may be formed of different materials, and thus the bonding strength thereof may be degraded.

In addition, dishing appears in the wiring region during the CMP process of the interlayer insulating layer to form the wiring, and thus the wiring and the photodiode are not electrically connected.

Meanwhile, according to the related art, since both the source and the drain of the transfer transistor are doped with a high concentration N type, charge sharing occurs as illustrated in FIG. 18. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur. In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

The embodiment provides an image sensor excellent in physical and electrical contact force between a photodiode and a substrate on which a readout circuit is formed while employing a vertical photodiode, and a method of manufacturing the same.

A method of manufacturing an image sensor according to a first embodiment includes forming a semiconductor substrate including a readout circuit; Forming an interlayer insulating film including a plurality of wirings on the semiconductor substrate; Forming a via hole penetrating the interlayer insulating film to expose the interconnection; Forming a metal layer on the interlayer insulating layer so that the via holes are gap-filled; Performing a CMP process on the metal layer to form a via contact having a dishing region formed on a surface thereof; Removing the interlayer insulating film including a portion of the via contact in which the dishing region is formed, in a horizontal direction to form an interlayer insulating layer and a metal contact having a flat surface; And forming an image detector on the interlayer insulating layer including the metal contact.

A method of manufacturing an image sensor according to a second embodiment includes forming a semiconductor substrate including a readout circuit; Forming an interlayer insulating layer including a plurality of wirings on the semiconductor substrate; Forming a crystalline wafer on the interlayer insulating film; Forming via holes in the interlayer insulating layer and the crystalline wafer to expose the interconnects; Forming a metal layer on the crystalline wafer such that the via holes are gapfilled; Performing a CMP process on the metal layer to form a via contact having a dishing region formed on a surface thereof; Removing the crystalline wafer including a portion of the via contact in which the dishing region is formed, in a horizontal direction to form a crystalline semiconductor layer and a metal contact having a flat surface; And forming an image detector on the crystalline semiconductor layer including the metal contact.

An image sensor according to a second embodiment includes a semiconductor substrate including a readout circuit; An interlayer insulating layer including a plurality of wirings formed on the semiconductor substrate; A crystalline semiconductor layer formed on the interlayer insulating film; A via hole formed in the interlayer insulating layer and the crystalline semiconductor layer to expose the wiring; A metal contact formed in the via hole; And an image detector formed on the crystalline semiconductor layer including the metal contact.

According to the image sensor and the manufacturing method thereof according to the embodiment, the fill factor can be improved by collecting the readout circuit and the photodiode.

In addition, since the hydrogen injection layer is formed inside the interlayer insulating film formed by the CMP process and the interlayer insulating film corresponding to the upper portion of the hydrogen injection layer is removed by the cleaving process, a flat surface interlayer insulating layer may be formed. . Therefore, since the interlayer insulating layer and the image sensing unit are connected to the face-to-face, the electrical characteristics may be improved to increase the yield of the image sensor.

 In addition, a hydrogen injection layer is formed inside the crystalline semiconductor layer formed on the interlayer insulating layer and wired by the CMP process, and the crystalline semiconductor layer corresponding to the upper portion of the hydrogen injection layer is removed by the cleaving process. A crystalline semiconductor layer may be formed. Therefore, since the crystalline semiconductor layer and the image sensing unit are connected face to face, electrical characteristics may be improved.

In addition, since the image sensing unit is formed on the crystalline semiconductor layer by a bonding process, the bonding surface is solid, thereby improving reliability.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode such as a CCD image sensor.

<First Embodiment>

Hereinafter, a method of manufacturing the image sensor according to the first embodiment will be described with reference to FIGS. 1 to 10.

1 and 2, the wiring 150 and the interlayer insulating layer 160 are formed on the semiconductor substrate 100 including the readout circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation layer 110 is formed on the semiconductor substrate 100 to define an active region. A readout circuit 120 including transistors for each unit pixel is formed in the active region corresponding to the pixel portion.

FIG. 2 is a detailed view of the readout circuit 120 shown in FIG. 1.

Referring to FIG. 2, the readout circuit 120 and the wiring 150 will be described in detail. The readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. . Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be any one of 3Tr, 4Tr, or 5Tr.

The forming of the lead-out circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100 and the wiring 150 on the electrical junction region 140. The method may include forming a first conductivity type connection region 147 connected to the first conductive connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the embodiment, as shown in FIG. 2, an electrical junction region 140 is formed in the semiconductor substrate 100 on which the readout circuit 120 is formed such that there is a voltage difference between the source / drain across the transfer transistor (Tx) 121. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 2 and 3.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated in the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the semiconductor substrate 100, is P0 / N- / Pwell during the 4-Tr APS Reset operation. In the junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141). Therefore, P0 / N- / Pwell double junction is more than Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the related art, according to the embodiment, problems such as degradation of saturation and degradation of sensitivity can be avoided.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit 120 to minimize the dark current source by creating a smooth movement path of the photo charge. Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the embodiment may form an N + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

4 shows another structure for the readout circuit. As shown in FIG. 4, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 4, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, wherein the process of forming the N + connection region 148 and the M1C contact 151a is performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process inside these electric fields become a source of liquidity.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added, which is also a leakage source. Can be

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented.

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Next, an interlayer insulating layer 160 may be formed on the semiconductor substrate 100, and the wiring 150 may be formed. The wiring 150 may include a second metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

Referring to FIG. 1 again, a method of forming the fourth metal contact 154a after forming the third metal 153 will be described. First, a via hole is formed in the interlayer insulating layer 160 on which the third metal 153 is formed so that the third metal 153 is exposed, and then a metal layer 15 such as tungsten is formed in the interlayer insulating layer 160 so that the via hole is gap-filled. Evaporate).

As shown in FIG. 5, the CMP process may be performed on the metal layer 15 to form a via contact 154 electrically connected to the third metal 153 in the via hole. In particular, a dishing region 155 may be formed in the via contact 154 during the CMP process for forming the via contact 154.

The dishing area 155 may have a lower height than the interlayer insulating layer 160 because the via contact 154 has a different polishing rate according to the hardness between materials during the CMP process. When the dishing region 155 is formed in the via contact 154, the dishing region 155 may be electrically disconnected from the photodiode formed later.

Referring to FIG. 6, an ion implantation process is performed on the interlayer insulating layer 160. The ion implantation process may be performed on the entire interlayer insulating layer 160 using hydrogen ions (H ₂ ). By controlling ion implantation energy during the ion implantation process, the hydrogen ions H ₂ may be implanted into the interlayer insulating layer 160 corresponding to the lower portion of the dishing region 155.

Referring to FIG. 7, a hydrogen injection layer 180 is formed inside the interlayer insulating layer 160 corresponding to the lower portion of the dishing region 155. In addition, a heat treatment process may be performed to change the hydrogen injection layer 180 into a hydrogen gas layer.

The hydrogen injection layer 180 may be formed in a horizontal direction in the interlayer insulating layer 160 between the dishing region 155 and the third metal 153. In addition, the hydrogen injection layer 180 may be formed in the via contact 154 under the dishing region 155.

For example, the interlayer insulating layer 160 and the via contact 154 corresponding to the hydrogen injection layer 180 on the basis of the hydrogen injection layer 180 are referred to as the dummy insulating layer 60 and the dummy contact 54. It is called. Since the hydrogen injection layer 180 is formed in a bubble shape, an interlayer insulating layer including the dummy contact layer 60 including the dummy contact 54 and the via contact 154 based on the hydrogen injection layer 180. 160 is in a state that can be easily separated.

Referring to FIG. 8, the dummy insulating layer 60 including the dummy contact 54 is removed to form a fourth metal contact 154a on the interlayer insulating layer 160a. For example, the dummy insulating layer 60 may be removed by performing a cleaving process on the hydrogen injection layer 180. That is, the dummy insulating layer 60 may be removed using a blade or the like while leaving the interlayer insulating layer 160a on the basis of the hydrogen injection layer 180.

When the hydrogen injection layer 180 and the dummy insulating layer 60 are physically removed by the cleaving process, the surfaces of the interlayer insulating layer 160a and the fourth metal contact 154a may have a flat surface. . In particular, since the dummy contact 54 having the dishing area 155 is included in the dummy insulating layer 60, when the dummy insulating layer 60 is removed, the surface of the fourth metal contact 154a is flat. (flat type) can be formed.

9, an image detector 200 is formed on the interlayer insulating layer 160a. The image sensing unit 200 may be formed by a bonding process with the interlayer insulating layer 160a. In addition, the image detector 200 may include a first impurity region N− and a second impurity region P + to have a photodiode structure of a PN junction. In addition, an ion implantation region N + may be formed under the first impurity region N−. The ion implantation region N + may serve as an ohmic contact.

For example, the image detecting unit 200 ion-implants N-type impurities (N−) and P-type impurities (P +) in order in the p-type carrier substrate (not shown) having a crystalline structure, and thus the first impurity region (N). -) And the second impurity region P + are formed. In addition, an ion implantation region N + may be formed by ion implanting a high concentration of n-type impurities N + under the first impurity region N−. For example, the first impurity region may be formed with a junction depth of 1.0 μm to 2.0 μm, and the second impurity region may be formed with a junction depth of 0.5 μm or less.

The image sensing unit 200 may be a PIN diode including an n-type amorphous silicon, an intrinsic amorphous silicon, and a p-type amorphous silicon. It may be formed.

Next, the ion implantation region N + of the carrier substrate is positioned to face the interlayer insulating layer 160a, and a bonding process is performed to bond the semiconductor substrate 100 and the carrier substrate. Thereafter, the carrier substrate is removed by a cleaving process so that the image sensing unit 200 bonded on the interlayer insulating layer 160 is exposed.

According to an embodiment, the image sensing unit 200 may employ a three-dimensional image sensor positioned above the readout circuit 120 to increase the fill factor and prevent defects of the image sensing unit 200. .

In addition, since the thickness of the first impurity region N− is greater than the thickness of the second impurity region P +, the charge storage capacity may be increased. That is, by forming the N-layer thicker to expand the area, it is possible to improve the capacity (capacity) that may contain the optoelectronic.

In addition, since the image sensing unit 200 is formed on the interlayer insulating layer 160a including the fourth metal contact 154a from which the dishing region 155 is removed, the image sensing unit 200 and the fourth metal contact are formed. This electrical connection can be effectively made 154a.

Referring to FIG. 10, an etching process may be performed such that the image sensing unit 200 is formed only in the pixel area. Therefore, the wiring 150 and the interlayer insulating layer 160a corresponding to the peripheral area may be exposed.

Although not shown, the device isolation region may be additionally formed in the image sensing unit 200, and then an upper electrode, a color filter, and a micro lens forming process may be performed.

Second Embodiment

17 is a diagram illustrating an image sensor according to a second embodiment.

The image sensor according to the second embodiment includes a semiconductor substrate 100 including a readout circuit 120; An interlayer insulating layer 160 including a plurality of wirings 150 formed on the semiconductor substrate 100; A crystalline semiconductor layer 300a formed on the interlayer insulating layer 160; A via hole 310 formed in the interlayer insulating layer 160 and the crystalline semiconductor layer 300a to expose the wiring 150; A metal contact 354a formed in the via hole 310; And an image detector 200 formed on the crystalline semiconductor layer 300 including the metal contact 354a.

The crystalline semiconductor layer 300a and the image sensing unit 200 may be formed of a silicon layer having a crystalline structure, and thus the junction surface of the crystalline semiconductor layer 300a and the image sensing unit 200 may be firm.

Unexplained reference numerals among the reference numerals of FIG. 17 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing the image sensor according to the second embodiment will be described with reference to FIGS. 11 to 17. In the description of the second embodiment, the same reference numerals are used for the same components as those of the first embodiment. In addition, the description of the same components as in the first embodiment will be omitted.

Referring to FIG. 11, a wiring 150 and an interlayer insulating layer 160 are formed on the semiconductor substrate 100 on which the readout circuit 120 is formed. The formation of the lead-out circuit 120, the first metal contact 151a, the first metal 151, the second metal 152, and the third metal 153 formed on the semiconductor substrate 100 may be different from those of the first embodiment. Since it is the same, a description thereof will be omitted.

Therefore, as shown in FIG. 10, the wiring 150 formed on the semiconductor substrate 100 is formed to the third metal 153.

Next, the crystalline wafer 300 is formed on the interlayer insulating layer 160. For example, the crystalline wafer 300 may be a single crystal or polycrystalline silicon layer.

The crystalline wafer 300 may be combined with the interlayer insulating layer 160 by a bonding process. Meanwhile, before bonding the crystalline wafer 300 and the interlayer insulating layer 160, the bonding may be performed by increasing the surface energy of the surface bonded by plasma activation.

Meanwhile, in order to improve the bonding force, bonding may be performed by placing an insulating layer, a metal layer, or the like on the bonding interface.

12, a via hole 310 is formed in the crystalline wafer 300 and the interlayer insulating layer 160 to expose the third metal 153. The via hole 310 may be formed by removing a portion of the crystalline wafer 300 and the interlayer insulating layer 160 by a selective etching process. Therefore, the third metal 153 may be selectively exposed by the via hole 310.

Referring to FIG. 13, a via contact 354 is formed in the via hole 310 to be electrically connected to the third metal 153. The via contact 354 may be formed by depositing a metal layer such as tungsten (not shown) on the crystalline wafer 300 so as to gap fill the via hole 310 and then planarizing the same.

In this case, the planarization process for the via contact 354 is a CMP process, and a dishing region 355 is formed in the via contact 354 during the CMP process. That is, since the polishing rate varies according to the hardness between materials during the CMP process, a dishing area 355 having a recessed shape is formed on the via contact 354.

As described above, when the dishing region 355 is formed in the via contact 354, electrical contact with the image sensing unit 200 formed on the via contact 354 may not be performed, and an error may occur in the device. The removal process for the dishing area 355 is required.

14 and 15, a hydrogen injection layer 380 is formed inside the crystalline wafer 300 by performing an ion implantation process on the crystalline wafer 300.

The hydrogen injection layer 380 may be entirely formed in the crystalline wafer 300 corresponding to the lower portion of the dishing region 355. The hydrogen injection layer 380 may be formed in a desired region by performing an ion implantation process using hydrogen ions (H ₂ ). That is, by controlling the ion implantation energy during the ion implantation process, the hydrogen ions (H ₂ ) may be formed in the horizontal direction inside the crystalline wafer 300 corresponding to the lower portion of the dishing region 355. In addition, a heat treatment process may be performed to change the hydrogen injection layer 380 into a hydrogen gas layer.

Therefore, since the hydrogen injection layer 380 is formed inside the crystalline wafer 300 corresponding to the dishing region 355 and the third metal 153, the via contact 354 also includes the hydrogen injection layer ( 380). For example, the crystalline wafer 300 and the via contact 354 corresponding to the hydrogen injection layer 380 on the basis of the hydrogen injection layer 380 are referred to as a dummy layer 30 and a dummy contact 355. . That is, the dummy layer 35 may include a dummy contact 355 having a dishing area 355 formed therein.

Therefore, since the hydrogen injection layer 380 is formed in a bubble shape, the dummy layer 30 and the crystalline wafer 300 may be easily separated based on the hydrogen injection layer 380.

Referring to FIG. 16, the dummy layer 30 including the dummy contact 355 is removed to form a fourth metal contact 354a on the crystalline semiconductor layer 300a. For example, the dummy layer 35 may be removed by performing a cleaving process on the hydrogen injection layer 380. That is, the dummy layer 30 may be removed using a blade or the like so as to leave the crystalline semiconductor layer 300a based on the hydrogen injection layer 380.

When the hydrogen injection layer 380 and the dummy layer 30 are physically removed by the cleaving process, the surfaces of the crystalline semiconductor layer 300a and the fourth metal contact 354a may have a flat surface. In particular, since the dummy contact 355 having the dishing area 355 is included in the dummy layer 30, when the dummy layer 30 is removed, the surface of the fourth metal contact 354a is flat. type).

Referring to FIG. 17, an image detector 200 is formed on the crystalline semiconductor layer 300a. The image sensing unit 200 may be coupled to the crystalline semiconductor layer 300a by a bonding process.

The image detector 200 may be formed by ion implanting impurities into a crystalline wafer. For example, the image detector 200 may be formed of a first impurity region N− and a second impurity region P + to have a photodiode structure of a PN junction. In addition, an ion implantation region N + may be formed under the first impurity region N−. The ion implantation region N + may serve as an ohmic contact.

The image sensing unit 200 formed as described above is coupled to the crystalline semiconductor layer 300a by a bonding process. In particular, since the image sensing unit 200 and the crystalline semiconductor layer 300a are formed of the same material, the bonding force may be strong.

In addition, since the image sensing unit 200 is formed on the crystalline semiconductor layer 300a including the fourth metal contact 354a from which the dishing region 155 is removed, the image sensing unit 200 and the fourth metal contact. This electrical connection can be effectively made 354a.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 9 are sectional views showing the manufacturing process of the image sensor according to the first embodiment.

10 to 16 are cross-sectional views illustrating a manufacturing process of an image sensor according to a second embodiment.

17 is a view schematically showing a dumping structure of a photocharge according to the prior art.

Claims (11)

delete delete delete delete Forming a semiconductor substrate comprising a readout circuit; Forming an interlayer insulating layer including a plurality of wirings on the semiconductor substrate; Forming a crystalline wafer on the interlayer insulating layer; Forming a via hole in the interlayer insulating layer and the crystalline wafer to expose a topmost wiring of the wirings; Forming a metal layer on the crystalline wafer such that the via holes are gapfilled; Performing a CMP process on the metal layer to form a via contact having a dishing region formed on a surface thereof; Removing the crystalline wafer including a portion of the via contact in which the dishing region is formed, in a horizontal direction to form a crystalline semiconductor layer and a metal contact having a flat surface; And And forming an image sensing unit on the crystalline semiconductor layer including the metal contact. The method of claim 5, And the crystalline wafer is formed by a bonding process on the interlayer dielectric layer. The method of claim 5, Forming the crystalline semiconductor layer and the metal contact, Implanting hydrogen ions into the crystalline wafer and the via contact to form a hydrogen injection layer on the crystalline wafer and the via contact corresponding to the lower portion of the dishing region; And And removing the crystalline wafer and the via contact corresponding to the upper region of the hydrogen injection layer together with the hydrogen injection layer. The method of claim 5, And the crystalline wafer including a portion of the via contact in which the dishing region is formed is removed in a horizontal direction by a cleaving process. The method of claim 5, And the image sensing unit is formed on the crystalline semiconductor layer by a bonding process. delete delete

Images