KR100649527B1 - Plasma display, and driving device and method thereof - Google Patents

Abstract

A plasma display device, a driving device, and a driving method thereof are provided to reduce the cost by using a transistor with a voltage corresponding to a quarter of voltage applied to a Y electrode. A plasma display device includes plural first electrodes(Y); a first transistor(Ys) having a first stage connected to a first power source(Vs) supplying a first voltage; a second transistor(Yg) having a first stage connected to a second stage of the first transistor and a second stage connected to a second power source supplying a second voltage lower than the first voltage; a first capacitor(Cst1) of which a first stage is connected to the contact point between the first and second transistors; a second capacitor(Cst2) having a first stage connected to a second stage of the first capacitor; a charging path connected between the second power source and a second stage of the second capacitor to charge the first and second capacitors when the first transistor is turned on; plural third transistors(Yh) having first stages connected to the first electrodes, respectively; plural fourth transistors(Yl) having first stages connected to the first electrodes, respectively; a fifth transistor(Sch) connected among the second stages of the third transistors and the first stage of the first capacitor; a sixth transistor(Scl) connected among the second stages of the fourth transistors and the second stage of the second capacitor; an increasing path connected among the second stages of the third transistors and the contact point between the first and second capacitors to increase the voltage of the first electrodes; and a decreasing path connected among the second stages of the fourth transistors and the contact point between the first and second capacitors to decrease the voltage of the first electrodes.

Description

Plasma display device, driving device thereof and driving method thereof {PLASMA DISPLAY, AND DRIVING DEVICE AND METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 to 4 are diagrams illustrating driving waveforms of the plasma display device according to the first to third embodiments of the present invention, respectively.

5 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 4.

FIG. 6 is a diagram illustrating signal timing of the sustain discharge driving circuit 410 for generating the driving waveform of FIG. 4.

7A to 7F are views illustrating the operation of the sustain discharge driving circuit 410 of FIG. 5 according to the signal timing of FIG. 6, respectively.

The present invention relates to a plasma display device and a driving device thereof.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, dozens to millions of discharge cells are arranged in a matrix form according to their size.

In the plasma display device, one field (1TV field) is divided into a plurality of subfields having respective weights and driven, and the gray level is displayed by a combination of the weights of the subfields in which the display operation occurs among the plurality of subfields. In the address period of each subfield, discharge cells to emit light and discharge cells not to emit light are selected by the address discharge, and the discharge cells to emit light selected in the sustain period are sustained and discharged for a period corresponding to the weight of the subfield to display an image. do.

In particular, since the high level voltage and the low level voltage are alternately applied to the electrodes performing sustain discharge in the sustain period, the transistor for applying the high level voltage and the low level voltage corresponds to at least the difference between the high level voltage and the low level voltage. Should have a voltage withstand voltage. As a result, the transistor having a high breakdown voltage increases the cost of the sustain discharge driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device capable of using a low breakdown voltage transistor in a sustain discharge driving circuit, a driving device thereof, and a driving method thereof.

According to an aspect of the present invention, a plasma display device includes a plurality of first electrodes, a first transistor having a first terminal connected to a first power source for supplying a first voltage, and a second terminal of the first transistor. A second transistor having a first end connected to a second power supply for supplying a second voltage lower than the first voltage, and a first end connected to a contact point between the first transistor and the second transistor A first capacitor, a second capacitor connected to a second end of the first capacitor, a second capacitor connected between the second power supply and a second end of the second capacitor, and a turn-on of the first transistor A charge path for charging the first and second capacitors, a plurality of third transistors each having a first end connected to the plurality of first electrodes, and a first end respectively connected to the plurality of first electrodes Plural fourth transistors A fifth transistor connected between a second end of the plurality of third transistors and a first end of the first capacitor, and connected between a second end of the plurality of fourth transistors and a second end of the second capacitor. A sixth transistor, a rising path connected between a second end of the plurality of third transistors and a contact point of the first and second capacitors to raise voltages of the plurality of first electrodes, and the plurality of fourth transistors And a falling path connected between a second end of the first terminal and a contact point of the first and second capacitors to reduce voltages of the plurality of first electrodes.

According to another aspect of the present invention, a method of driving a plasma display device including a first electrode and a second electrode is provided. The driving method includes applying a fourth voltage to the first electrode through a first power supply for supplying a first voltage and first and second capacitors respectively charging a second voltage and a third voltage, wherein the fourth voltage is applied to the first electrode. Increasing a voltage of the first electrode through a first resonant path including a first power supply and the first capacitor and the first inductor, a second power supply supplying a fifth voltage higher than the first voltage, and the first power supply; Further increasing the voltage of the first electrode through a second resonant path comprising a capacitor and the first inductor, applying the fifth voltage to the first electrode, a second inductor and the first capacitor, and Reducing the voltage of the first electrode through a third resonant path comprising the second power source, and through the fourth resonant path comprising the second inductor, the first capacitor, and the first power source; And a step of further reducing the voltage of the first electrode.

According to still another feature of the present invention, a driving apparatus of a plasma display device including a plurality of first electrodes and a plurality of second electrodes is provided. The driving device has a first and a second input terminal, an output terminal is connected to the plurality of first electrodes, and the scan integration sequentially applies the voltage of the second input terminal to the plurality of first electrodes during an address period. A first transistor having a first end connected to a first power supply for supplying a first voltage, and a second voltage connected to a second end of the first transistor and lower than the first voltage The second power source is charged with a second transistor and a third voltage connected to a second power supply, and the first end is charged with a first capacitor and a fourth voltage connected to a contact point between the first transistor and the second transistor. A second capacitor having a first end connected to a second end of the first capacitor, a third transistor connected between a first input end of the scan integrated circuit and a first end of the first capacitor, the main capacitor A fourth transistor coupled between a second input end of the integrated circuit and a second end of the second capacitor; a plurality of second transistors connected between the first input end of the scan integrated circuit and the contacts of the first and second capacitors; A rising path for increasing the voltage of one electrode, and a falling path connected between the second input terminal of the scan integrated circuit and the contacts of the first and second capacitors to reduce the voltage of the plurality of first electrodes. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to be "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of the semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is very low, and thus the threshold voltage is regarded as 0V and approximated.

First, a plasma display device, a driving method thereof, and a driving device thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as “A electrodes”) A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs to each other in the row direction (hereinafter, “X”). Electrodes ”(X1 to Xn) and scan electrodes (hereinafter referred to as“ Y electrodes ”) (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X electrode and the Y electrode perform a display operation for displaying an image in the sustain period. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 12. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes an address period and a sustain period.

The address electrode driver 300 receives an A electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each A electrode.

The scan electrode driver 400 receives a Y electrode driving control signal from the controller 200 and applies a driving voltage to the Y electrode.

The sustain electrode driver 500 receives the X electrode driving control signal from the controller 200 and applies a driving voltage to the X electrode.

Next, a driving waveform of the plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4. In the following description, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described.

2 and 3 are diagrams illustrating driving waveforms of the plasma display device according to the first and second exemplary embodiments of the present invention, respectively. 2 and 3 show only drive waveforms in the sustain period.

As shown in Fig. 2, in the sustain period, a sustain discharge pulse having a high level voltage (Vs voltage) and a low level voltage (0 V voltage) is applied to the Y electrode and the X electrode in an opposite phase. Such sustain discharge pulses are repeatedly applied to the Y electrode and the X electrode as many times as the number corresponding to the weight indicated by the corresponding subfield. That is, 0 V is applied to the X electrode when the Vs voltage is applied to the Y electrode, and 0 V is applied to the Y electrode when the Vs voltage is applied to the X electrode. In this way, the voltage difference between each Y electrode and each X electrode alternates between the Vs voltage and the -Vs voltage, so that the sustain discharge is repeated a predetermined number of times in the discharge cell to be turned on.

Unlike in FIG. 2, a sustain discharge pulse having a high level voltage (Vs / 2 voltage) and a low level voltage (−Vs / 2 voltage) may be applied to the Y electrode and the X electrode in an opposite phase in the sustain period. In this case, -Vs / 2 voltage is applied to the X electrode when the Vs / 2 voltage is applied to the Y electrode, and -Vs / 2 voltage is applied to the Y electrode when the Vs / 2 voltage is applied to the X electrode. Even in this manner, similarly to the sustain discharge pulse of FIG. 2, the voltage difference between the X electrode and the Y electrode may alternately have a Vs voltage and a -Vs voltage.

Meanwhile, in the first and second embodiments of the present invention, the case where the sustain discharge pulse having the high level voltage and the low level voltage are alternately applied to the X electrode and the Y electrode in the opposite phase has been described. The sustain discharge pulse may be applied to only one of the Y electrodes. Hereinafter, such an embodiment will be described in detail with reference to FIG. 3.

4 illustrates a driving waveform of a plasma display device according to a third exemplary embodiment of the present invention.

First, as shown in FIG. 4, in the sustain period, a sustain discharge pulse having a voltage of Vs and a voltage of -Vs is applied to the Y electrode while the voltage of 0V is applied to the X electrode. In this manner, the voltage difference between the X electrode and the Y electrode may alternately have a Vs voltage and a -Vs voltage in the same manner as the sustain discharge pulse of FIG. 2.

Next, with reference to FIG. 5, the drive circuit which produces | generates the drive waveform of FIG. 4 is demonstrated in detail.

5 is a diagram illustrating a sustain discharge driving circuit of the scan electrode driver 400 for generating the driving waveform of FIG. 4. In FIG. 5, only the sustain discharge driving circuit 410 connected to the plurality of Y electrodes Y1 to Yn is illustrated for convenience of description, and the sustain discharge driving circuit 410 is formed in the scan electrode driver 400 of FIG. 1. Can be. Since the 0V voltage is applied to the X electrodes X1 to Xn during the sustain period, the plurality of X electrodes X1 to Xn are illustrated as being connected to the ground terminal 0 which supplies the ground voltage 0V. Meanwhile, in the driving waveforms of FIGS. 2 and 3, the sustain discharge driving circuit having the same structure as the sustain discharge driving circuit 410 of FIG. 5 may be connected to the plurality of X electrodes. In the sustain discharge driving circuit 410, only one X electrode and one Y electrode are illustrated for convenience of description, and a capacitive component formed by the X electrode and the Y electrode is illustrated as a panel capacitor Cp.

5 is a diagram illustrating a sustain discharge driving circuit of the scan electrode driver 400 for generating the driving waveform of FIG. 4.

As shown in FIG. 5, the sustain discharge driving circuit 410 includes transistors Ys, Yg, Yh, Yl, capacitors Cst1, Cst2, inductor L, diodes D1, D2, D3, and a selection circuit ( Scan IC). In FIG. 5, the transistors Ys, Yg, Yh, Yl, Sch, and Scl are illustrated as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors, and these transistors Ys, Yg, Yh, Yl, Sch and Scl) may be a body diode formed from a source to a drain direction. And other transistors having similar functions instead of NMOS transistors may be used as these transistors (Ys, Yg, Yh, Yl, Sch, Scl). In FIG. 5, the transistors Ys, Yg, Yh, Yl, Sch, and Scl are shown as one transistor, but the transistors Ys, Yg, Yh, Yl, Sch, and Scl are each a plurality of transistors connected in parallel. Can be formed.

In FIG. 5, only one selection circuit Scan IC connected to one Y electrode is illustrated, but there are a plurality of selection circuits Scan IC respectively connected to the plurality of Y electrodes Y1 to Yn. In addition, a predetermined number of selection circuits (Scan IC) may be formed in the form of one integrated circuit (IC) and connected to a predetermined number of Y electrodes. As shown in FIG. 5, the selection circuit Scan IC has a first input terminal and a second input terminal, and an output terminal is connected to the first electrode. The selection circuit Scan IC includes transistors Sch and Scl. The source of the transistor Sch is connected to the Y electrode and the drain of the transistor Sch is connected to the contact between the cathode of the diode D1 and the second end of the capacitor Cst. A drain of the transistor Scl is connected to the Y electrode, and a source of the transistor Scl is connected to a contact between the first end of the capacitor Cst and the first end of the inductor Ly. The selection circuit Scan IC sequentially applies the voltage of the second input terminal to the first electrode through the transistor Scl to select a discharge cell to be turned on in the address period.

The drain of the transistor Ys is connected to the power supply Vs for supplying the high level voltage Vs of the sustain discharge pulse, and the source of the transistor Yg whose drain is connected to the source of the transistor Ys is sustain discharge. It is connected to a power supply (0V) that supplies a 0V voltage corresponding to half of the high level voltage (Vs) and the low level voltage (0V) of the pulse. The first end of the capacitor Cst1 is connected to the source of the transistor Ys and the drain of the transistor Yg, and the first end of the capacitor Cst2 is connected to the second end of the capacitor Cst1. In addition, an anode of the diode D1 is connected to the second end of the capacitor Cst2, and a cathode of the diode D1 is connected to the power supply 0V. At this time, the diode D1 forms a charging path for charging the capacitors Cst1 and Cst2 to the voltage Vs when the transistor Ys is turned on, and another device (for example, a charge path instead of the diode D1) may be formed. For example, a transistor) may be used. In FIG. 5, it is assumed that Vs / 2 voltage is charged in each capacitor Cst1 and Cst2 by this charging path.

The first end of the inductor L is connected to the contact point of the first end of the capacitor Cst1 and the second end of the capacitor Cst2, and the second end of the inductor L is connected to the anode of the diode D2 and the diode ( It is connected to the contact of the cathode of D3). The cathode of the diode D2 is connected to the drain of the transistor Sch, and the anode of the diode S3 is connected to the source of the transistor Scl.

The source of the transistor Yh is connected to the drain of the transistor Sch, and the drain of the transistor Yh is connected to the first end of the capacitor Cst1. In addition, the drain of the transistor Yl is connected to the source of the transistor Scl, and the source of the transistor Yl is connected to the contact between the second end of the capacitor Cst2 and the anode of the diode D1. At this time, the diode D2 is to set the rising path to block the current path formed by the body diode of the transistor Sch and increase the voltage of the Y electrode, and the diode D3 is the body diode of the transistor Scl. It is to set the falling path to block the current path formed and reduce the voltage of the Y electrode.

Meanwhile, although FIG. 5 illustrates that one inductor Ly is connected to the contacts of the diodes D2 and D3, the inductor may be connected to the rising path and the falling path, respectively.

Next, the operation of the sustain discharge driving circuit 410 of FIG. 5 will be described in detail with reference to FIGS. 6 and 7A to 7F.

6 is a diagram illustrating signal timing of a sustain discharge driving circuit 410 for generating the driving waveform of FIG. 4, and FIGS. 7A to 7F are diagrams illustrating the sustain discharge driving circuit 410 of FIG. 5 according to the signal timing of FIG. 6, respectively. Is a view showing the operation. First, it is assumed that the transistors Ys, Yh, Yl, Sch are turned off and the transistors Yg, Scl are turned on before the mode 1 M1 starts.

6 and 7A, in the mode 1 M1, the transistor Yl is turned on, and as shown in FIG. 7A, the Y electrode, the transistors Scl and Yl and the capacitors Cst2 and Cst1 of the panel capacitor Cp are turned on. The voltage -Vs is applied to the Y electrode through the path of the transistor Yg and the ground terminal 0 (①). At this time, since the -Vs voltage is applied to the Y electrode by the voltage charged in the capacitors Cst2 and Cst1, since the source voltage of the transistor Sch is the -Vs voltage and the drain voltage of the transistor Yh is 0V, the transistor Sch The voltage of Vs is applied between the source of the transistor and the drain of the transistor Yh. Therefore, each transistor Sch and Yh may be used as a transistor having a voltage resistance of Vs / 2. In addition, since the source voltage of the transistor Ys is 0V and the drain voltage of the transistor Ys is the Vs voltage, a transistor having a breakdown voltage of Vs can be used as the transistor Ys.

Subsequently, in the mode 2 (M2), the transistor Sch is turned on and the transistors Yl and Scl are turned off, so that the ground terminal 0, the transistor Yg, the capacitor Cst1, and the inductor (as shown in FIG. 7B). Resonance occurs in the path of the Y electrode of L), diode D2, transistor Sch and panel capacitor Cp. Then, the energy charged in the capacitor Cst1 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from -Vs voltage to 0V voltage (②).

In mode 3 (M3), transistor Ys is turned on and transistor Yg is turned off, so that power supply Vs, transistor Ys, capacitor Cst1, inductor L, diode ( D2), resonance occurs in the path of the Y electrode of the transistor Sch and the panel capacitor Cp. Then, the energy charged in the capacitor Cst1 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from the 0V voltage to the Vs voltage (③).

Next, in the mode 4 (M4), the transistor Yh is turned on, and as shown in FIG. 7D, the power supply Vs, the transistor Ys, the capacitor Cst1, the transistors Yh, Sch, and the panel capacitor Cp are turned on. The voltage Vs is applied to the Y electrode through the path of the Y electrode (④). At this time, since the drain voltage of the transistor Scl is the Vs voltage and the source voltage of the transistor Yl becomes the 2Vs voltage by the capacitors Cst1 and Cst2, Vs is connected between the drain of the transistor Scl and the source of the transistor Yl. Voltage is applied. Therefore, each transistor Scl and Yl can be used as a transistor having a breakdown voltage of Vs / 2. In addition, since the drain voltage of the transistor Yg is Vs and the source voltage of the transistor Yg is 0V, a transistor having a Vs voltage as a breakdown voltage can be used as the transistor Yg.

In mode 5 M5, the transistor Scl is turned on and the transistors Yh and Sch are turned off, so that the Y electrode, the transistor Scl, the diode D3, the inductor of the panel capacitor Cp as shown in FIG. 7E. Resonance occurs in the paths of (L), capacitor (Cst1), transistor (Ys), and power supply (Vs). Then, while the energy stored in the panel capacitor Cp is recovered to the power supply Vs through the inductor L, the voltage of the Y electrode decreases from the voltage Vs to the voltage 0V.

In mode 6 (M6), transistor Yg is turned on and transistor Ys is turned off, so that the Y electrode, transistor Scl, diode D3, and inductor L of panel capacitor Cp as shown in FIG. 7F. ), Resonance occurs in the path of the capacitor Cst1, the transistor Yg, and the ground terminal 0. Then, as the energy stored in the panel capacitor Cp is recovered to the ground terminal 0 through the inductor L, the voltage of the Y electrode decreases from the voltage of 0V to the voltage of -Vs.

As such, during the sustain period, the modes 1 to 6 (M1 to M6) may be repeated the number of times corresponding to the weight of the corresponding subfield, so that the Vs voltage and the −Vs voltage may be alternately applied to the Y electrode. The transistors Sch and Scl and the transistors Yh and Yl of the selection circuit Scan IC may use a transistor having a breakdown voltage equal to 1/4 of the voltage applied to the Y electrode, that is, a Vs / 2 voltage. In addition, the transistors Ys, Ys, Yh, and Yl may also use transistors having a breakdown voltage of Vs.

Although generating driving waveforms according to the third embodiment of the present invention has been described above with reference to FIGS. 7A to 7F, the driving waveforms according to the first and second embodiments of the present invention may be generated using the circuit of FIG. 5. have.

Specifically, in the circuit of FIG. 5, when the source of the transistor Yg is connected to a power supply for supplying a Vs / 2 voltage, each of the capacitors Cst1 and Cst2 is charged with a Vs / 4 voltage when the transistor Ys is turned on. The sustain discharge pulses having the Vs voltage and the 0V voltage may be applied to the Y electrode through the same path as that shown in FIGS. 7A to 7F. At this time, the sustain discharge driving circuit 510 connected to the X electrode has the same structure as the sustain discharge driving circuit 410, and the sustain discharge driving circuit 510 applies a 0V voltage to the X electrode while the Vs voltage is applied to the Y electrode. The Vs voltage may be applied to the X electrode while the Vs voltage is applied to the Y electrode.

In the circuit of FIG. 5, when the drain of the transistor Ys is connected to a power supply for supplying the voltage Vs / 2, when the transistor Ys is turned on, each of the capacitors Cst1 and Cst2 is charged with the voltage Vs / 4, and FIG. The sustain discharge pulses having the voltage Vs / 2 and the voltage -Vs / 2 alternately may be applied to the Y electrode through the same path as those shown in FIG. 7F. At this time, the sustain discharge driving circuit 510 connected to the X electrode has the same structure as the sustain discharge driving circuit 410, and the sustain discharge driving circuit 510 alternates the Vs / 2 voltage and the -Vs / 2 voltage to the X electrode. The branch may apply the sustain discharge pulse in a phase opposite to that of the sustain discharge pulse applied to the Y electrode.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, a transistor with low breakdown voltage can be used in the sustain discharge drive circuit.

Claims (18)

A plurality of first electrodes, A first transistor having a first end connected to a first power supply for supplying a first voltage, A second transistor having a first end connected to a second end of the first transistor and having a second end connected to a second power supply for supplying a second voltage lower than the first voltage; A first capacitor having a first end connected to a contact point of the first transistor and the second transistor, A second capacitor having a first end connected to a second end of the first capacitor, A charge path connected between the second power supply and a second end of the second capacitor, the charge path for charging the first and second capacitors when the first transistor is turned on; A plurality of third transistors each having a first end connected to the plurality of first electrodes, A plurality of fourth transistors each having a first end connected to the plurality of first electrodes, A fifth transistor connected between a second end of the plurality of third transistors and a first end of the first capacitor, A sixth transistor connected between a second end of the plurality of fourth transistors and a second end of the second capacitor, A rising path connected between second terminals of the plurality of third transistors and contacts of the first and second capacitors to increase voltages of the plurality of first electrodes, and And a falling path connected between second ends of the plurality of fourth transistors and contacts of the first and second capacitors to reduce voltages of the plurality of first electrodes. The method of claim 1, The charging path includes a first diode having a cathode connected to the second power supply and an anode connected to a second end of the second capacitor. The method of claim 2, An inductor having a first end connected to a contact point of the first and second capacitors, The rising path includes a second diode connected between a second end of the inductor and a second end of the third transistor, And the falling path includes a third diode connected between a second end of the inductor and a second end of the plurality of fourth transistors. The method of claim 2, The rising path includes a first inductor and a second diode connected in series between a contact point of the first and second capacitors and a second end of the plurality of third transistors, And the falling path includes a second inductor and a third diode connected in series between the contacts of the first and second capacitors and the second ends of the plurality of fourth transistors. The method according to any one of claims 1 to 4, The plasma display device having the same size as the first capacitor and the second capacitor. The method according to any one of claims 1 to 4, In a state in which the second and sixth transistors are turned on and a voltage corresponding to a difference between the second voltage and the voltage charged in the first and second capacitors is applied to the first electrode, After the sixth transistor is turned off and the third transistor is turned on to increase the voltage of the first electrode through the inductor; The second transistor is turned off and the first transistor is turned on to further increase the voltage of the first electrode through the inductor, And the fifth transistor is turned on to apply the first voltage to the first electrode. The method according to any one of claims 1 to 4, With the first, third and fifth transistors turned on to apply the first voltage to the first electrode, After the fourth transistor is turned on and the third transistor is turned off to reduce the voltage of the first electrode through the inductor; The second transistor is turned on and the first transistor is turned off to further reduce the voltage of the first electrode through the inductor, And a voltage corresponding to a difference between the second voltage and the voltage charged in the first and second capacitors is applied to the first electrode. The method according to any one of claims 1 to 4, And the second voltage is a ground voltage, and the first voltage is a positive voltage. The method according to any one of claims 1 to 4, And the first voltage and the second voltage are positive voltages, and the first voltage is a voltage larger than the second voltage. In the method for driving a plasma display device comprising a first electrode and a second electrode, Applying a fourth voltage to the first electrode through a first power supply for supplying a first voltage and first and second capacitors respectively charging a second voltage and a third voltage, Increasing the voltage of the first electrode through a first resonant path including the first power source, the first capacitor, and the first inductor; Further increasing the voltage of the first electrode through a second power supply for supplying a fifth voltage higher than the first voltage and a second resonant path including the first capacitor and the first inductor; Applying the fifth voltage to the first electrode, Reducing the voltage of the first electrode through a third resonant path comprising a second inductor, the first capacitor and the second power source, and And further reducing the voltage of the first electrode through a fourth resonance path including the second inductor, the first capacitor, and the first power source. The method of claim 10, Each of the first and second resonant paths further includes a first transistor connected between the first electrode and the first inductor, And each of the third and fourth resonant paths further comprises a second transistor connected between the first electrode and the second inductor. The method of claim 11, The applying of the fifth voltage to the first electrode may further include charging the first and second capacitors with the second and third voltages through the second power supply, respectively. . The method according to any one of claims 10 to 12, And the first inductor and the second inductor are the same inductor. In the driving device of the plasma display device including a plurality of first electrodes and a plurality of second electrodes, A scan integrated circuit having first and second input terminals, an output terminal connected to the plurality of first electrodes, and sequentially applying a voltage of the second input terminal to the plurality of first electrodes during an address period; A first transistor having a first end connected to a first power supply for supplying a first voltage, A second transistor having a first end connected to a second end of the first transistor and having a second end connected to a second power supply for supplying a second voltage lower than the first voltage; A first capacitor charged with a third voltage and having a first end connected to a contact point of the first transistor and the second transistor, A second capacitor charged with a fourth voltage and having a first end connected to a second end of the first capacitor, A third transistor connected between a first input terminal of the scan integrated circuit and a first terminal of the first capacitor, A fourth transistor connected between the second input terminal of the scan integrated circuit and the second terminal of the second capacitor, A rising path connected between a first input terminal of the scan integrated circuit and a contact point of the first and second capacitors to increase voltages of the plurality of first electrodes, and And a falling path connected between a second input terminal of the scan integrated circuit and the contacts of the first and second capacitors to reduce voltages of the plurality of first electrodes. The method of claim 14, Further comprising: an inductor having a first end connected to the contacts of the first and second capacitors, The rising path includes a first diode connected between a second end of the inductor and a first input end of the scan integrated circuit, And the descending path includes a second diode coupled between the second end of the inductor and the second input end of the scan integrated circuit. The method of claim 14, The rising path includes a first inductor and a first diode connected in series between a contact point of a first and a second capacitor and a first input terminal of the scan integrated circuit, And the falling path includes a second inductor and a second diode connected in series between the contacts of the first and second capacitors and the second input terminal of the scan integrated circuit. The method according to any one of claims 14 to 16, In a state in which the second and fourth transistors are turned on to apply a fifth voltage through the first and second capacitors, The fourth transistor is turned off to increase the voltage of the first electrode through the rising path, The first transistor is turned on and the second transistor is turned off to further increase the voltage of the first electrode through the rising path; And the third transistor is turned on to apply the first voltage to the first electrode. The method according to any one of claims 14 to 16, In a state where the first and third transistors are turned on and the first voltage is applied to the first electrode, After the third transistor is turned off to reduce the voltage of the first electrode through the falling path, The second transistor is turned on and the first transistor is turned off to further reduce the voltage of the first electrode through the falling path, And the fourth transistor is turned on so that a fifth voltage is applied through the first and second capacitors.

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