KR20080040503A - Plasma display, and driving device and method thereof - Google Patents

Abstract

A plasma display apparatus and an apparatus and a method for driving the same are provided to reduce the cost of a circuit by using a transistor having a low withstanding voltage corresponding to difference between high and low level voltages of sustain discharge pulses. A first end of a first transistor(Yp1) is connected to a first source voltage for supplying a first voltage. A first end of a second transistor(Yp2) is connected to a second end of the first transistor and a second end thereof is connected to a second source voltage for supplying a second voltage lower than the first voltage. A first end of a third transistor(Yn2) is connected to a contact point between the second source voltage and the second end of the second transistor. A first end of a fourth transistor(Yn1) is connected to a second end of the third transistor and a second end thereof is connected to a third source voltage for supplying a third voltage lower than the second voltage. A first end of a first capacitor(C1) is connected to a contact point between the first source voltage and the first transistor and a second end thereof is connected to a contact point between first and second transistors. A first end of a second capacitor(C2) is connected to a contact point between the third source voltage and the fourth transistor and a second end thereof is connected to a contact point between third and fourth transistors. First ends of fifth and sixth transistors(Sch,Scl) are connected to first electrodes. Seventh and eighth transistors(YH,YL) are connected between the fifth transistor and the first capacitor, and the sixth transistor and the second capacitor. A first path connected between the second source voltage and the fourth transistor increases the voltage of the first electrodes. A second path connected between the second source voltage and the sixth transistor, decreases the voltage of the first electrodes.

Description

Plasma display device, driving device thereof and driving method thereof {PLASMA DISPLAY, AND DRIVING DEVICE AND METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 to 4 are diagrams illustrating driving waveforms of the plasma display device according to the first to third embodiments of the present invention, respectively.

FIG. 5 is a diagram illustrating a sustain discharge driving circuit of the scan electrode driver for generating the driving waveform of FIG. 4.

6 is a diagram illustrating signal timing of a sustain discharge driving circuit for generating the driving waveform of FIG. 4.

7A to 7D are diagrams illustrating operations of the sustain discharge driving circuit of FIG. 5 according to the signal timing of FIG. 6, respectively.

The present invention relates to a plasma display device, a drive device thereof and a drive method thereof.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size.

In the plasma display device, one field (1TV field) is divided into a plurality of subfields having respective weights and driven, and the gray level is displayed by a combination of the weights of the subfields in which the display operation occurs among the plurality of subfields. In the address period of each subfield, discharge cells to emit light and discharge cells not to emit light are selected by the address discharge, and the discharge cells to emit light selected in the sustain period are sustained and discharged for a period corresponding to the weight of the subfield to display an image do.

In particular, since the high level voltage and the low level voltage are alternately applied to the electrodes performing sustain discharge in the sustain period, the transistor for applying the high level voltage and the low level voltage corresponds to at least the difference between the high level voltage and the low level voltage. Should have a voltage withstand voltage. As a result, the transistor having a high breakdown voltage increases the cost of the sustain discharge driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device capable of using a low breakdown voltage transistor in a sustain discharge driving circuit, a driving device thereof, and a driving method thereof.

According to an aspect of the present invention, a plasma display device includes a plurality of first electrodes, a first transistor Yp1 having a first end connected to a first power source (3Vs / 4) for supplying a first voltage, and the first A second transistor Yp2 and the second terminal having a first end connected to a second end of the transistor and having a second end connected to a second power supply Vs / 2 for supplying a second voltage lower than the first voltage; A third transistor Yn2 having a first end connected to a power supply and a contact of a second end of the second transistor; a first end connected to a second end of the third transistor and lower than the second voltage; A fourth transistor Yn1 having a second end connected to a third power supply Vs / 4 for supplying three voltages, and a fourth voltage being charged, and a first end of which is a contact point between the first power supply and the first transistor; A first capacitor C1 and a fifth voltage connected to the first transistor and the second transistor, the second end of the first A second capacitor C2 charged with a voltage and having a first end connected to a contact point of the third power supply and the fourth transistor, and a second end connected to a contact point of the third transistor and the fourth transistor, A plurality of fifth transistors (Sch) each having a first end connected to the plurality of first electrodes, a plurality of sixth transistors (Scl) each having a first end connected to the plurality of first electrodes, and the plurality of A seventh transistor YH connected between a second end of the fifth transistor and a first end of the first capacitor, and connected between a second end of the plurality of sixth transistors and a first end of the second capacitor. A first path connected between the eighth transistor YL, the second power supply and the second ends of the plurality of fifth transistors, and increasing voltages of the plurality of first electrodes, and the second power supply; Second of the sixth transistors It is connected between, and a second path for decreasing the voltage of the plurality of first electrodes.

According to another feature of the present invention, there is provided a method of driving a plasma display device comprising a plurality of first electrodes and a scan integrated circuit having a first input end and a second input end and whose output end is connected to the first electrode. In this driving method, a third voltage (0V) is applied to the first electrode through a first capacitor that is charged with a first power supply for supplying a first voltage (Vs / 4) and a second voltage (Vs / 4). Making; Injecting energy stored in a second power supply that supplies a fourth voltage (Vs / 2) higher than the first voltage to the first electrode through a first input terminal of the scan integrated circuit to increase the voltage of the first electrode. step; The first voltage higher than the fifth voltage to the first electrode through a third power supply for supplying a fifth voltage (3Vs / 4) higher than the fourth voltage and a second capacitor charging the sixth voltage (Vs / 4). Applying seven voltages (Vs); And recovering energy stored in the first electrode to the second power source through a second input terminal of the scan integrated circuit to reduce the voltage of the first electrode.

According to still another feature of the present invention, a driving apparatus of a plasma display device including a plurality of first electrodes is provided. The driving device has first and second input terminals, and a plurality of first output terminals are connected to the plurality of first electrodes, respectively, and the voltage of the second input terminal during the address period corresponds to one of the plurality of first electrodes. A scan integrated circuit selectively applied to a first electrode, a first transistor connected between a first input terminal of the scan integrated circuit and a first terminal of the first capacitor, a second input terminal and a second capacitor of the scan integrated circuit A second transistor connected between a first end of the inductor, an inductor having a first end connected to the first and second input ends of the scan integrated circuit and a first power supply for supplying a first voltage connected to the second end, A third transistor connected between a second power supply for supplying a second voltage higher than the first voltage and the first power supply to apply a third voltage higher than the second voltage to the first electrode when turned on; And a fourth transistor connected between a third power supply for supplying a fourth voltage lower than a first voltage and the first power supply to apply a fifth voltage lower than the fourth voltage to the first electrode when turned on. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Including case. In addition, since the threshold voltage of the semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is very low, and thus the threshold voltage is regarded as 0V and approximated.

First, a plasma display device, a driving method thereof, and a driving device thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as "A electrodes") A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs to each other in the row direction (hereinafter, "X"). Electrodes ”(X1 to Xn) and scan electrodes (hereinafter referred to as“ Y electrodes ”) (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X and Y electrodes perform a display operation for displaying an image in the sustain period. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 12. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes an address period and a sustain period.

The address electrode driver 300 receives an A electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each A electrode.

The scan electrode driver 400 receives a Y electrode driving control signal from the controller 200 and applies a driving voltage to the Y electrode.

The sustain electrode driver 500 receives the X electrode driving control signal from the controller 200 and applies a driving voltage to the X electrode.

Next, a driving waveform of the plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4. In the following description, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described.

2 and 3 are diagrams illustrating driving waveforms of the plasma display device according to the first and second exemplary embodiments of the present invention, respectively. 2 and 3 show only drive waveforms in the sustain period.

As shown in Fig. 2, in the sustain period, a sustain discharge pulse having a high level voltage (Vs voltage) and a low level voltage (0 V voltage) is applied to the Y electrode and the X electrode in an opposite phase. Such sustain discharge pulses are repeatedly applied to the Y electrode and the X electrode as many times as the number corresponding to the weight indicated by the corresponding subfield. That is, 0 V is applied to the X electrode when the Vs voltage is applied to the Y electrode, and 0 V is applied to the Y electrode when the Vs voltage is applied to the X electrode. In this way, the voltage difference between each Y electrode and each X electrode alternates between the Vs voltage and the -Vs voltage, so that the sustain discharge is repeated a predetermined number of times in the discharge cell to be turned on.

Unlike FIG. 2, in FIG. 3, a sustain discharge pulse having a high level voltage (Vs / 2 voltage) and a low level voltage (−Vs / 2 voltage) is alternately applied to the Y electrode and the X electrode in a sustain period. It may be. In this case, -Vs / 2 voltage is applied to the X electrode when the Vs / 2 voltage is applied to the Y electrode, and -Vs / 2 voltage is applied to the Y electrode when the Vs / 2 voltage is applied to the X electrode. Even in this manner, similarly to the sustain discharge pulse of FIG. 2, the voltage difference between the X electrode and the Y electrode may alternately have a Vs voltage and a -Vs voltage.

Meanwhile, in the first and second embodiments of the present invention, the case where the sustain discharge pulse having the high level voltage and the low level voltage are alternately applied to the X electrode and the Y electrode in the opposite phase has been described. The sustain discharge pulse may be applied to only one of the Y electrodes. Hereinafter, this embodiment will be described in detail with reference to FIG. 4.

4 illustrates a driving waveform of a plasma display device according to a third exemplary embodiment of the present invention.

First, as shown in FIG. 4, in the sustain period, a sustain discharge pulse having a voltage of Vs and a voltage of -Vs is applied to the Y electrode while the voltage of 0V is applied to the X electrode. In this manner, the voltage difference between the X electrode and the Y electrode may alternately have a Vs voltage and a -Vs voltage, similarly to the sustain discharge pulse of FIG. 2.

Next, with reference to FIG. 5, the drive circuit which produces | generates the drive waveform of FIG. 2 is demonstrated in detail.

5 is a diagram illustrating a sustain discharge driving circuit of the scan electrode driver 400 for generating the driving waveform of FIG. 2.

5 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 4. In FIG. 5, only the sustain discharge driving circuit 410 connected to the plurality of Y electrodes Y1 to Yn is illustrated for convenience of description, and the sustain discharge driving circuit 410 is formed in the scan electrode driver 400 of FIG. 1. Can be. Since the 0V voltage is applied to the X electrodes X1 to Xn during the sustain period, the plurality of X electrodes X1 to Xn are connected to the ground terminal 0 which supplies the ground voltage 0V. Meanwhile, in the driving waveforms of FIGS. 2 and 3, the sustain discharge driving circuit having the same structure as the sustain discharge driving circuit 410 of FIG. 5 may be connected to the plurality of X electrodes. In the sustain discharge driving circuit 410, only one X electrode and one Y electrode are illustrated for convenience of description, and a capacitive component formed by the X electrode and the Y electrode is illustrated as a panel capacitor Cp.

5 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 4.

As shown in FIG. 5, the sustain discharge driving circuit 410 includes transistors Yp1, Yp2, Yn1, Yn2, YH, YL, capacitors C1, C2, inductor Ly, and a scan integrated circuit. 411). At this time, the scanning IC 411 includes transistors Sch and Scl. In FIG. 5, transistors Yp1, Yp2, Yn1, Yn2, YH, YL, Sch, and Scl are shown as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors, and these transistors Yp1, Yp2, Yn1, Yn2, YH, YL, Sch, and Scl) may be formed with a body diode in the direction from the source to the drain. And other transistors having similar functions in place of the NMOS transistors may be used as these transistors Yp1, Yp2, Yn1, Yn2, YH, YL, Sch, Scl. In FIG. 5, transistors Yp1, Yp2, Yn1, Yn2, YH, YL, Sch, and Scl are shown as one transistor, respectively. However, transistors Yp1, Yp2, Yn1, Yn2, YH, YL, Sch, and Scl Each may be formed of a plurality of transistors connected in parallel.

Referring to FIG. 5, the scan IC 411 has a first input terminal and a second input terminal, and an output terminal is connected to the Y electrode of the panel capacitor Cp. The scan IC 411 selectively applies the voltage at the first input terminal and the voltage at the second input terminal to the corresponding Y electrodes in order to select a cell to be turned on in the address period. Although one Y electrode is connected to the scan IC 411 in FIG. 5, the scan IC 411 may have a plurality of output terminals. That is, the plurality of Y electrodes Y1 to Yk may be connected to the plurality of output terminals of the scan IC 411. In this case, when the number of output terminals of the scanning IC 411 is smaller than the number of the Y electrodes Y1 to Yn, the plurality of scanning ICs 411 may be used.

The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode of the panel capacitor Cp. A source of the transistor YH and a cathode of the diode D3 are connected to a first input terminal of the scanning IC 411, and a drain of the transistor YL and an anode of the diode D4 are connected to a second input terminal of the scanning IC 411. Is connected.

The drain of the transistor Yp1 is connected to the drain of the transistor YH and the power supply 3Vs / 4 which supplies a 3Vs / 4 voltage, and the source of the transistor Yp2 whose drain is connected to the source of the transistor Yp1. Is connected to a power supply (Vs / 2) which supplies a Vs / 2 voltage.

In addition, a source of the transistor Yn1 is connected to a source of the transistor YL and a power supply Vs / 4 for supplying a Vs / 4 voltage, and a transistor Yn2 having a source connected to the drain of the transistor Yn1. The source of is connected to the power supply (Vs / 2).

The first end of the capacitor C1 is connected to the contact point of the power supply 3Vs / 4 and the transistor YH, and the second end of the capacitor C1 is connected to the contact point of the transistor Yp1 and Yp2. It is connected. Similarly, the first end of the capacitor C2 is connected to the contacts of the power supply Vs / 4 and the transistor YL, and the second end of the capacitor C2 is connected to the contacts of the transistors Yn1 and Yn2. It is.

A power supply Vs / 2 for supplying a Vs / 2 voltage is connected between the transistor Yp2 and Yn2, and a second end of the inductor Ly connected to the power supply Vs / 2 is connected to a diode. It is connected to the contacts of the anode of D3 and the cathode of diode D4.

The anode of the diode D1 is connected to the power supply 3Vs / 4, and the cathode of the diode D1 is connected to the first end of the capacitor C1. Similarly, the anode of diode D2 is connected to the first end of capacitor C2, and the cathode of diode D2 is connected to power supply Vs / 4.

At this time, the transistors Yp1, Yp2, Yn1, Yn2 operate as switching means for selectively applying a Vs voltage or a 0V voltage to the first end of the capacitor C1 or the first end of the capacitor C2.

Next, the operation of the sustain discharge driving circuit 410 of FIG. 5 will be described in detail with reference to FIGS. 6 and 7A to 7D.

6 is a diagram illustrating signal timings of the sustain discharge driving circuit 410 for generating the driving waveform of FIG. 4, and FIGS. 7A to 7D illustrate operations of the sustain discharge driving circuit 410 according to the signal timing of FIG. 6, respectively. It is a diagram showing. Before mode 1 (M1) starts, transistor Yn2 is turned on to form a charge path that charges capacitor C2 to Vs / 4 voltage, whereby capacitor C2 charges to Vs / 4 voltage. Assume that it is.

6 and 7A, in the mode 1 M1, the transistor Yn2 is turned off, the transistors Yn1, YL, Scl are turned on, and as shown in FIG. 7A, the Y electrode of the panel capacitor Cp, 0V power is applied to the Y electrode through the path of the transistor Scl, transistor YL, capacitor C2, transistor Yn1 and power source Vs / 4 (1).

On the other hand, transistor Yp2 is turned on to form a path of power supply 3Vs / 4, diode D1, capacitor C1, transistor Yp2 and power supply Vs / 2 (2), and capacitor C1. ) Is charged with the voltage Vs / 4 corresponding to the difference between the voltages applied to the power source 3Vs / 4 and the power source Vs / 2.

At this time, since the drain of the transistor Yp1 is connected to the power supply 3Vs / 4, and the source voltage of the transistor Yp1 becomes the Vs / 2 voltage, the voltage difference between the both ends of the transistor Yp1 becomes the Vs / 4 voltage. . In addition, since the drain of the transistor Yn2 is connected to the power supply Vs / 2, and the source voltage of the transistor Yn2 becomes the Vs / 4 voltage, the voltage difference across the transistor Yn2 becomes the Vs / 4 voltage. Therefore, the transistors Yp1 and Yn2 can use transistors having a voltage resistance of Vs / 4.

In addition, since the drain of the transistor YH is connected to the power supply 3Vs / 4, and the source voltage of the transistor Sch becomes the 0V voltage, the voltage difference between the transistors YH and Sch becomes the 3Vs / 4 voltage. Therefore, the transistors YH and Sch may each use a transistor having a breakdown voltage of 3Vs / 8.

Subsequently, in the mode 2 M2, the transistors Yp2, Yn1, YL, Scl are turned off, and the transistor Sch is turned on, as shown in FIG. 7B, the power supply Vs / 2, the inductor Ly, and the diode. Resonance occurs in the path of the Y electrode of the transistor D3, the transistor Sch, and the panel capacitor Cp (3). At this time, since the voltage of the power supply Vs / 2 is applied to the first end of the inductor Ly and the voltage of 0 V is applied to the second end, the voltage applied to the Y electrode of the panel capacitor Cp through LC resonance. Increases from the 0V voltage to the Vs voltage.

Subsequently, the transistor Yp1 is turned on in the mode 3 M3 so that the power supply 3Vs / 4, the transistor Yp1, the capacitor C1, the transistor YH, and the transistor Sch are shown in FIG. 7C. And a Vs voltage is applied to the Y electrode through the path of the Y electrode of the panel capacitor Cp.

On the other hand, transistor Yn2 is turned on to form a path of power supply Vs / 2, transistor Yn2, capacitor C2, diode D2, and power supply Vs / 4 (5). The voltage Cs / 4 corresponding to the difference between the voltage applied to the Vs / 2 power supply and the power supply Vs / 4 is charged in the C2.

At this time, the drain voltage of the transistor Yp2 becomes the voltage of 3Vs / 4, and the source voltage of the transistor Yp2 is connected to the power supply Vs / 2, so that the voltage difference across the transistor Yp2 becomes the Vs / 4 voltage. In addition, since the drain voltage of the transistor Yn1 becomes the voltage Vs / 2, and the source of the transistor Yn1 is connected to the power supply Vs / 4, the voltage difference across the transistor Yn1 becomes the Vs / 4 voltage. Therefore, the transistors Yp2 and Yn1 may use transistors having a voltage resistance of Vs / 4.

In addition, since the drain voltage of the transistor Scl becomes the Vs voltage and the source voltage of the transistor YL becomes the Vs / 4 voltage, the voltage difference between the transistors YL and Scl becomes 3Vs / 8 voltage, respectively. Accordingly, the transistors YL and Scl may use transistors having a breakdown voltage of 3Vs / 8 respectively.

Next, in mode 4 M4, the transistors Yp1, Yn2, YH, and Sch are turned off, and the transistor Scl is turned on, as shown in FIG. 7D, the Y electrode and the transistor Scl of the panel capacitor Cp. The resonance occurs in the path of the diode D4, the inductor Ly and the power supply Vs / 2 (6). At this time, since the voltage of the power supply Vs / 2 is applied to the first end of the inductor Ly and the voltage of Vs is applied to the second end, the voltage applied to the Y electrode of the panel capacitor Cp through LC resonance. Drops from the Vs voltage to the 0V voltage.

As described above, according to the exemplary embodiment of the present invention, the transistors Yp1, Yp2, Yn1, and Yn2 are equal to 1/4 of the voltage corresponding to the difference between the high level voltage Vs and the low level voltage 0V of the sustain discharge pulse. Transistors having a corresponding Vs / 4 voltage withstand voltage can be used, and transistors YH, YL, Sch and Scl are voltages corresponding to the difference between the high level voltage Vs and the low level voltage 0V of the sustain discharge pulse. A transistor having a voltage of 3/8, i.e., a voltage of 3Vs / 8, can be used. In the sustain period, the modes 1 to 4 (M1 to M4) may be repeated as many times as the weight of the corresponding subfield to alternately apply the Vs voltage and the 0V voltage to the Y electrode.

Although generating driving waveforms according to the first embodiment of the present invention has been described above with reference to FIGS. 7A to 7D, the second and third embodiments of the present invention are described through the sustain discharge driving circuit 410 of FIG. 5. A corresponding drive waveform can also be generated.

Specifically, in the sustain discharge driving circuit 410 of FIG. 5, the drain of the transistor Yp1 is connected to the power supply Vs / 4 for supplying the Vs / 4 voltage, and the source of the transistor Yp2 and the transistor Yn2 are connected to each other. When the drain is connected to a power supply (0V) supplying a 0V power supply, and the source of the transistor Yn1 is connected to a power supply (-Vs / 4) supplying a voltage of -Vs / 4, the path shown in Figs. 7A to 7D is shown. A sustain discharge pulse as shown in FIG. 3 may be applied to the Y electrode alternately having a voltage of Vs / 2 and a voltage of -Vs / 2 through the same path.

In the sustain discharge driving circuit 410 of FIG. 5, the drain of the transistor Yp1 is connected to the power supply Vs / 2 supplying the Vs / 2 voltage, and the source of the transistor Yp2 and the drain of the transistor Yn2 are connected. Is connected to a power supply (0V) supplying a 0V power supply, and the source of the transistor Yn1 is connected to a power supply (-Vs / 2) supplying a voltage of -Vs / 2, and the path shown in FIGS. A sustain discharge pulse as shown in FIG. 4 may be applied to the Y electrode through the same path as shown in FIG. At this time, a 0V voltage is applied to the X electrode.

In addition, in the embodiment of the present invention, all transistors included in the current path have been described as being turned on. However, when the current path is formed through the body diode included in the transistor, the corresponding transistor may be turned off.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the transistor having a low breakdown voltage can be used in the sustain discharge driving circuit, the circuit cost can be reduced.

Claims (20)

A plurality of first electrodes, A first transistor having a first end connected to a first power supply for supplying a first voltage, A second transistor having a first end connected to a second end of the first transistor and having a second end connected to a second power supply for supplying a second voltage lower than the first voltage; A third transistor having a first end connected to a contact point of the second power supply and a second end of the second transistor, A fourth transistor having a first end connected to a second end of the third transistor and having a second end connected to a third power supply for supplying a third voltage lower than the second voltage; A first capacitor charged with a fourth voltage and having a first end connected to a contact point of the first power supply and the first transistor, and a second end connected to a contact point of the first transistor and the second transistor, A second capacitor charged with a fifth voltage and having a first end connected to a contact point of the third power supply and the fourth transistor, and a second end connected to a contact point of the third transistor and the fourth transistor, A plurality of fifth transistors each having a first end connected to the plurality of first electrodes, A plurality of sixth transistors each having a first end connected to the plurality of first electrodes, A seventh transistor connected between a second end of the plurality of fifth transistors and a first end of the first capacitor, An eighth transistor connected between a second end of the sixth transistor and a first end of the second capacitor, A first path connected between the second power supply and a second terminal of the plurality of fifth transistors and increasing voltages of the plurality of first electrodes, and A second path connected between the second power supply and a second terminal of the plurality of sixth transistors to reduce voltages of the plurality of first electrodes; Plasma display device comprising a. The method of claim 1, And an inductor connected between the second power supply and second ends of the plurality of fifth and sixth transistors. The method of claim 2, The first path is, And a first diode having an anode connected to the inductor and a cathode connected to a second terminal of the plurality of fifth transistors. The method of claim 2, The second path is, And a second diode having a cathode connected to the inductor and an anode connected to the second ends of the sixth transistors. The method according to claim 1 or 4, The fourth, sixth, and eighth transistors are turned on for a first period, the sixth transistor is turned on for a second period, and the first, fifth, and seventh transistors are over a third period of time. To turn on and set the sixth transistor to the turned on state for the fourth period Plasma display device further comprising. The method of claim 5, In the first period, the second transistor is turned on to charge the first capacitor with the fourth voltage, And in the third period, the third transistor is turned on to charge the second capacitor to the fifth voltage. The method of claim 6, The fourth voltage is a voltage corresponding to the difference between the first voltage and the second voltage. And the fifth voltage is a voltage corresponding to a voltage difference between the second voltage and the third voltage. The method of claim 7, wherein The plasma display device having the same size as the first capacitor and the second capacitor. The method of claim 5, A third diode having an anode connected to a contact point of the first power supply and the first transistor and a cathode connected to a first end of the first capacitor, And a fourth diode having a cathode connected to a contact point of the third power supply and the fourth transistor and an anode connected to a first end of the second capacitor. The method of claim 5, And the first voltage, the second voltage, and the third voltage have a positive voltage level. The method of claim 5, Wherein the first voltage is a positive voltage, the second voltage is a ground voltage, and the third voltage is a negative voltage. A method of driving a plasma display device comprising a plurality of first electrodes and a scan integrated circuit having a first input terminal and a second input terminal and having an output terminal connected to the first electrode. Applying a third voltage to the first electrode through a first capacitor supplying a first voltage and a second voltage supplying a first voltage; Injecting energy stored in a second power supply that supplies a fourth voltage higher than the first voltage to the first electrode through a first input terminal of the scan integrated circuit to increase the voltage of the first electrode; Applying a seventh voltage higher than the fifth voltage to the first electrode through a third power supply supplying a fifth voltage higher than the fourth voltage and a second capacitor charging the sixth voltage; And Reducing the voltage of the first electrode by recovering the energy stored in the first electrode to the second power source through a second input terminal of the scan integrated circuit; Method of driving a plasma display device comprising a. The method of claim 12, The third voltage is applied to the first electrode through the second input terminal of the scan integrated circuit, and the seventh voltage is applied to the first electrode through the first input terminal of the scan integrated circuit. Way. The method of claim 13, Applying the third voltage to the first electrode, And charging the sixth voltage to the second capacitor through the third power source. The method of claim 13, Applying the seventh voltage to the first electrode, And charging the first voltage to the first capacitor through the second power supply. The method according to any one of claims 12 to 15, And a voltage of the first electrode is increased through an inductor connected to the first electrode and is reduced through the inductor. In the driving device of the plasma display device including a plurality of first electrodes, And a plurality of first output terminals are respectively connected to the plurality of first electrodes, and the voltage of the second input terminal is connected to a corresponding first electrode of the plurality of first electrodes during an address period. Scanning integrated circuits that selectively apply; A first transistor connected between a first input end of the scan integrated circuit and a first end of a first capacitor, A second transistor connected between the second input end of the scan integrated circuit and the first end of a second capacitor, An inductor having a first end connected to first and second input ends of the scan integrated circuit and a first power supply for supplying a first voltage connected to a second end; A third transistor connected between a second power supply for supplying a second voltage higher than the first voltage and the first power supply to apply a third voltage higher than the second voltage to the first electrode when turned on; and A fourth transistor connected between a third power supply for supplying a fourth voltage lower than the first voltage and the first power supply to apply a fifth voltage lower than the fourth voltage to the first electrode when turned on A driving device of the plasma display device comprising a. The method of claim 17, In the state where the fourth voltage is applied to the second end of the second capacitor, the second and fourth transistors are turned on to apply the fifth voltage to the first electrode. The voltage of the first electrode is increased from the fifth voltage to the third voltage through the first power supply and the first input terminal of the scan integrated circuit. In the state where the second voltage is applied to the second terminal of the first capacitor, the first and third transistors are turned on to apply a third voltage to the first electrode,  And a voltage of the first electrode is reduced from the third voltage to the fifth voltage through a second input terminal of the scan integrated circuit and the first power source. The method of claim 18, A fifth transistor is further disposed between the third transistor and the first power supply, and a voltage corresponding to a difference between the second voltage and the first voltage is charged in the first capacitor when the fifth transistor is turned on. Driving device of plasma display device. The method of claim 19, A sixth transistor is further included between the fourth transistor and the second power supply, and a voltage corresponding to the difference between the first voltage and the fourth voltage is charged in the second capacitor when the sixth transistor is turned on. Driving device of plasma display device.

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